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b43: fix calc_nrssi_slope

PATCH Superseded Stefano Brivio 2 participants 5 messages Nov 29, 2007 – Nov 30, 2007 Networking drivers (wireless)

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Stefano Brivio

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#0 lore raw

PATCH 1/1 b43: fix calc_nrssi_slope

Fix calc_nrssi_slope() which caused PHY TX errors on devices containing a 802.11a PHY. The code is synced to v4 specs and relevant registers are renamed accordingly.

Signed-off-by Stefano Brivio <[email protected]>

---

Michael, John,
this fixes a not-so-fatal error with bcm4309 and possibly other devices such as bcm4312 and bcm4319. I actually don't care that much about this getting to 2.6.24, it's up to you. This still needs testing on other devices, thanks.

---

drivers/net/wireless/b43/b43.h +9 -5
Index: wireless-2.6/drivers/net/wireless/b43/b43.h
===================================================================
@@ -72,11 +72,11 @@
 #define B43_MMIO_PIO4_BASE		0x330
 
 #define B43_MMIO_PHY_VER		0x3E0
-#define B43_MMIO_PHY_RADIO		0x3E2
+#define B43_MMIO_PHY_BBANDCFG		0x3E2
 #define B43_MMIO_PHY0			0x3E6
 #define B43_MMIO_ANTENNA		0x3E8
 #define B43_MMIO_CHANNEL		0x3F0
-#define B43_MMIO_CHANNEL_EXT		0x3F4
+#define B43_MMIO_PHY_TEST		0x3F4
 #define B43_MMIO_RADIO_CONTROL		0x3F6
 #define B43_MMIO_RADIO_DATA_HIGH	0x3F8
 #define B43_MMIO_RADIO_DATA_LOW		0x3FA

@@ -278,20 +278,21 @@ enum {
 #define B43_PHY_ILT_A_CTRL		0x0072
 #define B43_PHY_ILT_A_DATA1		0x0073
 #define B43_PHY_ILT_A_DATA2		0x0074
-#define B43_PHY_G_LO_CONTROL		0x0810
 #define B43_PHY_ILT_G_CTRL		0x0472
 #define B43_PHY_ILT_G_DATA1		0x0473
 #define B43_PHY_ILT_G_DATA2		0x0474
 #define B43_PHY_A_PCTL			0x007B
 #define B43_PHY_G_PCTL			0x0029
-#define B43_PHY_A_CRS			0x0029
 #define B43_PHY_RADIO_BITFIELD		0x0401
-#define B43_PHY_G_CRS			0x0429
 #define B43_PHY_NRSSILT_CTRL		0x0803
 #define B43_PHY_NRSSILT_DATA		0x0804
 
 /* RadioRegisters */
 #define B43_RADIOCTL_ID			0x01
+#define B43_RADIO_2050_RXCTL0		0x007A
+#define B43_RADIO_2050_TXCTL1		0x0052
+#define B43_RADIO_2050_PCTL		0x0043
+
 
 /* MAC Control bitfield */
 #define B43_MACCTL_ENABLED		0x00000001	/* MAC Enabled */

@@ -551,6 +552,9 @@ struct b43_phy {
 
 	/* PHY TX errors counter. */
 	atomic_t txerr_cnt;
+
+	/* Hardware power control enabled? */
+	bool pctl_en;
 };
 
 /* Data structures for DMA transmission, per 80211 core. */
drivers/net/wireless/b43/lo.c +5 -5
Index: wireless-2.6/drivers/net/wireless/b43/lo.c
===================================================================
@@ -563,7 +563,7 @@ struct lo_g_saved_values {
 	u16 phy_rfoverval;
 	u16 phy_classctl;
 	u16 phy_base_3E;
-	u16 phy_crs0;
+	u16 phy_crs;
 	u16 phy_pgactl;
 	u16 phy_base_2A;
 	u16 phy_syncctl;

@@ -619,13 +619,13 @@ static void lo_measure_setup(struct b43_
 		sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
 		sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
 		sav->phy_base_3E = b43_phy_read(dev, B43_PHY_BASE(0x3E));
-		sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
+		sav->phy_crs = b43_phy_read(dev, B43_PHY_CRS);
 
 		b43_phy_write(dev, B43_PHY_CLASSCTL,
 			      b43_phy_read(dev, B43_PHY_CLASSCTL)
 			      & 0xFFFC);
-		b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
-			      & 0x7FFF);
+		b43_phy_write(dev, B43_PHY_CRS, b43_phy_read(dev, B43_PHY_CRS)
+			      & ~B43_PHY_CRS_EN_ALL);
 		b43_phy_write(dev, B43_PHY_ANALOGOVER,
 			      b43_phy_read(dev, B43_PHY_ANALOGOVER)
 			      | 0x0003);

@@ -766,7 +766,7 @@ static void lo_measure_restore(struct b4
 		b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
 		b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
 		b43_phy_write(dev, B43_PHY_BASE(0x3E), sav->phy_base_3E);
-		b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
+		b43_phy_write(dev, B43_PHY_CRS, sav->phy_crs);
 	}
 	if (b43_has_hardware_pctl(phy)) {
 		tmp = (sav->phy_lo_mask & 0xBFFF);
drivers/net/wireless/b43/main.c +3 -0
Index: wireless-2.6/drivers/net/wireless/b43/main.c
===================================================================
@@ -2271,6 +2271,9 @@ static int b43_chip_init(struct b43_wlde
 	/* PHY TX errors counter. */
 	atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
 
+	/* Hardware power control status flag. */
+	phy->pctl_en = 0;
+
 	err = 0;
 	b43dbg(dev->wl, "Chip initialized\n");
 out:
drivers/net/wireless/b43/phy.c +150 -153

519 lines not on this page · raw message

drivers/net/wireless/b43/phy.h +9 -2
Index: wireless-2.6/drivers/net/wireless/b43/phy.h
===================================================================
@@ -29,8 +29,9 @@ struct b43_phy;
 #define B43_PHY_LNAHPFCTL		B43_PHY_OFDM(0x1C)	/* LNA/HPF control */
 #define B43_PHY_LPFGAINCTL		B43_PHY_OFDM(0x20)	/* LPF Gain control */
 #define B43_PHY_ADIVRELATED		B43_PHY_OFDM(0x27)	/* FIXME rename */
-#define B43_PHY_CRS0			B43_PHY_OFDM(0x29)	/* Collision resolution signaling */
-#define  B43_PHY_CRS0_EN		0x8000	/* CRS enable */
+#define B43_PHY_CRS			B43_PHY_OFDM(0x29)	/* Collision resolution signaling */
+#define  B43_PHY_CRS_EN_ALL		0x8000			/* CRS enable */
+#define  B43_PHY_CRS_EN_0		0x4000			/* CRS 0 enable */
 #define B43_PHY_PEAK_COUNT		B43_PHY_OFDM(0x30)
 #define B43_PHY_ANTDWELL		B43_PHY_OFDM(0x2B)	/* Antenna dwell */
 #define  B43_PHY_ANTDWELL_AUTODIV1	0x0100	/* Automatic RX diversity start antenna */

@@ -78,11 +79,14 @@ struct b43_phy;
 /* CCK (B) PHY Registers */
 #define B43_PHY_VERSION_CCK		B43_PHY_BASE(0x00)	/* Versioning register for B-PHY */
 #define B43_PHY_CCKBBANDCFG		B43_PHY_BASE(0x01)	/* Contains antenna 0/1 control bit */
+#define B43_PHY_TR_LT2			B43_PHY_BASE(0x14)	/* TR lookup table 2 */
 #define B43_PHY_PGACTL			B43_PHY_BASE(0x15)	/* PGA control */
 #define  B43_PHY_PGACTL_LPF		0x1000	/* Low pass filter (?) */
 #define  B43_PHY_PGACTL_LOWBANDW	0x0040	/* Low bandwidth flag */
 #define  B43_PHY_PGACTL_UNKNOWN		0xEFA0
 #define B43_PHY_FBCTL1			B43_PHY_BASE(0x18)	/* Frequency bandwidth control 1 */
+#define B43_PHY_TXDC_OFFSET1		B43_PHY_BASE(0x2E)
+#define B43_PHY_TXDC_OFFSET2		B43_PHY_BASE(0x2F)
 #define B43_PHY_ITSSI			B43_PHY_BASE(0x29)	/* Idle TSSI */
 #define B43_PHY_LO_LEAKAGE		B43_PHY_BASE(0x2D)	/* Measured LO leakage */
 #define B43_PHY_ENERGY			B43_PHY_BASE(0x33)	/* Energy */

@@ -92,7 +96,10 @@ struct b43_phy;
 #define B43_PHY_RCCALOVER		B43_PHY_BASE(0x78)	/* RC calibration override */
 
 /* Extended G-PHY Registers */
+#define B43_PHY_G_CTL			B43_PHY_EXTG(0x01)	/* G PHY control */
 #define B43_PHY_CLASSCTL		B43_PHY_EXTG(0x02)	/* Classify control */
+#define  B43_PHY_CLASSCTL_CCK		0x0001
+#define  B43_PHY_CLASSCTL_OFDM		0x0002
 #define B43_PHY_GTABCTL			B43_PHY_EXTG(0x03)	/* G-PHY table control (see below) */
 #define  B43_PHY_GTABOFF		0x03FF	/* G-PHY table offset (see below) */
 #define  B43_PHY_GTABNR			0xFC00	/* G-PHY table number (see below) */
drivers/net/wireless/b43/wa.c +2 -2
Index: wireless-2.6/drivers/net/wireless/b43/wa.c
===================================================================
@@ -325,8 +325,8 @@ static void b43_wa_crs_ed(struct b43_wld
 
 static void b43_wa_crs_thr(struct b43_wldev *dev)
 {
-	b43_phy_write(dev, B43_PHY_CRS0,
-			(b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
+	b43_phy_write(dev, B43_PHY_CRS,
+			(b43_phy_read(dev, B43_PHY_CRS) & ~0x03C0) | 0xD000);
 }
 
 static void b43_wa_crs_blank(struct b43_wldev *dev)
Signature · 2 lines
Ciao
Stefano
author
#1 lore raw

PATCH v2 1/1 b43: fix calc_nrssi_slope

Fix calc_nrssi_slope() which caused PHY TX errors on devices containing a 802.11a PHY. The code is synced to v4 specs and relevant registers are renamed accordingly.

Signed-off-by Stefano Brivio <[email protected]>

---

Previous version introduced a duplicated flag and a redundant newline.

---

drivers/net/wireless/b43/b43.h +5 -5
Index: wireless-2.6/drivers/net/wireless/b43/b43.h
===================================================================
@@ -72,11 +72,11 @@
 #define B43_MMIO_PIO4_BASE		0x330
 
 #define B43_MMIO_PHY_VER		0x3E0
-#define B43_MMIO_PHY_RADIO		0x3E2
+#define B43_MMIO_PHY_BBANDCFG		0x3E2
 #define B43_MMIO_PHY0			0x3E6
 #define B43_MMIO_ANTENNA		0x3E8
 #define B43_MMIO_CHANNEL		0x3F0
-#define B43_MMIO_CHANNEL_EXT		0x3F4
+#define B43_MMIO_PHY_TEST		0x3F4
 #define B43_MMIO_RADIO_CONTROL		0x3F6
 #define B43_MMIO_RADIO_DATA_HIGH	0x3F8
 #define B43_MMIO_RADIO_DATA_LOW		0x3FA

@@ -278,20 +278,20 @@ enum {
 #define B43_PHY_ILT_A_CTRL		0x0072
 #define B43_PHY_ILT_A_DATA1		0x0073
 #define B43_PHY_ILT_A_DATA2		0x0074
-#define B43_PHY_G_LO_CONTROL		0x0810
 #define B43_PHY_ILT_G_CTRL		0x0472
 #define B43_PHY_ILT_G_DATA1		0x0473
 #define B43_PHY_ILT_G_DATA2		0x0474
 #define B43_PHY_A_PCTL			0x007B
 #define B43_PHY_G_PCTL			0x0029
-#define B43_PHY_A_CRS			0x0029
 #define B43_PHY_RADIO_BITFIELD		0x0401
-#define B43_PHY_G_CRS			0x0429
 #define B43_PHY_NRSSILT_CTRL		0x0803
 #define B43_PHY_NRSSILT_DATA		0x0804
 
 /* RadioRegisters */
 #define B43_RADIOCTL_ID			0x01
+#define B43_RADIO_2050_RXCTL0		0x007A
+#define B43_RADIO_2050_TXCTL1		0x0052
+#define B43_RADIO_2050_PCTL		0x0043
 
 /* MAC Control bitfield */
 #define B43_MACCTL_ENABLED		0x00000001	/* MAC Enabled */
drivers/net/wireless/b43/lo.c +5 -5
Index: wireless-2.6/drivers/net/wireless/b43/lo.c
===================================================================
@@ -563,7 +563,7 @@ struct lo_g_saved_values {
 	u16 phy_rfoverval;
 	u16 phy_classctl;
 	u16 phy_base_3E;
-	u16 phy_crs0;
+	u16 phy_crs;
 	u16 phy_pgactl;
 	u16 phy_base_2A;
 	u16 phy_syncctl;

@@ -619,13 +619,13 @@ static void lo_measure_setup(struct b43_
 		sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
 		sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
 		sav->phy_base_3E = b43_phy_read(dev, B43_PHY_BASE(0x3E));
-		sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
+		sav->phy_crs = b43_phy_read(dev, B43_PHY_CRS);
 
 		b43_phy_write(dev, B43_PHY_CLASSCTL,
 			      b43_phy_read(dev, B43_PHY_CLASSCTL)
 			      & 0xFFFC);
-		b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
-			      & 0x7FFF);
+		b43_phy_write(dev, B43_PHY_CRS, b43_phy_read(dev, B43_PHY_CRS)
+			      & ~B43_PHY_CRS_EN_ALL);
 		b43_phy_write(dev, B43_PHY_ANALOGOVER,
 			      b43_phy_read(dev, B43_PHY_ANALOGOVER)
 			      | 0x0003);

@@ -766,7 +766,7 @@ static void lo_measure_restore(struct b4
 		b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
 		b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
 		b43_phy_write(dev, B43_PHY_BASE(0x3E), sav->phy_base_3E);
-		b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
+		b43_phy_write(dev, B43_PHY_CRS, sav->phy_crs);
 	}
 	if (b43_has_hardware_pctl(phy)) {
 		tmp = (sav->phy_lo_mask & 0xBFFF);
drivers/net/wireless/b43/phy.c +149 -153

512 lines not on this page · raw message

drivers/net/wireless/b43/phy.h +9 -2
Index: wireless-2.6/drivers/net/wireless/b43/phy.h
===================================================================
@@ -29,8 +29,9 @@ struct b43_phy;
 #define B43_PHY_LNAHPFCTL		B43_PHY_OFDM(0x1C)	/* LNA/HPF control */
 #define B43_PHY_LPFGAINCTL		B43_PHY_OFDM(0x20)	/* LPF Gain control */
 #define B43_PHY_ADIVRELATED		B43_PHY_OFDM(0x27)	/* FIXME rename */
-#define B43_PHY_CRS0			B43_PHY_OFDM(0x29)	/* Collision resolution signaling */
-#define  B43_PHY_CRS0_EN		0x8000	/* CRS enable */
+#define B43_PHY_CRS			B43_PHY_OFDM(0x29)	/* Collision resolution signaling */
+#define  B43_PHY_CRS_EN_ALL		0x8000			/* CRS enable */
+#define  B43_PHY_CRS_EN_0		0x4000			/* CRS 0 enable */
 #define B43_PHY_PEAK_COUNT		B43_PHY_OFDM(0x30)
 #define B43_PHY_ANTDWELL		B43_PHY_OFDM(0x2B)	/* Antenna dwell */
 #define  B43_PHY_ANTDWELL_AUTODIV1	0x0100	/* Automatic RX diversity start antenna */

@@ -78,11 +79,14 @@ struct b43_phy;
 /* CCK (B) PHY Registers */
 #define B43_PHY_VERSION_CCK		B43_PHY_BASE(0x00)	/* Versioning register for B-PHY */
 #define B43_PHY_CCKBBANDCFG		B43_PHY_BASE(0x01)	/* Contains antenna 0/1 control bit */
+#define B43_PHY_TR_LT2			B43_PHY_BASE(0x14)	/* TR lookup table 2 */
 #define B43_PHY_PGACTL			B43_PHY_BASE(0x15)	/* PGA control */
 #define  B43_PHY_PGACTL_LPF		0x1000	/* Low pass filter (?) */
 #define  B43_PHY_PGACTL_LOWBANDW	0x0040	/* Low bandwidth flag */
 #define  B43_PHY_PGACTL_UNKNOWN		0xEFA0
 #define B43_PHY_FBCTL1			B43_PHY_BASE(0x18)	/* Frequency bandwidth control 1 */
+#define B43_PHY_TXDC_OFFSET1		B43_PHY_BASE(0x2E)
+#define B43_PHY_TXDC_OFFSET2		B43_PHY_BASE(0x2F)
 #define B43_PHY_ITSSI			B43_PHY_BASE(0x29)	/* Idle TSSI */
 #define B43_PHY_LO_LEAKAGE		B43_PHY_BASE(0x2D)	/* Measured LO leakage */
 #define B43_PHY_ENERGY			B43_PHY_BASE(0x33)	/* Energy */

@@ -92,7 +96,10 @@ struct b43_phy;
 #define B43_PHY_RCCALOVER		B43_PHY_BASE(0x78)	/* RC calibration override */
 
 /* Extended G-PHY Registers */
+#define B43_PHY_G_CTL			B43_PHY_EXTG(0x01)	/* G PHY control */
 #define B43_PHY_CLASSCTL		B43_PHY_EXTG(0x02)	/* Classify control */
+#define  B43_PHY_CLASSCTL_CCK		0x0001
+#define  B43_PHY_CLASSCTL_OFDM		0x0002
 #define B43_PHY_GTABCTL			B43_PHY_EXTG(0x03)	/* G-PHY table control (see below) */
 #define  B43_PHY_GTABOFF		0x03FF	/* G-PHY table offset (see below) */
 #define  B43_PHY_GTABNR			0xFC00	/* G-PHY table number (see below) */
drivers/net/wireless/b43/wa.c +2 -2
Index: wireless-2.6/drivers/net/wireless/b43/wa.c
===================================================================
@@ -325,8 +325,8 @@ static void b43_wa_crs_ed(struct b43_wld
 
 static void b43_wa_crs_thr(struct b43_wldev *dev)
 {
-	b43_phy_write(dev, B43_PHY_CRS0,
-			(b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
+	b43_phy_write(dev, B43_PHY_CRS,
+			(b43_phy_read(dev, B43_PHY_CRS) & ~0x03C0) | 0xD000);
 }
 
 static void b43_wa_crs_blank(struct b43_wldev *dev)
Signature · 2 lines
Ciao
Stefano
author
#2 lore raw

PATCH v3 1/1 b43: fix calc_nrssi_slope

Fix calc_nrssi_slope() which caused PHY TX errors on devices containing a 802.11a PHY. The code is synced to v4 specs and relevant registers are renamed accordingly.

Signed-off-by Stefano Brivio <[email protected]>

---

It looks like I got confused by a comment and used phy->hardware_power_control instead of b43_has_hardware_pctl() in order to check whether hardware based power control is enabled. Michael, I think that this comment:

	/* Hardware Power Control enabled? */
	bool hardware_power_control;

should at least be amended ("enabled by userspace" maybe would be better). But it's obviously up to you. Here comes the correct patch.

---

drivers/net/wireless/b43/phy.c +94 -98
Index: wireless-2.6/drivers/net/wireless/b43/phy.c
===================================================================
@@ -2664,77 +2664,68 @@ void b43_calc_nrssi_slope(struct b43_wld
 			b43_calc_nrssi_offset(dev);
 
 		b43_phy_write(dev, B43_PHY_CRS,
-			      b43_phy_read(dev, B43_PHY_CRS) & 0x7FFF);
-		b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
-		backup[7] = b43_read16(dev, 0x03E2);
-		b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
-		backup[0] = b43_radio_read16(dev, 0x007A);
-		backup[1] = b43_radio_read16(dev, 0x0052);
-		backup[2] = b43_radio_read16(dev, 0x0043);
-		backup[3] = b43_phy_read(dev, 0x0015);
+			      b43_phy_read(dev, B43_PHY_CRS)
+			       & ~B43_PHY_CRS_EN_ALL);
+		b43_phy_write(dev, B43_PHY_CLASSCTL,
+			      b43_phy_read(dev, B43_PHY_CLASSCTL) &
+			       ~(B43_PHY_CLASSCTL_CCK | B43_PHY_CLASSCTL_OFDM));
+		backup[7] = b43_read16(dev, B43_MMIO_PHY_BBANDCFG);
+		b43_write16(dev, B43_MMIO_PHY_BBANDCFG, backup[7] | 0x8000);
+		backup[0] = b43_radio_read16(dev, B43_RADIO_2050_RXCTL0);
+		backup[1] = b43_radio_read16(dev, B43_RADIO_2050_TXCTL1);
+		backup[2] = b43_radio_read16(dev, B43_RADIO_2050_PCTL);
+		backup[3] = b43_phy_read(dev, B43_PHY_PGACTL);
 		backup[4] = b43_phy_read(dev, 0x005A);
 		backup[5] = b43_phy_read(dev, 0x0059);
 		backup[6] = b43_phy_read(dev, 0x0058);
-		backup[8] = b43_read16(dev, 0x03E6);
+		backup[8] = b43_read16(dev, B43_MMIO_PHY0);
 		backup[9] = b43_read16(dev, B43_MMIO_PHY_TEST);
-		if (phy->rev >= 3) {
-			backup[10] = b43_phy_read(dev, 0x002E);
-			backup[11] = b43_phy_read(dev, 0x002F);
-			backup[12] = b43_phy_read(dev, 0x080F);
+		if (phy->pctl_en) {
+			backup[10] = b43_phy_read(dev, B43_PHY_TXDC_OFFSET1);
+			backup[11] = b43_phy_read(dev, B43_PHY_TXDC_OFFSET2);
+			backup[12] = b43_phy_read(dev, B43_PHY_LO_MASK);
 			backup[13] = b43_phy_read(dev, B43_PHY_LO_CTL);
-			backup[14] = b43_phy_read(dev, 0x0801);
-			backup[15] = b43_phy_read(dev, 0x0060);
-			backup[16] = b43_phy_read(dev, 0x0014);
-			backup[17] = b43_phy_read(dev, 0x0478);
-			b43_phy_write(dev, 0x002E, 0);
+			backup[14] = b43_phy_read(dev, B43_PHY_G_CTL);
+			backup[15] = b43_phy_read(dev, B43_PHY_DACCTL);
+			backup[16] = b43_phy_read(dev, B43_PHY_TR_LT2);
+			backup[17] = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL);
+			b43_phy_write(dev, B43_PHY_TXDC_OFFSET1, 0);
+			b43_phy_write(dev, B43_PHY_TXDC_OFFSET2, 0);
+			b43_phy_write(dev, B43_PHY_LO_MASK, 0);
 			b43_phy_write(dev, B43_PHY_LO_CTL, 0);
-			switch (phy->rev) {
-			case 4:
-			case 6:
-			case 7:
-				b43_phy_write(dev, 0x0478,
-					      b43_phy_read(dev, 0x0478)
-					      | 0x0100);
-				b43_phy_write(dev, 0x0801,
-					      b43_phy_read(dev, 0x0801)
-					      | 0x0040);
-				break;
-			case 3:
-			case 5:
-				b43_phy_write(dev, 0x0801,
-					      b43_phy_read(dev, 0x0801)
-					      & 0xFFBF);
-				break;
-			}
-			b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
-				      | 0x0040);
-			b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
-				      | 0x0200);
-		}
-		b43_radio_write16(dev, 0x007A,
-				  b43_radio_read16(dev, 0x007A) | 0x0070);
+			b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, 0);
+			b43_phy_write(dev, B43_PHY_G_CTL, 0);
+			b43_phy_write(dev, B43_PHY_DACCTL, 0);
+			b43_phy_write(dev, B43_PHY_TR_LT2, 0);
+		}
+		b43_radio_write16(dev, B43_RADIO_2050_RXCTL0,
+				  b43_radio_read16(dev, B43_RADIO_2050_RXCTL0)
+				   | 0x0070);
 		b43_set_all_gains(dev, 0, 8, 0);
-		b43_radio_write16(dev, 0x007A,
-				  b43_radio_read16(dev, 0x007A) & 0x00F7);
+		b43_radio_write16(dev, B43_RADIO_2050_RXCTL0,
+				  b43_radio_read16(dev, B43_RADIO_2050_RXCTL0)
+				   & 0x00F7);
 		if (phy->rev >= 2) {
-			b43_phy_write(dev, 0x0811,
-				      (b43_phy_read(dev, 0x0811) & 0xFFCF) |
-				      0x0030);
-			b43_phy_write(dev, 0x0812,
-				      (b43_phy_read(dev, 0x0812) & 0xFFCF) |
-				      0x0010);
+			b43_phy_write(dev, B43_PHY_RFOVER,
+				      b43_phy_read(dev, B43_PHY_RFOVER)
+				       | 0x0030);
+			b43_phy_write(dev, B43_PHY_RFOVERVAL,
+				      (b43_phy_read(dev, B43_PHY_RFOVERVAL)
+				       & 0xFFCF) | 0x0010);
 		}
-		b43_radio_write16(dev, 0x007A,
-				  b43_radio_read16(dev, 0x007A) | 0x0080);
+		b43_radio_write16(dev, B43_RADIO_2050_RXCTL0,
+				  b43_radio_read16(dev, B43_RADIO_2050_RXCTL0)
+				   | 0x0080);
 		udelay(20);
 
-		nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
+		nrssi0 = (s16)((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 		if (nrssi0 >= 0x0020)
 			nrssi0 -= 0x0040;
 
-		b43_radio_write16(dev, 0x007A,
-				  b43_radio_read16(dev, 0x007A) & 0x007F);
-		if (phy->rev >= 2) {
+		b43_radio_write16(dev, B43_RADIO_2050_RXCTL0,
+				  b43_radio_read16(dev, B43_RADIO_2050_RXCTL0)
+				   & 0x0080);
+		if (phy->analog >= 2) {
 			b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
 						    & 0xFF9F) | 0x0040);
 		}

@@ -2742,32 +2733,34 @@ void b43_calc_nrssi_slope(struct b43_wld
 		b43_write16(dev, B43_MMIO_PHY_TEST,
 			    b43_read16(dev, B43_MMIO_PHY_TEST)
 			    | 0x2000);
-		b43_radio_write16(dev, 0x007A,
-				  b43_radio_read16(dev, 0x007A) | 0x000F);
-		b43_phy_write(dev, 0x0015, 0xF330);
+		b43_radio_write16(dev, B43_RADIO_2050_RXCTL0,
+				  b43_radio_read16(dev, B43_RADIO_2050_RXCTL0)
+				   | 0x000F);
+		b43_phy_write(dev, B43_PHY_PGACTL, 0xF330);
 		if (phy->rev >= 2) {
-			b43_phy_write(dev, 0x0812,
-				      (b43_phy_read(dev, 0x0812) & 0xFFCF) |
-				      0x0020);
-			b43_phy_write(dev, 0x0811,
-				      (b43_phy_read(dev, 0x0811) & 0xFFCF) |
-				      0x0020);
+			b43_phy_write(dev, B43_PHY_RFOVERVAL,
+				      (b43_phy_read(dev, B43_PHY_RFOVERVAL)
+				       & 0xFFCF) | 0x0020);
+			b43_phy_write(dev, B43_PHY_RFOVER,
+				      (b43_phy_read(dev, B43_PHY_RFOVER)
+				       & 0xFFCF) | 0x0020);
 		}
-
 		b43_set_all_gains(dev, 3, 0, 1);
-		if (phy->radio_rev == 8) {
-			b43_radio_write16(dev, 0x0043, 0x001F);
-		} else {
-			tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
-			b43_radio_write16(dev, 0x0052, tmp | 0x0060);
-			tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
-			b43_radio_write16(dev, 0x0043, tmp | 0x0009);
+		if (phy->radio_rev == 8)
+			b43_radio_write16(dev, B43_RADIO_2050_PCTL, 0x001F);
+		else {
+			b43_radio_write16(dev, B43_RADIO_2050_TXCTL1,
+					  (b43_radio_read16(dev, B43_RADIO_2050_TXCTL1)
+					   & 0xFF0F) | 0x0060);
+			b43_radio_write16(dev, B43_RADIO_2050_PCTL,
+					  (b43_radio_read16(dev, B43_RADIO_2050_PCTL)
+					   & 0xFFF0) | 0x0009);
 		}
 		b43_phy_write(dev, 0x005A, 0x0480);
 		b43_phy_write(dev, 0x0059, 0x0810);
 		b43_phy_write(dev, 0x0058, 0x000D);
 		udelay(20);
-		nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
+		nrssi1 = (s16)((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 		if (nrssi1 >= 0x0020)
 			nrssi1 -= 0x0040;
 		if (nrssi0 == nrssi1)

@@ -2778,40 +2771,43 @@ void b43_calc_nrssi_slope(struct b43_wld
 			phy->nrssi[0] = nrssi1;
 			phy->nrssi[1] = nrssi0;
 		}
-		if (phy->rev >= 3) {
-			b43_phy_write(dev, 0x002E, backup[10]);
-			b43_phy_write(dev, 0x002F, backup[11]);
-			b43_phy_write(dev, 0x080F, backup[12]);
+		if (phy->pctl_en) {
+			b43_phy_write(dev, B43_PHY_TXDC_OFFSET1, backup[10]);
+			b43_phy_write(dev, B43_PHY_TXDC_OFFSET2, backup[11]);
+			b43_phy_write(dev, B43_PHY_LO_MASK, backup[12]);
 			b43_phy_write(dev, B43_PHY_LO_CTL, backup[13]);
 		}
+		b43_radio_write16(dev, B43_RADIO_2050_RXCTL0, backup[0]);
+		b43_write16(dev, B43_MMIO_PHY_BBANDCFG, backup[7]);
+		b43_phy_write(dev, B43_PHY_PGACTL, backup[3]);
 		if (phy->rev >= 2) {
-			b43_phy_write(dev, 0x0812,
-				      b43_phy_read(dev, 0x0812) & 0xFFCF);
-			b43_phy_write(dev, 0x0811,
-				      b43_phy_read(dev, 0x0811) & 0xFFCF);
+			b43_phy_write(dev, B43_PHY_RFOVERVAL,
+				      b43_phy_read(dev, B43_PHY_RFOVERVAL)
+				       & 0xFFCF);
+			b43_phy_write(dev, B43_PHY_RFOVERVAL,
+				      b43_phy_read(dev, B43_PHY_RFOVER)
+				       & 0xFFCF);
 		}
-
-		b43_radio_write16(dev, 0x007A, backup[0]);
-		b43_radio_write16(dev, 0x0052, backup[1]);
-		b43_radio_write16(dev, 0x0043, backup[2]);
-		b43_write16(dev, 0x03E2, backup[7]);
-		b43_write16(dev, 0x03E6, backup[8]);
+		b43_write16(dev, B43_MMIO_PHY0, backup[8]);
 		b43_write16(dev, B43_MMIO_PHY_TEST, backup[9]);
-		b43_phy_write(dev, 0x0015, backup[3]);
+		b43_radio_write16(dev, B43_RADIO_2050_TXCTL1, backup[1]);
+		b43_radio_write16(dev, B43_RADIO_2050_PCTL, backup[2]);
 		b43_phy_write(dev, 0x005A, backup[4]);
 		b43_phy_write(dev, 0x0059, backup[5]);
 		b43_phy_write(dev, 0x0058, backup[6]);
 		b43_synth_pu_workaround(dev, phy->channel);
-		b43_phy_write(dev, 0x0802,
-			      b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
+		b43_phy_write(dev, B43_PHY_CLASSCTL,
+			      b43_phy_read(dev, B43_PHY_CLASSCTL)
+			       | (B43_PHY_CLASSCTL_CCK | B43_PHY_CLASSCTL_OFDM));
 		b43_set_original_gains(dev);
 		b43_phy_write(dev, B43_PHY_CRS,
-			      b43_phy_read(dev, B43_PHY_CRS) | 0x8000);
-		if (phy->rev >= 3) {
-			b43_phy_write(dev, 0x0801, backup[14]);
-			b43_phy_write(dev, 0x0060, backup[15]);
-			b43_phy_write(dev, 0x0014, backup[16]);
-			b43_phy_write(dev, 0x0478, backup[17]);
+			      b43_phy_read(dev, B43_PHY_CRS)
+			       | B43_PHY_CRS_EN_ALL);
+		if (phy->pctl_en) {
+			b43_phy_write(dev, B43_PHY_G_CTL, backup[14]);
+			b43_phy_write(dev, B43_PHY_DACCTL, backup[15]);
+			b43_phy_write(dev, B43_PHY_TR_LT2, backup[16]);
+			b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, backup[17]);
 		}
 		b43_nrssi_mem_update(dev);
 		b43_calc_nrssi_threshold(dev);
Signature · 2 lines
Ciao
Stefano
author
#3 lore raw

PATCH v4 1/1 b43: fix calc_nrssi_slope

Fix calc_nrssi_slope() which caused PHY TX errors on devices containing a 802.11a PHY. The code is synced to v4 specs and relevant registers are renamed accordingly.

Signed-off-by Stefano Brivio <[email protected]>

---

Sorry, I inlined the wrong file. Hope this is the last retry. :)

---

drivers/net/wireless/b43/b43.h +5 -5
Index: wireless-2.6/drivers/net/wireless/b43/b43.h
===================================================================
@@ -72,11 +72,11 @@
 #define B43_MMIO_PIO4_BASE		0x330
 
 #define B43_MMIO_PHY_VER		0x3E0
-#define B43_MMIO_PHY_RADIO		0x3E2
+#define B43_MMIO_PHY_BBANDCFG		0x3E2
 #define B43_MMIO_PHY0			0x3E6
 #define B43_MMIO_ANTENNA		0x3E8
 #define B43_MMIO_CHANNEL		0x3F0
-#define B43_MMIO_CHANNEL_EXT		0x3F4
+#define B43_MMIO_PHY_TEST		0x3F4
 #define B43_MMIO_RADIO_CONTROL		0x3F6
 #define B43_MMIO_RADIO_DATA_HIGH	0x3F8
 #define B43_MMIO_RADIO_DATA_LOW		0x3FA

@@ -278,20 +278,20 @@ enum {
 #define B43_PHY_ILT_A_CTRL		0x0072
 #define B43_PHY_ILT_A_DATA1		0x0073
 #define B43_PHY_ILT_A_DATA2		0x0074
-#define B43_PHY_G_LO_CONTROL		0x0810
 #define B43_PHY_ILT_G_CTRL		0x0472
 #define B43_PHY_ILT_G_DATA1		0x0473
 #define B43_PHY_ILT_G_DATA2		0x0474
 #define B43_PHY_A_PCTL			0x007B
 #define B43_PHY_G_PCTL			0x0029
-#define B43_PHY_A_CRS			0x0029
 #define B43_PHY_RADIO_BITFIELD		0x0401
-#define B43_PHY_G_CRS			0x0429
 #define B43_PHY_NRSSILT_CTRL		0x0803
 #define B43_PHY_NRSSILT_DATA		0x0804
 
 /* RadioRegisters */
 #define B43_RADIOCTL_ID			0x01
+#define B43_RADIO_2050_RXCTL0		0x007A
+#define B43_RADIO_2050_TXCTL1		0x0052
+#define B43_RADIO_2050_PCTL		0x0043
 
 /* MAC Control bitfield */
 #define B43_MACCTL_ENABLED		0x00000001	/* MAC Enabled */
drivers/net/wireless/b43/lo.c +5 -5
Index: wireless-2.6/drivers/net/wireless/b43/lo.c
===================================================================
@@ -563,7 +563,7 @@ struct lo_g_saved_values {
 	u16 phy_rfoverval;
 	u16 phy_classctl;
 	u16 phy_base_3E;
-	u16 phy_crs0;
+	u16 phy_crs;
 	u16 phy_pgactl;
 	u16 phy_base_2A;
 	u16 phy_syncctl;

@@ -619,13 +619,13 @@ static void lo_measure_setup(struct b43_
 		sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
 		sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
 		sav->phy_base_3E = b43_phy_read(dev, B43_PHY_BASE(0x3E));
-		sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
+		sav->phy_crs = b43_phy_read(dev, B43_PHY_CRS);
 
 		b43_phy_write(dev, B43_PHY_CLASSCTL,
 			      b43_phy_read(dev, B43_PHY_CLASSCTL)
 			      & 0xFFFC);
-		b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
-			      & 0x7FFF);
+		b43_phy_write(dev, B43_PHY_CRS, b43_phy_read(dev, B43_PHY_CRS)
+			      & ~B43_PHY_CRS_EN_ALL);
 		b43_phy_write(dev, B43_PHY_ANALOGOVER,
 			      b43_phy_read(dev, B43_PHY_ANALOGOVER)
 			      | 0x0003);

@@ -766,7 +766,7 @@ static void lo_measure_restore(struct b4
 		b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
 		b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
 		b43_phy_write(dev, B43_PHY_BASE(0x3E), sav->phy_base_3E);
-		b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
+		b43_phy_write(dev, B43_PHY_CRS, sav->phy_crs);
 	}
 	if (b43_has_hardware_pctl(phy)) {
 		tmp = (sav->phy_lo_mask & 0xBFFF);
drivers/net/wireless/b43/phy.c +149 -153

512 lines not on this page · raw message

drivers/net/wireless/b43/phy.h +9 -2
Index: wireless-2.6/drivers/net/wireless/b43/phy.h
===================================================================
@@ -29,8 +29,9 @@ struct b43_phy;
 #define B43_PHY_LNAHPFCTL		B43_PHY_OFDM(0x1C)	/* LNA/HPF control */
 #define B43_PHY_LPFGAINCTL		B43_PHY_OFDM(0x20)	/* LPF Gain control */
 #define B43_PHY_ADIVRELATED		B43_PHY_OFDM(0x27)	/* FIXME rename */
-#define B43_PHY_CRS0			B43_PHY_OFDM(0x29)	/* Collision resolution signaling */
-#define  B43_PHY_CRS0_EN		0x8000	/* CRS enable */
+#define B43_PHY_CRS			B43_PHY_OFDM(0x29)	/* Collision resolution signaling */
+#define  B43_PHY_CRS_EN_ALL		0x8000			/* CRS enable */
+#define  B43_PHY_CRS_EN_0		0x4000			/* CRS 0 enable */
 #define B43_PHY_PEAK_COUNT		B43_PHY_OFDM(0x30)
 #define B43_PHY_ANTDWELL		B43_PHY_OFDM(0x2B)	/* Antenna dwell */
 #define  B43_PHY_ANTDWELL_AUTODIV1	0x0100	/* Automatic RX diversity start antenna */

@@ -78,11 +79,14 @@ struct b43_phy;
 /* CCK (B) PHY Registers */
 #define B43_PHY_VERSION_CCK		B43_PHY_BASE(0x00)	/* Versioning register for B-PHY */
 #define B43_PHY_CCKBBANDCFG		B43_PHY_BASE(0x01)	/* Contains antenna 0/1 control bit */
+#define B43_PHY_TR_LT2			B43_PHY_BASE(0x14)	/* TR lookup table 2 */
 #define B43_PHY_PGACTL			B43_PHY_BASE(0x15)	/* PGA control */
 #define  B43_PHY_PGACTL_LPF		0x1000	/* Low pass filter (?) */
 #define  B43_PHY_PGACTL_LOWBANDW	0x0040	/* Low bandwidth flag */
 #define  B43_PHY_PGACTL_UNKNOWN		0xEFA0
 #define B43_PHY_FBCTL1			B43_PHY_BASE(0x18)	/* Frequency bandwidth control 1 */
+#define B43_PHY_TXDC_OFFSET1		B43_PHY_BASE(0x2E)
+#define B43_PHY_TXDC_OFFSET2		B43_PHY_BASE(0x2F)
 #define B43_PHY_ITSSI			B43_PHY_BASE(0x29)	/* Idle TSSI */
 #define B43_PHY_LO_LEAKAGE		B43_PHY_BASE(0x2D)	/* Measured LO leakage */
 #define B43_PHY_ENERGY			B43_PHY_BASE(0x33)	/* Energy */

@@ -92,7 +96,10 @@ struct b43_phy;
 #define B43_PHY_RCCALOVER		B43_PHY_BASE(0x78)	/* RC calibration override */
 
 /* Extended G-PHY Registers */
+#define B43_PHY_G_CTL			B43_PHY_EXTG(0x01)	/* G PHY control */
 #define B43_PHY_CLASSCTL		B43_PHY_EXTG(0x02)	/* Classify control */
+#define  B43_PHY_CLASSCTL_CCK		0x0001
+#define  B43_PHY_CLASSCTL_OFDM		0x0002
 #define B43_PHY_GTABCTL			B43_PHY_EXTG(0x03)	/* G-PHY table control (see below) */
 #define  B43_PHY_GTABOFF		0x03FF	/* G-PHY table offset (see below) */
 #define  B43_PHY_GTABNR			0xFC00	/* G-PHY table number (see below) */
drivers/net/wireless/b43/wa.c +2 -2
Index: wireless-2.6/drivers/net/wireless/b43/wa.c
===================================================================
@@ -325,8 +325,8 @@ static void b43_wa_crs_ed(struct b43_wld
 
 static void b43_wa_crs_thr(struct b43_wldev *dev)
 {
-	b43_phy_write(dev, B43_PHY_CRS0,
-			(b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
+	b43_phy_write(dev, B43_PHY_CRS,
+			(b43_phy_read(dev, B43_PHY_CRS) & ~0x03C0) | 0xD000);
 }
 
 static void b43_wa_crs_blank(struct b43_wldev *dev)
Signature · 2 lines
Ciao
Stefano
#4 lore raw
Quoted 8 lines · On Thursday 29 November 2007 22:06:54 Stefano Brivio wrote:

Fix calc_nrssi_slope() which caused PHY TX errors on devices containing a 802.11a PHY. The code is synced to v4 specs and relevant registers are renamed accordingly.

Signed-off-by Stefano Brivio <[email protected]>

---

That patch looks good, though I did not test it, yet.

John, please don't apply this, yet. It needs a lot more testing on several different devices. In the past we had this kind of rewrite patches already improve one device and completely break another.

So, people, please try this and check if it causes any regressions.

Thanks.

Signature · 1 line
Greetings Michael.