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3430 clock: minor cleanup patches

PATCH In review Paul Walmsley 2 participants 6 messages Dec 4, 2007 – Dec 5, 2007

Subsystems (4)
Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP clock framework support
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Paul Walmsley

author maintainer
#0 lore raw

cover 3430 clock: minor cleanup patches

Hello,

These patches clean up a few minor issues with the OMAP3430 clock framework. They:

- ensure that the System Control Module is enabled at clock framework init;

- combine some redundant clksel_rate structures;

- add the ICR clock, present on both 3430ES versions in chassis mode; and

- resolve the "Enable for xxx without enable code" warnings that appear in 3430 bootlog.

Boot-tested on 3430ES1 SDP. Comments welcome.

- Paul

diffstat:

 arch/arm/mach-omap2/clock34xx.h |  128 +++++++++++++++++++++++-----------------
 1 file changed, 76 insertions(+), 52 deletions(-)

size:

text data bss dec hex filename

2885268  147008   96280 3128556  2fbcec vmlinux.3430sdp.orig
2885164  147088   96280 3128532  2fbcd4 vmlinux.3430sdp.patched
author maintainer
#1 lore raw

PATCH 1/4 3430 clock: 3430 clock: enable SCM clock at boot

As we do with 24xx, enable the System Control Module iclk at boot.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-omap2/clock34xx.h +1 -1
Index: linux-omap/arch/arm/mach-omap2/clock34xx.h
===================================================================
@@ -1337,7 +1337,7 @@
 	.parent		= &core_l4_ick,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP3430_EN_OMAPCTRL_SHIFT,
-	.flags		= CLOCK_IN_OMAP343X,
+	.flags		= CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
 	.recalc		= &followparent_recalc,
 };
author maintainer
#2 lore raw

PATCH 2/4 3430 clock: 3430 clock: combine div2_rates

In reply to Paul Walmsley

Several 3430 clocks have separate, identical clksel_rate structures that pass through the full parent rate, or divide it by 2 - combine these structures.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.h |   18 +++---------------
 1 file changed, 3 insertions(+), 15 deletions(-)
arch/arm/mach-omap2/clock34xx.h +3 -15
Index: linux-omap/arch/arm/mach-omap2/clock34xx.h
===================================================================
@@ -151,14 +151,14 @@
 	.recalc		= &omap2_clksel_recalc,
 };
 
-static const struct clksel_rate sys_osc_rates[] = {
+static const struct clksel_rate div2_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
 	{ .div = 0 }
 };
 
 static const struct clksel sys_clksel[] = {
-	{ .parent = &osc_sys_ck, .rates = sys_osc_rates },
+	{ .parent = &osc_sys_ck, .rates = div2_rates },
 	{ .parent = NULL }
 };
 

@@ -307,12 +307,6 @@
 	{ .div = 0 }
 };
 
-static const struct clksel_rate div2_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 0 },
-};
-
 static const struct clksel div2_dpll3m2_clksel[] = {
 	{ .parent = &dpll3_ck, .rates = div2_rates },
 	{ .parent = NULL }

@@ -1362,14 +1356,8 @@
 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
  * but l4_ick makes more sense to me */
 
-static const struct clksel_rate usb_l4_l4_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
-	{ .div = 0 }
-};
-
 static const struct clksel usb_l4_clksel[] = {
-	{ .parent = &l4_ick, .rates = usb_l4_l4_rates },
+	{ .parent = &l4_ick, .rates = div2_rates },
 	{ .parent = NULL },
 };
author maintainer
#3 lore raw

PATCH 3/4 3430 clock: Add missing ICR clock

In reply to Paul Walmsley

Add the 3430 clock for the ICR.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.h |   11 +++++++++++
 1 file changed, 11 insertions(+)
arch/arm/mach-omap2/clock34xx.h +11 -0
Index: linux-omap/arch/arm/mach-omap2/clock34xx.h
===================================================================
@@ -1125,6 +1125,16 @@
 	.recalc		= &followparent_recalc,
 };
 
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+	.name		= "icr_ick",
+	.parent		= &core_l4_ick,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+	.enable_bit	= OMAP3430_EN_ICR_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.recalc		= &followparent_recalc,
+};
+
 static struct clk aes2_ick = {
 	.name		= "aes2_ick",
 	.parent		= &core_l4_ick,

@@ -2265,6 +2275,7 @@
 	&security_l3_ick,
 	&pka_ick,
 	&core_l4_ick,
+	&icr_ick,
 	&aes2_ick,
 	&sha12_ick,
 	&des2_ick,
author maintainer
#4 lore raw

PATCH 4/4 3430 clock: Fix missing enable warnings from various clocks

In reply to Paul Walmsley

This patch marks all of the 3430 clocks that are missing enable information with either the ALWAYS_ENABLED or PARENT_CONTROLS_CLOCK clock flags, as deemed appropriate.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.h |   97 +++++++++++++++++++++++++---------------
 1 file changed, 61 insertions(+), 36 deletions(-)
arch/arm/mach-omap2/clock34xx.h +61 -36
Index: linux-omap/arch/arm/mach-omap2/clock34xx.h
===================================================================
@@ -223,7 +223,7 @@
 	.name		= "dpll1_ck",
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll1_dd,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.recalc		= &omap3_dpll_recalc,
 };
 

@@ -234,7 +234,8 @@
 static struct clk emu_mpu_alwon_ck = {
 	.name		= "emu_mpu_alwon_ck",
 	.parent		= &dpll1_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -259,7 +260,7 @@
 	.name		= "dpll2_ck",
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll2_dd,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.recalc		= &omap3_dpll_recalc,
 };
 

@@ -283,7 +284,7 @@
 	.name		= "dpll3_ck",
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll3_dd,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.recalc		= &omap3_dpll_recalc,
 };
 

@@ -324,14 +325,16 @@
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 	.clksel		= div2_dpll3m2_clksel,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 
 static struct clk core_ck = {
 	.name		= "core_ck",
 	.parent		= &dpll3_m2_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -342,14 +345,16 @@
 static struct clk dpll3_x2_ck = {
 	.name		= "dpll3_x2_ck",
 	.parent		= &core_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 
 static struct clk dpll3_m2x2_ck = {
 	.name		= "dpll3_m2x2_ck",
 	.parent		= &dpll3_x2_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -397,7 +402,7 @@
 	.name		= "dpll4_ck",
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll4_dd,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.recalc		= &omap3_dpll_recalc,
 };
 

@@ -408,7 +413,8 @@
 static struct clk dpll4_x2_ck = {
 	.name		= "dpll4_x2_ck",
 	.parent		= &dpll4_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
 

@@ -450,7 +456,8 @@
 static struct clk cm_96m_fck = {
 	.name		= "cm_96m_fck",
 	.parent		= &dpll4_m2x2_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -480,7 +487,7 @@
 
 static const struct clksel omap_54m_clksel[] = {
 	{ .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
-	{ .parent = &sys_altclk,     .rates = omap_54m_alt_rates },
+	{ .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 	{ .parent = NULL }
 };
 

@@ -490,7 +497,8 @@
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_54M,
 	.clksel		= omap_54m_clksel,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 

@@ -516,7 +524,8 @@
 	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 	.clksel_mask	= OMAP3430_SOURCE_48M,
 	.clksel		= omap_48m_clksel,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 

@@ -524,7 +533,8 @@
 	.name		= "omap_12m_fck",
 	.parent		= &omap_48m_fck,
 	.fixed_div	= 4,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_fixed_divisor_recalc,
 };
 

@@ -573,7 +583,8 @@
 static struct clk emu_per_alwon_ck = {
 	.name		= "emu_per_alwon_ck",
 	.parent		= &dpll4_m6x2_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -649,7 +660,8 @@
 static struct clk corex2_fck = {
 	.name		= "corex2_fck",
 	.parent		= &dpll3_m2x2_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -671,7 +683,8 @@
 	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,
 	.clksel		= div2_core_clksel,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 

@@ -682,7 +695,8 @@
 	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,
 	.clksel		= div2_core_clksel,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 

@@ -695,7 +709,8 @@
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_L3_MASK,
 	.clksel		= div2_core_clksel,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 

@@ -711,7 +726,8 @@
 	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_L4_MASK,
 	.clksel		= div2_l3_clksel,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 
 };

@@ -728,7 +744,7 @@
 	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 	.clksel_mask	= OMAP3430_CLKSEL_RM_MASK,
 	.clksel		= div2_l4_clksel,
-	.flags		= CLOCK_IN_OMAP343X,
+	.flags		= CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_clksel_recalc,
 };
 

@@ -940,7 +956,8 @@
 static struct clk core_48m_fck = {
 	.name		= "core_48m_fck",
 	.parent		= &omap_48m_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1012,7 +1029,8 @@
 static struct clk core_12m_fck = {
 	.name		= "core_12m_fck",
 	.parent		= &omap_12m_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1058,7 +1076,7 @@
 	.name		= "ssi_sst_fck",
 	.parent		= &ssi_ssr_fck,
 	.fixed_div	= 2,
-	.flags		= CLOCK_IN_OMAP343X,
+	.flags		= CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_fixed_divisor_recalc,
 };
 

@@ -1069,7 +1087,8 @@
 static struct clk core_l3_ick = {
 	.name		= "core_l3_ick",
 	.parent		= &l3_ick,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1094,7 +1113,7 @@
 static struct clk gpmc_fck = {
 	.name		= "gpmc_fck",
 	.parent		= &core_l3_ick,
-	.flags		= CLOCK_IN_OMAP343X,
+	.flags		= CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1103,7 +1122,8 @@
 static struct clk security_l3_ick = {
 	.name		= "security_l3_ick",
 	.parent		= &l3_ick,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1121,7 +1141,8 @@
 static struct clk core_l4_ick = {
 	.name		= "core_l4_ick",
 	.parent		= &l4_ick,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1391,7 +1412,8 @@
 static struct clk security_l4_ick2 = {
 	.name		= "security_l4_ick2",
 	.parent		= &l4_ick,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1533,7 +1555,7 @@
 static struct clk wkup_32k_fck = {
 	.name		= "wkup_32k_fck",
 	.parent		= &omap_32k_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1558,7 +1580,7 @@
 static struct clk wkup_l4_ick = {
 	.name		= "wkup_l4_ick",
 	.parent		= &sys_ck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1623,14 +1645,16 @@
 static struct clk per_96m_fck = {
 	.name		= "per_96m_fck",
 	.parent		= &omap_96m_alwon_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 
 static struct clk per_48m_fck = {
 	.name		= "per_48m_fck",
 	.parent		= &omap_48m_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1742,7 +1766,7 @@
 static struct clk per_32k_alwon_fck = {
 	.name		= "per_32k_alwon_fck",
 	.parent		= &omap_32k_fck,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1803,7 +1827,8 @@
 static struct clk per_l4_ick = {
 	.name		= "per_l4_ick",
 	.parent		= &l4_ick,
-	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+				PARENT_CONTROLS_CLOCK,
 	.recalc		= &followparent_recalc,
 };
maintainer
#5 lore raw
In reply to Paul Walmsley
Quoted 9 lines · Paul Walmsley

Hello,

These patches clean up a few minor issues with the OMAP3430 clock framework. They:

- ensure that the System Control Module is enabled at clock framework init;

- combine some redundant clksel_rate structures;

Quoted 7 lines

- add the ICR clock, present on both 3430ES versions in chassis mode; and

- resolve the "Enable for xxx without enable code" warnings that appear in 3430 bootlog.

Boot-tested on 3430ES1 SDP. Comments welcome.

Pushing today.

Tony