x86 intel_cacheinfo.c: cpu cache info entry for Intel Tolapai
PATCH 1/1 x86 intel_cacheinfo.c: cpu cache info entry for Intel Tolapai
This patch adds a cpu cache info entry for the Intel Tolapai cpu.
Signed-off-by Jason Gaston <[email protected]>
arch/x86/kernel/cpu/intel_cacheinfo.c renamed from arch/x86/kernel/cpu/intel_cacheinfo.c.orig +1 -0
@@ -49,6 +49,7 @@ { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */ { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */ { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */ + { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */ { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */ { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */ { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
Ingo Molnar
AppliedQuoted 1 line · Jason Gaston
This patch adds a cpu cache info entry for the Intel Tolapai cpu.
thanks, applied.
Ingo