Improve support for 4xx indirect DCRs
PATCH 2/21 Improve support for 4xx indirect DCRs
Accessing indirect DCRs is done via a pair of address/data DCRs.
Such accesses are thus inherently racy, vs. interrupts, preemption and possibly SMP if 4xx SMP cores are ever used.
This updates the mfdcri/mtdcri macros in dcr-native.h (which were so far unused) to use a spinlock.
In addition, add some common definitions to a new dcr-regs.h file.
Signed-off-by Benjamin Herrenschmidt <[email protected]>
---
include/asm-powerpc/dcr-native.h | 30 ++++++++++------ include/asm-powerpc/dcr-regs.h | 71 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 10 deletions(-)
include/asm-powerpc/dcr-native.h +20 -10
@@ -22,6 +22,8 @@#ifdef __KERNEL__#ifndef __ASSEMBLY__ +#include <linux/spinlock.h> +typedef struct {unsigned int base; }dcr_host_t ;
@@ -55,20 +57,28 @@ do { \ } while (0)/* R/W of indirect DCRs make use of standard naming conventions for DCRs */ -#define mfdcri (base, reg) \ -({ \ - mtdcr(base ## _CFGADDR, base ## _ ## reg); \ - mfdcr(base ## _CFGDATA); \ +extern spinlock_t dcr_ind_lock; + +#define mfdcri (base, reg) \ +({ \ + unsigned long flags; \ + unsigned int val; \ + spin_lock_irqsave(&dcr_ind_lock, flags); \ + mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \ + val = mfdcr(DCRN_ ## base ## _CONFIG_DATA); \ + spin_unlock_irqrestore(&dcr_ind_lock, flags); \ + val; \ }) -#define mtdcri (base, reg, data) \ -do { \ - mtdcr(base ## _CFGADDR, base ## _ ## reg); \ - mtdcr(base ## _CFGDATA, data); \ +#define mtdcri (base, reg, data) \ +do { \ + unsigned long flags; \ + spin_lock_irqsave(&dcr_ind_lock, flags); \ + mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \ + mtdcr(DCRN_ ## base ## _CONFIG_DATA, data); \ + spin_unlock_irqrestore(&dcr_ind_lock, flags); \ } while (0)#endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_DCR_NATIVE_H */ - -
include/asm-powerpc/dcr-regs.h new file +71 -0
71 lines not on this page · raw message