MPC8360E-RDK: Device tree and board file
PATCH 1/1 MPC8360E-RDK: Device tree and board file
This is new board made by Freescale Semiconductor Inc. and Logic Product Development.
Currently supported:
1. UEC1,2,7,4
2. I2C
3. SPI
4. NS16550 serial
5. PCI and miniPCI
6. Intel NOR StrataFlash X16 64Mbit PC28F640P30T85
Not supported so far:
1. StMICRO NAND512W3A2BN6E, 512 Mbit (supported with FSL UPM patches)
2. QE SCCs (slow UCCs, used as an UARTs)
3. ADC AD7843
4. FHCI USB
5. Graphics controller, Fujitsu MB86277
--- arch/powerpc/boot/dts/mpc836x_rdk.dts | 331 +++++++++++++++++++++++++++++ arch/powerpc/platforms/83xx/Kconfig | 11 +- arch/powerpc/platforms/83xx/Makefile | 1 + arch/powerpc/platforms/83xx/mpc836x_rdk.c | 118 ++++++++++ 4 files changed, 460 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/boot/dts/mpc836x_rdk.dts create mode 100644 arch/powerpc/platforms/83xx/mpc836x_rdk.c
arch/powerpc/boot/dts/mpc836x_rdk.dts new file +331 -0
@@ -0,0 +1,331 @@ +/* + * MPC8360E RDK Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * Copyright 2007 MontaVista Software, Inc. + * Anton Vorontsov <[email protected]> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "MPC8360ERDK", "MPC836xRDK", "MPC83xxRDK"; + model = "MPC8360RDK"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + pci0 = &pci0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8360@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* filled by u-boot */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + soc8360@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges = <0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + /* filled by u-boot */ + bus-frequency = <0>; + + wdt@200 { + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <16 8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + serial0: serial@4500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + interrupts = <9 8>; + interrupt-parent = <&ipic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + serial1: serial@4600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + interrupts = <10 8>; + interrupt-parent = <&ipic>; + /* filled by u-boot */ + clock-frequency = <0>; + }; + + crypto@30000 { + compatible = "fsl,sec2-crypto"; + reg = <0x30000 0x10000>; + interrupts = <11 8>; + interrupt-parent = <&ipic>; + num-channels = <4>; + channel-fifo-len = <24>; + exec-units-mask = <0x0000007e>; + /* + * desc mask is for rev1.x, we need runtime fixup + * for >=2.x + */ + descriptor-types-mask = <0x01010ebf>; + }; + + ipic: interrupt-controller@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + }; + + par_io@1400 { + compatible = "fsl,qe-pario"; + reg = <0x1400 0x100>; + num-ports = <7>; + }; + }; + + qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe"; + ranges = <0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + /* filled by u-boot */ + brg-frequency = <0>; + + muram@10000 { + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x00010000 0x0000c000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; + + spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "cpu-qe"; + }; + + spi@500 { + cell-index = <1>; + compatible = "fsl,spi"; + reg = <0x500 0x40>; + interrupts = <1>; + interrupt-parent = <&qeic>; + mode = "cpu-qe"; + }; + + usb@6c0 { + compatible = "qe_udc"; + reg = <0x6c0 0x40 0x8b00 0x100>; + interrupts = <11>; + interrupt-parent = <&qeic>; + mode = "slave"; + }; + + enet0: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + model = "UCC"; + device-id = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + rx-clock = <0>; + tx-clock = <25>; + phy-handle = <&phy2>; + phy-connection-type = "rgmii-id"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet1: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + model = "UCC"; + device-id = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + rx-clock = <0>; + tx-clock = <20>; + phy-handle = <&phy4>; + phy-connection-type = "rgmii-id"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet2: ucc@2600 { + device_type = "network"; + compatible = "ucc_geth"; + model = "UCC"; + device-id = <7>; + reg = <0x2600 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + rx-clock = <36>; + tx-clock = <35>; + phy-handle = <&phy1>; + phy-connection-type = "mii"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + enet3: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + model = "UCC"; + device-id = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + rx-clock = <24>; + tx-clock = <23>; + phy-handle = <&phy3>; + phy-connection-type = "mii"; + /* filled by u-boot */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + mdio@2120 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2120 0x18>; + compatible = "fsl,ucc-mdio"; + + phy1: ethernet-phy@1 { + compatible = "national,DP83848VV"; + reg = <1>; + device_type = "ethernet-phy"; + }; + + phy2: ethernet-phy@2 { + compatible = "broadcom,BCM5481UA2KMLG"; + reg = <2>; + device_type = "ethernet-phy"; + }; + + phy3: ethernet-phy@3 { + compatible = "national,DP83848VV"; + reg = <3>; + device_type = "ethernet-phy"; + }; + + phy4: ethernet-phy@4 { + compatible = "broadcom,BCM5481UA2KMLG"; + reg = <4>; + device_type = "ethernet-phy"; + }; + }; + + qeic: interrupt-controller@80 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "fsl,qe-pic"; + interrupt-controller; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8360-localbus", + "fsl,pq2pro-localbus"; + reg = <0xe0005000 0xd8>; + ranges = <0 0 0xff800000 0x800000>; + + nor-flash@0,0 { + compatible = "intel,PC28F640P30T85", "cfi-flash"; + reg = <0 0 0x800000>; + bank-width = <2>; + device-width = <1>; + }; + }; + + pci0: pci@e0008500 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; + reg = <0xe0008500 0x100>; + ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 + 0x42000000 0 0x80000000 0x80000000 0 0x10000000 + 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; + interrupts = <66 8>; + interrupt-parent = <&ipic>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */ + 0xa000 0 0 1 &ipic 18 8 + 0xa000 0 0 2 &ipic 19 8 + + /* PCI1 IDSEL 0x15 AD21 */ + 0xa800 0 0 1 &ipic 19 8 + 0xa800 0 0 2 &ipic 20 8 + 0xa800 0 0 3 &ipic 21 8 + 0xa800 0 0 4 &ipic 18 8>; + /* filled by u-boot */ + bus-range = <0 0>; + clock-frequency = <0>; + }; +};
arch/powerpc/platforms/83xx/Kconfig +10 -1
@@ -55,6 +55,15 @@ config MPC837x_MDS select DEFAULT_UIMAGE help This option enables support for the MPC837x MDS Processor Board. + +config MPC836x_RDK + bool "Freescale/Logic MPC836x RDK" + select DEFAULT_UIMAGE + select QUICC_ENGINE + help + This option enables support for the MPC836x RDK Processor Board, + also known as ZOOM PowerQUICC Kit. + endchoice config PPC_MPC831x
@@ -79,7 +88,7 @@ config PPC_MPC836x bool select PPC_UDBG_16550 select PPC_INDIRECT_PCI - default y if MPC836x_MDS + default y if MPC836x_MDS || MPC836x_RDK config PPC_MPC837x bool
arch/powerpc/platforms/83xx/Makefile +1 -0
@@ -10,3 +10,4 @@ obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o obj-$(CONFIG_MPC832x_MDS) += mpc832x_mds.o obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o +obj-$(CONFIG_MPC836x_RDK) += mpc836x_rdk.o
arch/powerpc/platforms/83xx/mpc836x_rdk.c new file +118 -0
118 lines not on this page · raw message
Signature · 1 line
1.5.2.2
Quoted 2 lines · On Fri, 21 Dec 2007 23:23:09 +0300 Anton Vorontsov <[email protected]>…
+static struct
of_device_idmpc836x_rdk_ids[] = {
Please make this __initdata.
Signature · 3 lines
Cheers, Stephen Rothwell [email protected] http://www.canb.auug.org.au/~sfr/
Quoted 1 line · Anton Vorontsov
2. QE SCCs (slow UCCs, used as an UARTs)
I a posted a driver that provides this support, I'm just waiting for Kumar to apply it.
What revision of the 8360 does this board use?
Quoted 6 lines · Timur Tabi
Quoted 1 line · Anton Vorontsov
2. QE SCCs (slow UCCs, used as an UARTs)
I a posted a driver that provides this support, I'm just waiting for Kumar to apply it.
Yup. I've seen it, thanks. I'm going to test it as well. ;-)
Quoted 1 line
What revision of the 8360 does this board use?
MPC8360E, Rev: 21. Are you aware of any known issues on this chip regarding UCC serials?
Signature · 4 lines
Anton Vorontsov email: [email protected] backup email: [email protected] irc://irc.freenode.net/bd2
Quoted 1 line · Anton Vorontsov
Yup. I've seen it, thanks. I'm going to test it as well. ;-)
If they work for you, please let Kumar know.
Quoted 2 lines
MPC8360E, Rev: 21. Are you aware of any known issues on this chip regarding UCC serials?
Yep. You need a microcode upload. My patches describe everything.
Quoted 5 lines · Timur Tabi
Quoted 1 line · Anton Vorontsov
Yup. I've seen it, thanks. I'm going to test it as well. ;-)
If they work for you, please let Kumar know.
Unfortunately they don't.
root@mpc8360erdk:~# echo abc > /dev/ttyQE0
And hang. No interrupts.
After ^C:ucc_uart e0102400.ucc: shutdown timeout
The same for ttyQE1 (just for testing I set it up to not use Soft-UART).
The same for loopback mode.
I wonder what are the symptoms if microcode is at fault? According to errata description, hang isn't something I should get on the transmit attempt.
Quoted 4 lines
Quoted 2 lines
MPC8360E, Rev: 21. Are you aware of any known issues on this chip regarding UCC serials?
Yep. You need a microcode upload. My patches describe everything.
Well. All I've found is: QERAMPTCH.zip ("RAM Microcode Patches for PowerQUICC II Pro Family QE Errata"), which should fix QE_UART5 errata for MPC8323 Rev 1.1. Can I assume it works for MPC8360 too? I've tried it. No luck.
Here are dts entries I use:
firmware {
id = "Soft-UART";
extended_modes = <0 0>;
virtual_traps = <0 0 0 0 0 0 0 0>;
};
ucc@2400 {
device_type = "serial";
compatible = "ucc_uart";
reg = <0x2400 0x200>;
device-id = <5>;
port-number = <0>;
rx-clock-name = "brg7";
tx-clock-name = "brg8";
interrupts = <40>;
interrupt-parent = <&qeic>;
soft-uart;
};
ucc@3400 {
device_type = "serial";
compatible = "ucc_uart";
reg = <0x3400 0x200>;
device-id = <6>;
port-number = <1>;
rx-clock-name = "brg14";
tx-clock-name = "brg14";
interrupts = <41>;
interrupt-parent = <&qeic>;
};Any ideas?
Thanks,
Signature · 4 lines
Anton Vorontsov email: [email protected] backup email: [email protected] irc://irc.freenode.net/bd2
Quoted 5 lines · Anton Vorontsov
Quoted 4 lines · Timur Tabi
Quoted 1 line · Anton Vorontsov
Yup. I've seen it, thanks. I'm going to test it as well. ;-)
Quoted 7 lines
Quoted 1 line
If they work for you, please let Kumar know.
Unfortunately they don't.
root@mpc8360erdk:~# echo abc > /dev/ttyQE0And hang. No interrupts.
I've just tried to set CD and CTS to GPIO functions (for loopbacking), as suggested in the ref manual.. and still it doesn't work. Hm..
Signature · 4 lines
Anton Vorontsov email: [email protected] backup email: [email protected] irc://irc.freenode.net/bd2
Quoted 3 lines · Anton Vorontsov
I wonder what are the symptoms if microcode is at fault? According to errata description, hang isn't something I should get on the transmit attempt.
Well, if the microcode fails, you'll never know. I tried to explain the need for a unified microcode validation mechanism to the QE microcode developers, but I didn't get very far.
Quoted 3 lines
Well. All I've found is: QERAMPTCH.zip ("RAM Microcode Patches for PowerQUICC II Pro Family QE Errata"), which should fix
QE_UART5errata for MPC8323 Rev 1.1.
I don't know what that is, but it doesn't apply. I'm talking about the QE and QE UART patches I've posted to this mailing list over the past month. Once Kumar applies them to them to his for-2.6.25 branch, it'll make life easier for everyone.
Can I assume it works for MPC8360 too?
No. Microcode is very sensitive to the processor and the revision. A microcode for 8360 2.1 won't work on 8360 2.0.
I forgot to give you the actual microcode. :-) I'll email it to you later.
Quoted 7 lines
Here are dts entries I use:
firmware { id = "Soft-UART"; extended_modes = <0 0>; virtual_traps = <0 0 0 0 0 0 0 0>; };
This entry is created by U-Boot only if it uploads the microcode. This should not be in the DTS.
Quoted 17 lines
ucc@2400 {
device_type = "serial";
compatible = "ucc_uart";
reg = <0x2400 0x200>;
device-id = <5>;
port-number = <0>;
rx-clock-name = "brg7";
tx-clock-name = "brg8";
interrupts = <40>;
interrupt-parent = <&qeic>;
soft-uart;
};
ucc@3400 {
device_type = "serial";
compatible = "ucc_uart";Quoted 8 lines
reg = <0x3400 0x200>; device-id = <6>; port-number = <1>; rx-clock-name = "brg14"; tx-clock-name = "brg14"; interrupts = <41>; interrupt-parent = <&qeic>; };
You need to have separate BRGs for TX and RX when using soft-uart mode, and you MUST use soft-uart mode on the 8360.
Quoted 10 lines · Timur Tabi
Quoted 3 lines · Anton Vorontsov
I wonder what are the symptoms if microcode is at fault? According to errata description, hang isn't something I should get on the transmit attempt.
Well, if the microcode fails, you'll never know. I tried to explain the need for a unified microcode validation mechanism to the QE microcode developers, but I didn't get very far.
Quoted 7 lines
Quoted 3 lines
Well. All I've found is: QERAMPTCH.zip ("RAM Microcode Patches for PowerQUICC II Pro Family QE Errata"), which should fix
QE_UART5errata for MPC8323 Rev 1.1.I don't know what that is, but it doesn't apply. I'm talking about the QE and QE UART patches I've posted to this mailing list over the past month.
:-) I didn't get it wrong. QERAMPTCH.zip is the microcode (they name it "microcode patches") I've tried, it has nothing to do with your Linux patches.
Quoted 9 lines
Once Kumar applies them to them to his for-2.6.25 branch, it'll make life easier for everyone.
Can I assume it works for MPC8360 too?
No. Microcode is very sensitive to the processor and the revision. A microcode for 8360 2.1 won't work on 8360 2.0.
I forgot to give you the actual microcode. :-) I'll email it to you later.
Much thanks! Also, could you provide the magic python script to generate binary firmwares to try loading fw from the linux? Or just a .bin file.
Quoted 10 lines
Quoted 7 lines
Here are dts entries I use:
firmware { id = "Soft-UART"; extended_modes = <0 0>; virtual_traps = <0 0 0 0 0 0 0 0>; };This entry is created by U-Boot only if it uploads the microcode. This should not be in the DTS.
Sure thing. That was just a quirk for the quick testing, to not tinker with u-boot part.
Quoted 26 lines
Quoted 17 lines
ucc@2400 { device_type = "serial"; compatible = "ucc_uart"; reg = <0x2400 0x200>; device-id = <5>; port-number = <0>; rx-clock-name = "brg7"; tx-clock-name = "brg8"; interrupts = <40>; interrupt-parent = <&qeic>; soft-uart; }; ucc@3400 { device_type = "serial"; compatible = "ucc_uart";Quoted 8 lines
reg = <0x3400 0x200>; device-id = <6>; port-number = <1>; rx-clock-name = "brg14"; tx-clock-name = "brg14"; interrupts = <41>; interrupt-parent = <&qeic>; };
Quoted 2 lines
You need to have separate BRGs for TX and RX when using soft-uart mode, and you MUST use soft-uart mode on the 8360.
Yup, I know. In the original email I've explained that I deliberately configured two uarts differently for the testing purposes.
Thanks!
Signature · 4 lines
Anton Vorontsov email: [email protected] backup email: [email protected] irc://irc.freenode.net/bd2
arch/powerpc/boot/dts/mpc836x_rdk.dts line 143
Quoted 8 lines · Anton Vorontsov
arch/powerpc/boot/dts/mpc836x_rdk.dts new file +8
-0+ qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe"; + ranges = <0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + /* filled by u-boot */ + brg-frequency = <0>;
You need "bus-frequency" here too
Quoted 12 lines · Timur Tabi
arch/powerpc/boot/dts/mpc836x_rdk.dts line 143
Quoted 8 lines · Anton Vorontsov
arch/powerpc/boot/dts/mpc836x_rdk.dts new file +8
-0+ qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe"; + ranges = <0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + /* filled by u-boot */ + brg-frequency = <0>;You need "bus-frequency" here too
Hm..
http://ozlabs.org/pipermail/linuxppc-dev/2007-December/048388.html
^^ David Gibson suggested to get rid of it.
Signature · 4 lines
Anton Vorontsov email: [email protected] backup email: [email protected] irc://irc.freenode.net/bd2
Quoted 7 lines · Anton Vorontsov
Quoted 1 line
You need "bus-frequency" here too
Hm..
http://ozlabs.org/pipermail/linuxppc-dev/2007-December/048388.html
^^ David Gibson suggested to get rid of it.
It looks to me like he's just suggesting that we rename it to clock-frequency. That may be a better name, but for now changing it will only confuse U-Boot and any other code that's looking for bus-frequency. If we want to rename it, I suggest we do that in a different patch. Having some DTS files with "bus-frequency" and others with "clock-frequency" is bad.