64 bit i/o
RFC 1/1 64 bit i/o
Sparc32 has a 64 bit counter that should be read and written as 64 bits but that isn't supported in QEMU. I did a quick hack to add 64 bit i/o and converted sparc32 to use it and it seems to work. I'm suppling the sparc changes to get comments on if this is worth pursuing. This has only received enough testing to verify that the 64 bit counter was being read and written as 64 bits. I was able to run the linux kernel in sparc-test. QEMU will crash on accessing an unsupported size because the latest io changes are partially disabled until I figure out a clean way to call do_unassigned_access. A lot of the embedded processors use the same function for accessing all sizes so converting them will be painful.
Index: cpu-all.h
===================================================================
RCS file: /sources/qemu/qemu/cpu-all.h,v
retrieving revision 1.81
cpu-all.h +29 -6
@@ -823,8 +823,31 @@ extern uint8_t *phys_ram_dirty;#define IO_MEM_SUBPAGE (2)#define IO_MEM_SUBWIDTH (4) -typedef void CPUWriteMemoryFunc (void *opaque,target_phys_addr_t addr,uint32_t value); -typedef uint32_t CPUReadMemoryFunc (void *opaque,target_phys_addr_t addr); +typedef void CPUWriteMemoryFunc8 (void *opaque,target_phys_addr_t addr,uint8_t value); +typedef uint8_t CPUReadMemoryFunc8 (void *opaque,target_phys_addr_t addr); + +typedef void CPUWriteMemoryFunc16 (void *opaque,target_phys_addr_t addr,uint16_t value); +typedef uint16_t CPUReadMemoryFunc16 (void *opaque,target_phys_addr_t addr); + +typedef void CPUWriteMemoryFunc32 (void *opaque,target_phys_addr_t addr,uint32_t value); +typedef uint32_t CPUReadMemoryFunc32 (void *opaque,target_phys_addr_t addr); + +typedef void CPUWriteMemoryFunc64 (void *opaque,target_phys_addr_t addr,uint64_t value); +typedef uint64_t CPUReadMemoryFunc64 (void *opaque,target_phys_addr_t addr); + +typedef struct CPUWriteMemoryFuncs { +CPUWriteMemoryFunc8 *b; +CPUWriteMemoryFunc16 *w; +CPUWriteMemoryFunc32 *l; +CPUWriteMemoryFunc64 *q; +}CPUWriteMemoryFuncs ; + +typedef struct CPUReadMemoryFuncs { +CPUReadMemoryFunc8 *b; +CPUReadMemoryFunc16 *w; +CPUReadMemoryFunc32 *l; +CPUReadMemoryFunc64 *q; +}CPUReadMemoryFuncs ; void cpu_register_physical_memory(target_phys_addr_t start_addr, unsigned long size,
@@ -833,11 +856,11 @@ uint32_t cpu_get_physical_page_desc(targram_addr_t qemu_ram_alloc (unsigned int size);void qemu_ram_free (ram_addr_t addr);int cpu_register_io_memory (int io_index, -CPUReadMemoryFunc **mem_read, -CPUWriteMemoryFunc **mem_write, +CPUReadMemoryFuncs *mem_read, +CPUWriteMemoryFuncs *mem_write,void *opaque); -CPUWriteMemoryFunc **cpu_get_io_memory_write (int io_index); -CPUReadMemoryFunc **cpu_get_io_memory_read (int io_index); +CPUWriteMemoryFuncs *cpu_get_io_memory_write (int io_index); +CPUReadMemoryFuncs *cpu_get_io_memory_read (int io_index);void cpu_physical_memory_rw (target_phys_addr_t addr,uint8_t *buf,int len,int is_write);
Index: exec-all.h
===================================================================
RCS file: /sources/qemu/qemu/exec-all.h,v
retrieving revision 1.73
exec-all.h +2 -2
@@ -336,8 +336,8 @@ dummy_label ## n: ;\#endif -extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES ][4 ]; -extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES ][4 ]; +extern CPUWriteMemoryFuncs io_mem_write[IO_MEM_NB_ENTRIES ]; +extern CPUReadMemoryFuncs io_mem_read[IO_MEM_NB_ENTRIES ];extern void *io_mem_opaque[IO_MEM_NB_ENTRIES ];#if defined(__powerpc__)
Index: exec.c
===================================================================
RCS file: /sources/qemu/qemu/exec.c,v
retrieving revision 1.121
exec.c +256 -103
646 lines not on this page · raw message
Index: softmmu_template.h
===================================================================
RCS file: /sources/qemu/qemu/softmmu_template.h,v
retrieving revision 1.21
softmmu_template.h +32 -16
66 lines not on this page · raw message
Index: hw/cs4231.c
===================================================================
RCS file: /sources/qemu/qemu/hw/cs4231.c,v
retrieving revision 1.5
cs4231.c +5 -3
@@ -127,16 +127,18 @@ static void cs_mem_writel(void *opaque, } } -static CPUReadMemoryFunc *cs_mem_read[3 ] = { +static CPUReadMemoryFuncs cs_mem_read = { cs_mem_readl, cs_mem_readl, cs_mem_readl, +NULL , }; -static CPUWriteMemoryFunc *cs_mem_write[3 ] = { +static CPUWriteMemoryFuncs cs_mem_write = { cs_mem_writel, cs_mem_writel, cs_mem_writel, +NULL , };static void cs_save (QEMUFile *f,void *opaque)
@@ -174,7 +176,7 @@ void cs_init(target_phys_addr_t base, inif (!s)return ; - cs_io_memory =cpu_register_io_memory (0 , cs_mem_read, cs_mem_write, s); + cs_io_memory =cpu_register_io_memory (0 , &cs_mem_read, &cs_mem_write, s);cpu_register_physical_memory (base,CS_SIZE , cs_io_memory);register_savevm ("cs4231" , base,1 , cs_save, cs_load, s);qemu_register_reset (cs_reset, s);
Index: hw/eccmemctl.c
===================================================================
RCS file: /sources/qemu/qemu/hw/eccmemctl.c,v
retrieving revision 1.2
eccmemctl.c +5 -3
@@ -176,16 +176,18 @@ static uint32_t ecc_mem_readl(void *opaqreturn ret; } -static CPUReadMemoryFunc *ecc_mem_read[3 ] = { +static CPUReadMemoryFuncs ecc_mem_read = {NULL ,NULL , ecc_mem_readl, +NULL , }; -static CPUWriteMemoryFunc *ecc_mem_write[3 ] = { +static CPUWriteMemoryFuncs ecc_mem_write = {NULL ,NULL , ecc_mem_writel, +NULL , };static int ecc_load (QEMUFile *f,void *opaque,int version_id)
@@ -233,7 +235,7 @@ void * ecc_init(target_phys_addr_t base, s->regs[0 ] = version; - ecc_io_memory =cpu_register_io_memory (0 , ecc_mem_read, ecc_mem_write, s); + ecc_io_memory =cpu_register_io_memory (0 , &ecc_mem_read, &ecc_mem_write, s);cpu_register_physical_memory (base,ECC_SIZE , ecc_io_memory);register_savevm ("ECC" , base,1 , ecc_save, ecc_load, s);qemu_register_reset (ecc_reset, s);
Index: hw/esp.c
===================================================================
RCS file: /sources/qemu/qemu/hw/esp.c,v
retrieving revision 1.33
esp.c +7 -5
@@ -397,7 +397,7 @@ static void parent_esp_reset(void *opaquesp_reset (opaque); } -static uint32_t esp_mem_readb (void *opaque,target_phys_addr_t addr) +static uint8_t esp_mem_readb (void *opaque,target_phys_addr_t addr) {ESPState *s = opaque;uint32_t saddr;
@@ -433,7 +433,7 @@ static uint32_t esp_mem_readb(void *opaqreturn s->rregs[saddr]; } -static void esp_mem_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) +static void esp_mem_writeb (void *opaque,target_phys_addr_t addr,uint8_t val) {ESPState *s = opaque;uint32_t saddr;
@@ -541,16 +541,18 @@ static void esp_mem_writeb(void *opaque, s->wregs[saddr] = val; } -static CPUReadMemoryFunc *esp_mem_read[3 ] = { +static CPUReadMemoryFuncs esp_mem_read = { esp_mem_readb,NULL ,NULL , +NULL , }; -static CPUWriteMemoryFunc *esp_mem_write[3 ] = { +static CPUWriteMemoryFuncs esp_mem_write = { esp_mem_writeb,NULL ,NULL , +NULL , };static void esp_save (QEMUFile *f,void *opaque)
@@ -633,7 +635,7 @@ void *esp_init(target_phys_addr_t espadd s->irq = irq; s->dma_opaque = dma_opaque; - esp_io_memory =cpu_register_io_memory (0 , esp_mem_read, esp_mem_write, s); + esp_io_memory =cpu_register_io_memory (0 , &esp_mem_read, &esp_mem_write, s);cpu_register_physical_memory (espaddr,ESP_SIZE , esp_io_memory);esp_reset (s);
Index: hw/fdc.c
===================================================================
RCS file: /sources/qemu/qemu/hw/fdc.c,v
retrieving revision 1.37
fdc.c +11 -7
@@ -481,28 +481,32 @@ static void fdctrl_write_mem (void *opaqfdctrl_write (opaque, (uint32_t )reg, value); } -static CPUReadMemoryFunc *fdctrl_mem_read[3 ] = { +static CPUReadMemoryFuncs fdctrl_mem_read = { fdctrl_read_mem, fdctrl_read_mem, fdctrl_read_mem, +NULL }; -static CPUWriteMemoryFunc *fdctrl_mem_write[3 ] = { +static CPUWriteMemoryFuncs fdctrl_mem_write = { fdctrl_write_mem, fdctrl_write_mem, fdctrl_write_mem, +NULL }; -static CPUReadMemoryFunc *fdctrl_mem_read_strict[3 ] = { +static CPUReadMemoryFuncs fdctrl_mem_read_strict = { fdctrl_read_mem,NULL ,NULL , +NULL , }; -static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3 ] = { +static CPUWriteMemoryFuncs fdctrl_mem_write_strict = { fdctrl_write_mem,NULL ,NULL , +NULL , };static void fd_save (QEMUFile *f,fdrive_t *fd)
@@ -653,7 +657,7 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int fdctrl->sun4m =0 ;if (mem_mapped) { - io_mem =cpu_register_io_memory (0 , fdctrl_mem_read, fdctrl_mem_write, + io_mem =cpu_register_io_memory (0 , &fdctrl_mem_read, &fdctrl_mem_write, fdctrl);cpu_register_physical_memory (io_base,0x08 , io_mem); }else {
@@ -678,8 +682,8 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq ir fdctrl =fdctrl_init_common (irq,0 , io_base, fds); fdctrl->sun4m =1 ; - io_mem =cpu_register_io_memory (0 , fdctrl_mem_read_strict, - fdctrl_mem_write_strict, + io_mem =cpu_register_io_memory (0 , &fdctrl_mem_read_strict, + &fdctrl_mem_write_strict, fdctrl);cpu_register_physical_memory (io_base,0x08 , io_mem);
Index: hw/iommu.c
===================================================================
RCS file: /sources/qemu/qemu/hw/iommu.c,v
retrieving revision 1.25
iommu.c +6 -4
@@ -212,16 +212,18 @@ static void iommu_mem_writel(void *opaqu } } -static CPUReadMemoryFunc *iommu_mem_read[3 ] = { +static CPUReadMemoryFuncs iommu_mem_read = {NULL ,NULL , iommu_mem_readl, +NULL , }; -static CPUWriteMemoryFunc *iommu_mem_write[3 ] = { +static CPUWriteMemoryFuncs iommu_mem_write = {NULL ,NULL , iommu_mem_writel, +NULL , };static uint32_t iommu_page_get_flags (IOMMUState *s,target_phys_addr_t addr)
@@ -353,8 +355,8 @@ void *iommu_init(target_phys_addr_t addr s->version = version; s->irq = irq; - iommu_io_memory =cpu_register_io_memory (0 , iommu_mem_read, - iommu_mem_write, s); + iommu_io_memory =cpu_register_io_memory (0 , &iommu_mem_read, + &iommu_mem_write, s);cpu_register_physical_memory (addr,IOMMU_NREGS *4 , iommu_io_memory);register_savevm ("iommu" , addr,2 , iommu_save, iommu_load, s);
Index: hw/m48t59.c
===================================================================
RCS file: /sources/qemu/qemu/hw/m48t59.c,v
retrieving revision 1.19
m48t59.c +48 -14
102 lines not on this page · raw message
Index: hw/pcnet.c
===================================================================
RCS file: /sources/qemu/qemu/hw/pcnet.c,v
retrieving revision 1.23
pcnet.c +47 -20
140 lines not on this page · raw message
Index: hw/sbi.c
===================================================================
RCS file: /sources/qemu/qemu/hw/sbi.c,v
retrieving revision 1.2
sbi.c +5 -3
@@ -90,16 +90,18 @@ static void sbi_mem_writel(void *opaque, } } -static CPUReadMemoryFunc *sbi_mem_read[3 ] = { +static CPUReadMemoryFuncs sbi_mem_read = {NULL ,NULL , sbi_mem_readl, +NULL , }; -static CPUWriteMemoryFunc *sbi_mem_write[3 ] = { +static CPUWriteMemoryFuncs sbi_mem_write = {NULL ,NULL , sbi_mem_writel, +NULL , };static void sbi_save (QEMUFile *f,void *opaque)
@@ -154,7 +156,7 @@ void *sbi_init(target_phys_addr_t addr, s->cpu_irqs[i] = parent_irq[i]; } - sbi_io_memory =cpu_register_io_memory (0 , sbi_mem_read, sbi_mem_write, s); + sbi_io_memory =cpu_register_io_memory (0 , &sbi_mem_read, &sbi_mem_write, s);cpu_register_physical_memory (addr,SBI_SIZE , sbi_io_memory);register_savevm ("sbi" , addr,1 , sbi_save, sbi_load, s);
Index: hw/slavio_intctl.c
===================================================================
RCS file: /sources/qemu/qemu/hw/slavio_intctl.c,v
retrieving revision 1.29
slavio_intctl.c +10 -6
@@ -128,16 +128,18 @@ static void slavio_intctl_mem_writel(voi } } -static CPUReadMemoryFunc *slavio_intctl_mem_read[3 ] = { +static CPUReadMemoryFuncs slavio_intctl_mem_read = {NULL ,NULL , slavio_intctl_mem_readl, +NULL , }; -static CPUWriteMemoryFunc *slavio_intctl_mem_write[3 ] = { +static CPUWriteMemoryFuncs slavio_intctl_mem_write = {NULL ,NULL , slavio_intctl_mem_writel, +NULL , };// master system interrupt controller
@@ -199,16 +201,18 @@ static void slavio_intctlm_mem_writel(vo } } -static CPUReadMemoryFunc *slavio_intctlm_mem_read[3 ] = { +static CPUReadMemoryFuncs slavio_intctlm_mem_read = {NULL ,NULL , slavio_intctlm_mem_readl, +NULL , }; -static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3 ] = { +static CPUWriteMemoryFuncs slavio_intctlm_mem_write = {NULL ,NULL , slavio_intctlm_mem_writel, +NULL , };void slavio_pic_info (void *opaque)
@@ -376,13 +380,13 @@ void *slavio_intctl_init(target_phys_add s->intbit_to_level = intbit_to_level;for (i =0 ; i <MAX_CPUS ; i++) { - slavio_intctl_io_memory =cpu_register_io_memory (0 , slavio_intctl_mem_read, slavio_intctl_mem_write, s); + slavio_intctl_io_memory =cpu_register_io_memory (0 , &slavio_intctl_mem_read, &slavio_intctl_mem_write, s);cpu_register_physical_memory (addr + i *TARGET_PAGE_SIZE ,INTCTL_SIZE , slavio_intctl_io_memory); s->cpu_irqs[i] = parent_irq[i]; } - slavio_intctlm_io_memory =cpu_register_io_memory (0 , slavio_intctlm_mem_read, slavio_intctlm_mem_write, s); + slavio_intctlm_io_memory =cpu_register_io_memory (0 , &slavio_intctlm_mem_read, &slavio_intctlm_mem_write, s);cpu_register_physical_memory (addrg,INTCTLM_SIZE , slavio_intctlm_io_memory);register_savevm ("slavio_intctl" , addr,1 , slavio_intctl_save, slavio_intctl_load, s);
Index: hw/slavio_misc.c
===================================================================
RCS file: /sources/qemu/qemu/hw/slavio_misc.c,v
retrieving revision 1.17
slavio_misc.c +25 -18
126 lines not on this page · raw message
Index: hw/slavio_serial.c
===================================================================
RCS file: /sources/qemu/qemu/hw/slavio_serial.c,v
retrieving revision 1.32
slavio_serial.c +10 -8
@@ -470,7 +470,7 @@ static void slavio_serial_update_paramet }static void slavio_serial_mem_writeb (void *opaque,target_phys_addr_t addr, -uint32_t val) +uint8_t val) {SerialState *serial = opaque;ChannelState *s;
@@ -563,7 +563,7 @@ static void slavio_serial_mem_writeb(voi } } -static uint32_t slavio_serial_mem_readb (void *opaque,target_phys_addr_t addr) +static uint8_t slavio_serial_mem_readb (void *opaque,target_phys_addr_t addr) {SerialState *serial = opaque;ChannelState *s;
@@ -639,16 +639,18 @@ static void serial_event(void *opaque, iserial_receive_break (s); } -static CPUReadMemoryFunc *slavio_serial_mem_read[3 ] = { +static CPUReadMemoryFuncs slavio_serial_mem_read = { slavio_serial_mem_readb,NULL ,NULL , +NULL , }; -static CPUWriteMemoryFunc *slavio_serial_mem_write[3 ] = { +static CPUWriteMemoryFuncs slavio_serial_mem_write = { slavio_serial_mem_writeb,NULL ,NULL , +NULL , };static void slavio_serial_save_chn (QEMUFile *f,ChannelState *s)
@@ -720,8 +722,8 @@ SerialState *slavio_serial_init(target_pif (!s)return NULL ; - slavio_serial_io_memory =cpu_register_io_memory (0 , slavio_serial_mem_read, - slavio_serial_mem_write, + slavio_serial_io_memory =cpu_register_io_memory (0 , &slavio_serial_mem_read, + &slavio_serial_mem_write, s);cpu_register_physical_memory (base,SERIAL_SIZE , slavio_serial_io_memory);
@@ -906,8 +908,8 @@ void slavio_serial_ms_kbd_init(target_ph s->chn[0 ].disabled = disabled; s->chn[1 ].disabled = disabled; - slavio_serial_io_memory =cpu_register_io_memory (0 , slavio_serial_mem_read, - slavio_serial_mem_write, + slavio_serial_io_memory =cpu_register_io_memory (0 , &slavio_serial_mem_read, + &slavio_serial_mem_write, s);cpu_register_physical_memory (base,SERIAL_SIZE , slavio_serial_io_memory);
Index: hw/slavio_timer.c
===================================================================
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.28
slavio_timer.c +60 -6
98 lines not on this page · raw message
Index: hw/sparc32_dma.c
===================================================================
RCS file: /sources/qemu/qemu/hw/sparc32_dma.c,v
retrieving revision 1.11
sparc32_dma.c +5 -3
@@ -197,16 +197,18 @@ static void dma_mem_writel(void *opaque, s->dmaregs[saddr] = val; } -static CPUReadMemoryFunc *dma_mem_read[3 ] = { +static CPUReadMemoryFuncs dma_mem_read = {NULL ,NULL , dma_mem_readl, +NULL , }; -static CPUWriteMemoryFunc *dma_mem_write[3 ] = { +static CPUWriteMemoryFuncs dma_mem_write = {NULL ,NULL , dma_mem_writel, +NULL , };static void dma_reset (void *opaque)
@@ -252,7 +254,7 @@ void *sparc32_dma_init(target_phys_addr_ s->irq = parent_irq; s->iommu = iommu; - dma_io_memory =cpu_register_io_memory (0 , dma_mem_read, dma_mem_write, s); + dma_io_memory =cpu_register_io_memory (0 , &dma_mem_read, &dma_mem_write, s);cpu_register_physical_memory (daddr,DMA_SIZE , dma_io_memory);register_savevm ("sparc32_dma" , daddr,2 , dma_save, dma_load, s);
Index: hw/sun4c_intctl.c
===================================================================
RCS file: /sources/qemu/qemu/hw/sun4c_intctl.c,v
retrieving revision 1.2
sun4c_intctl.c +8 -6
@@ -57,7 +57,7 @@ typedef struct Sun4c_INTCTLState {static void sun4c_check_interrupts (void *opaque); -static uint32_t sun4c_intctl_mem_readb (void *opaque,target_phys_addr_t addr) +static uint8_t sun4c_intctl_mem_readb (void *opaque,target_phys_addr_t addr) {Sun4c_INTCTLState *s = opaque;uint32_t ret;
@@ -68,7 +68,7 @@ static uint32_t sun4c_intctl_mem_readb(vreturn ret; } -static void sun4c_intctl_mem_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) +static void sun4c_intctl_mem_writeb (void *opaque,target_phys_addr_t addr,uint8_t val) {Sun4c_INTCTLState *s = opaque;
@@ -78,16 +78,18 @@ static void sun4c_intctl_mem_writeb(voidsun4c_check_interrupts (s); } -static CPUReadMemoryFunc *sun4c_intctl_mem_read[3 ] = { +static CPUReadMemoryFuncs sun4c_intctl_mem_read = { sun4c_intctl_mem_readb,NULL ,NULL , +NULL , }; -static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3 ] = { +static CPUWriteMemoryFuncs sun4c_intctl_mem_write = { sun4c_intctl_mem_writeb,NULL ,NULL , +NULL , };void sun4c_pic_info (void *opaque)
@@ -206,8 +208,8 @@ void *sun4c_intctl_init(target_phys_addrif (!s)return NULL ; - sun4c_intctl_io_memory =cpu_register_io_memory (0 , sun4c_intctl_mem_read, - sun4c_intctl_mem_write, s); + sun4c_intctl_io_memory =cpu_register_io_memory (0 , &sun4c_intctl_mem_read, + &sun4c_intctl_mem_write, s);cpu_register_physical_memory (addr,INTCTL_SIZE , sun4c_intctl_io_memory); s->cpu_irqs = parent_irq;
Index: hw/tcx.c
===================================================================
RCS file: /sources/qemu/qemu/hw/tcx.c,v
retrieving revision 1.26
tcx.c +10 -6
@@ -456,16 +456,18 @@ static void tcx_dac_writel(void *opaque,return ; } -static CPUReadMemoryFunc *tcx_dac_read[3 ] = { +static CPUReadMemoryFuncs tcx_dac_read = {NULL ,NULL , tcx_dac_readl, +NULL , }; -static CPUWriteMemoryFunc *tcx_dac_write[3 ] = { +static CPUWriteMemoryFuncs tcx_dac_write = {NULL ,NULL , tcx_dac_writel, +NULL , };static uint32_t tcx_dummy_readl (void *opaque,target_phys_addr_t addr)
@@ -478,16 +480,18 @@ static void tcx_dummy_writel(void *opaqu { } -static CPUReadMemoryFunc *tcx_dummy_read[3 ] = { +static CPUReadMemoryFuncs tcx_dummy_read = {NULL ,NULL , tcx_dummy_readl, +NULL , }; -static CPUWriteMemoryFunc *tcx_dummy_write[3 ] = { +static CPUWriteMemoryFuncs tcx_dummy_write = {NULL ,NULL , tcx_dummy_writel, +NULL , }; void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
@@ -515,10 +519,10 @@ void tcx_init(DisplayState *ds, target_p vram_offset += size; vram_base += size; - io_memory =cpu_register_io_memory (0 , tcx_dac_read, tcx_dac_write, s); + io_memory =cpu_register_io_memory (0 , &tcx_dac_read, &tcx_dac_write, s);cpu_register_physical_memory (addr +0x00200000ULL ,TCX_DAC_NREGS , io_memory); - dummy_memory =cpu_register_io_memory (0 , tcx_dummy_read, tcx_dummy_write, + dummy_memory =cpu_register_io_memory (0 , &tcx_dummy_read, &tcx_dummy_write, s);cpu_register_physical_memory (addr +0x00700000ULL ,TCX_TEC_NREGS , dummy_memory);
Quoted 5 lines · Robert Reif
Sparc32 has a 64 bit counter that should be read and written as 64 bits but that isn't supported in QEMU. I did a quick hack to add 64 bit i/o and converted sparc32 to use it and it seems to work. I'm suppling the sparc changes to get comments on if this is worth pursuing.
Couldn't you just latch the value when one half is accessed?
Paul
Quoted 11 lines · Paul Brook
Quoted 7 lines · Robert Reif
Sparc32 has a 64 bit counter that should be read and written as 64 bits but that isn't supported in QEMU. I did a quick hack to add 64 bit i/o and converted sparc32 to use it and it seems to work. I'm suppling the sparc changes to get comments on if this is worth pursuing.
Quoted 8 lines
Couldn't you just latch the value when one half is accessed?
Paul
In this one specific case you could do that but this is not the only case in sparc32 (TOD, MXCC, ...) and other architectures with 64 bit hardware have similar requirements.
This is a generic solution that fills a hole in the qemu implementation.
Quoted 10 lines · Robert Reif
Quoted 3 lines · Paul Brook
Couldn't you just latch the value when one half is accessed?
In this one specific case you could do that but this is not the only case in sparc32 (TOD, MXCC, ...) and other architectures with 64 bit hardware have similar requirements.
This is a generic solution that fills a hole in the qemu implementation.
Agreed. Some non-PC hardware has 64-bit registers which need to be accessed as 64-bit quantities, in order to read or write all fields at once. Qemu should support 64-bit I/O.
Brian
Quoted 9 lines · Brian Johnson
Quoted 8 lines · Robert Reif
Quoted 3 lines · Paul Brook
Couldn't you just latch the value when one half is accessed?
In this one specific case you could do that but this is not the only case in sparc32 (TOD, MXCC, ...) and other architectures with 64 bit hardware have similar requirements.
Quoted 6 lines
Quoted 2 lines
This is a generic solution that fills a hole in the qemu implementation.
Agreed. Some non-PC hardware has 64-bit registers which need to be accessed as 64-bit quantities, in order to read or write all fields at once. Qemu should support 64-bit I/O.
On Sparc64 many registers can only be handled using 64 bit accesses, other methods should raise an exception.