QE UEC: Add MII Commands

diff -purN a/drivers/qe/uec.c b/drivers/qe/uec.c
@@ -29,6 +29,7 @@
 #include "uccf.h"
 #include "uec.h"
 #include "uec_phy.h"
+#include "miiphy.h"
 
 #if defined(CONFIG_QE)
 

@@ -88,6 +89,17 @@ static uec_info_t eth3_uec_info = {
 };
 #endif
 
+#define MAXCONTROLLERS	(4)
+
+static struct eth_device *devlist[MAXCONTROLLERS];
+
+static int uec_miiphy_read(char *devname, unsigned char addr,
+			    unsigned char reg, unsigned short *value);
+static int uec_miiphy_write(char *devname, unsigned char addr,
+			     unsigned char reg, unsigned short value);
+u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
+void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
+
 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
 {
 	uec_t		*uec_regs;

@@ -1267,6 +1279,8 @@ int uec_initialize(int index)
 		return -EINVAL;
 	}
 
+	devlist[index] = dev;
+	
 	uec->uec_info = uec_info;
 
 	sprintf(dev->name, "FSL UEC%d", index);

@@ -1297,6 +1311,45 @@ int uec_initialize(int index)
 
 	phy_change(dev);
 
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+	&& !defined(BITBANGMII)
+	miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
+#endif
+
 	return 1;
 }
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+	&& !defined(BITBANGMII)
+
+/*
+ * Read a MII PHY register.
+ *
+ * Returns:
+ *  0 on success
+ */
+static int uec_miiphy_read(char *devname, unsigned char addr,
+			    unsigned char reg, unsigned short *value)
+{
+	*value = uec_read_phy_reg(devlist[0], addr, reg);
+
+	return 0;
+}
+
+/*
+ * Write a MII PHY register.
+ *
+ * Returns:
+ *  0 on success
+ */
+static int uec_miiphy_write(char *devname, unsigned char addr,
+			     unsigned char reg, unsigned short value)
+{
+	uec_write_phy_reg(devlist[0], addr, reg, value);
+
+	return 0;
+}
+
+#endif
+
 #endif /* CONFIG_QE */

index 281f0b2..3750bb6 100644
@@ -48,10 +48,11 @@
 
 struct mii_dev {
 	struct list_head link;
+	struct eth_device *edev;
 	char *name;
-	int (*read) (char *devname, unsigned char addr,
+	int (*read) (struct eth_device *edev, unsigned char addr,
 		     unsigned char reg, unsigned short *value);
-	int (*write) (char *devname, unsigned char addr,
+	int (*write) (struct eth_device *edev, unsigned char addr,
 		      unsigned char reg, unsigned short value);
 };
 

@@ -72,12 +73,13 @@ void miiphy_init ()
  *
  * Register read and write MII access routines for the device <name>.
  */
-void miiphy_register (char *name,
-		      int (*read) (char *devname, unsigned char addr,
+void miiphy_register (struct eth_device *edev,
+		      int (*read) (struct eth_device *edev, unsigned char addr,
 				   unsigned char reg, unsigned short *value),
-		      int (*write) (char *devname, unsigned char addr,
+		      int (*write) (struct eth_device *edev, unsigned char addr,
 				    unsigned char reg, unsigned short value))
 {
+	char *name = edev->name;
 	struct list_head *entry;
 	struct mii_dev *new_dev;
 	struct mii_dev *miidev;

@@ -109,6 +111,7 @@ void miiphy_register (char *name,
 	INIT_LIST_HEAD (&new_dev->link);
 	new_dev->read = read;
 	new_dev->write = write;
+	new_dev->edev = edev;
 	new_dev->name = (char *)(new_dev + 1);
 	strncpy (new_dev->name, name, name_len);
 	new_dev->name[name_len] = '\0';

@@ -175,7 +178,7 @@ int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
 
 		if (strcmp (devname, dev->name) == 0) {
 			found_dev = 1;
-			read_ret = dev->read (devname, addr, reg, value);
+			read_ret = dev->read (dev->edev, addr, reg, value);
 			break;
 		}
 	}

@@ -212,7 +215,7 @@ int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
 
 		if (strcmp (devname, dev->name) == 0) {
 			found_dev = 1;
-			write_ret = dev->write (devname, addr, reg, value);
+			write_ret = dev->write (dev->edev, addr, reg, value);
 			break;
 		}
 	}

index a27c12a..2d29403 100644
@@ -1296,6 +1296,9 @@ int uec_initialize(int index)
 
 	phy_change(dev);
 
+	if (index == 1)
+		uec_mmiphy_register(dev);
+
 	return 1;
 }
 #endif /* CONFIG_QE */

index 6882d03..ccd6645 100644
@@ -681,4 +681,28 @@ void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
 	marvell_phy_interface_mode (dev, mode);
 #endif
 }
+
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+	&& !defined(BITBANGMII)
+static int uec_miiphy_read(struct eth_device *dev, unsigned char addr,
+			    unsigned char reg, unsigned short *value)
+{
+	*value = uec_read_phy_reg(dev, addr, reg);
+	return 0;
+}
+
+static int uec_miiphy_write(struct eth_device *dev, unsigned char addr,
+			     unsigned char reg, unsigned short value)
+{
+	uec_write_phy_reg(dev, addr, reg, value);
+	return 0;
+}
+
+void uec_mmiphy_register(struct eth_device *dev)
+{
+	miiphy_register(dev, uec_miiphy_read, uec_miiphy_write);
+}
+#endif
+
 #endif /* CONFIG_QE */

index 6f769fb..ef62f0b 100644
@@ -261,4 +261,5 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
 				  u32 interrupts);
+void uec_mmiphy_register(struct eth_device *dev);
 #endif /* __UEC_PHY_H__ */

index 5518a0a..0ff4ae6 100644
@@ -48,10 +48,10 @@ int miiphy_link (char *devname, unsigned char addr);
 
 void miiphy_init (void);
 
-void miiphy_register (char *devname,
-		      int (*read) (char *devname, unsigned char addr,
+void miiphy_register (struct eth_device *edev,
+		      int (*read) (struct eth_device *edev, unsigned char addr,
 				   unsigned char reg, unsigned short *value),
-		      int (*write) (char *devname, unsigned char addr,
+		      int (*write) (struct eth_device *edev, unsigned char addr,
 				    unsigned char reg, unsigned short value));
 
 int miiphy_set_current_dev (char *devname);