Various new ibm405 DCRN #defines
PATCH 1/1 Various new ibm405 DCRN #defines
Various new ibm405 DCRN #defines.
--- arch/ppc/platforms/4xx/ibm405ep.h | 3 +++ arch/ppc/platforms/4xx/ibm405gp.h | 9 +++++++++ arch/ppc/platforms/4xx/ibm405gpr.h | 9 +++++++++ include/asm-ppc/ibm405.h | 27 +++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 0 deletions(-)
arch/ppc/platforms/4xx/ibm405ep.h +3 -0
@@ -139,6 +139,9 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_STATUS 0x24/* SDRAM Controller Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405EP_H__ */
arch/ppc/platforms/4xx/ibm405gp.h +9 -0
@@ -142,6 +142,15 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_BESR0 0x00/* Bus Error Syndrome Reg 0 */ +#define DCRN_SDRAM0_BESR1 0x08/* Bus Error Syndrome Reg 1 */ +#define DCRN_SDRAM0_BEAR 0x10/* Bus Error Address Reg */ +#define DCRN_SDRAM0_B2CR 0x48/* Memory Bank 2 Configuration Reg */ +#define DCRN_SDRAM0_B3CR 0x4c/* Memory Bank 3 Configuration Reg */ +#define DCRN_SDRAM0_ECCCFG 0x94/* ECC Configuration */ +#define DCRN_SDRAM0_ECCESR 0x98/* ECC Error Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405GP_H__ */
arch/ppc/platforms/4xx/ibm405gpr.h +9 -0
@@ -142,6 +142,15 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_BESR0 0x00/* Bus Error Syndrome Reg 0 */ +#define DCRN_SDRAM0_BESR1 0x08/* Bus Error Syndrome Reg 1 */ +#define DCRN_SDRAM0_BEAR 0x10/* Bus Error Address Reg */ +#define DCRN_SDRAM0_B2CR 0x48/* Memory Bank 2 Configuration Reg */ +#define DCRN_SDRAM0_B3CR 0x4c/* Memory Bank 3 Configuration Reg */ +#define DCRN_SDRAM0_ECCCFG 0x94/* ECC Configuration */ +#define DCRN_SDRAM0_ECCESR 0x98/* ECC Error Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405GPR_H__ */
include/asm-ppc/ibm405.h +0 -0
@@ -135,6 +135,26 @@#ifdef DCRN_EBC_BASE #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0)/* Peripheral Controller
Address */
#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller
Data */
+#define DCRN_EBC_PB0CR 0x00 /* Peripheral Bank 0 Config Reg */
+#define DCRN_EBC_PB1CR 0x01 /* Peripheral Bank 1 Config Reg */
+#define DCRN_EBC_PB2CR 0x02 /* Peripheral Bank 2 Config Reg */
+#define DCRN_EBC_PB3CR 0x03 /* Peripheral Bank 3 Config Reg */
+#define DCRN_EBC_PB4CR 0x04 /* Peripheral Bank 4 Config Reg */
+#define DCRN_EBC_PB5CR 0x05 /* Peripheral Bank 5 Config Reg */
+#define DCRN_EBC_PB6CR 0x06 /* Peripheral Bank 6 Config Reg */
+#define DCRN_EBC_PB7CR 0x07 /* Peripheral Bank 7 Config Reg */
+#define DCRN_EBC_PB0AP 0x10 /* Peripheral Bank 0 Access Parameters */
+#define DCRN_EBC_PB1AP 0x11 /* Peripheral Bank 1 Access parameters */
+#define DCRN_EBC_PB2AP 0x12 /* Peripheral Bank 2 Access Parameters */
+#define DCRN_EBC_PB3AP 0x13 /* Peripheral Bank 3 Access Parameters */
+#define DCRN_EBC_PB4AP 0x14 /* Peripheral Bank 4 Access Parameters */
+#define DCRN_EBC_PB5AP 0x15 /* Peripheral Bank 5 Access Parameters */
+#define DCRN_EBC_PB6AP 0x16 /* Peripheral Bank 6 Access Parameters */
+#define DCRN_EBC_PB7AP 0x17 /* Peripheral Bank 7 Access Parameters */
+#define DCRN_EBC_PBEAR 0x20 /* Peripheral Bus Error Address Reg */
+#define DCRN_EBC_PBESR0 0x21 /* Peripheral Bus Error Status Reg 0 */
+#define DCRN_EBC_PBESR1 0x22 /* Peripheral Bus Error Status Reg 1 */
+#define DCRN_EBC_EPCR 0x23 /* External Peripheral Control Reg */
#endif
#ifdef DCRN_EXIER_BASE
@@ -286,6 +306,13 @@
#ifdef DCRN_SDRAM0_BASE
#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory
Controller Address */
#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory
Controller Data */
+#define DCRN_SDRAM0_CFG 0x20 /* SDRAM Configuration */
+#define DCRN_SDRAM0_STATUS 0x24 /* SDRAM Controller Status */
+#define DCRN_SDRAM0_RTR 0x30 /* Refresh Timer Reg */
+#define DCRN_SDRAM0_PMIT 0x34 /* Power Management Idle Timer */
+#define DCRN_SDRAM0_B0CR 0x40 /* Memory Bank 0 Configuration Reg */
+#define DCRN_SDRAM0_B1CR 0x44 /* Memory Bank 1 Configuration Reg */
+#define DCRN_SDRAM0_TR 0x80 /* SDRAM Timing Reg */
#endif
#ifdef DCRN_OCM0_BASE
Quoted 3 lines · Joshua Williams
Various new ibm405 DCRN #defines.
Signed-off-by Joshua Williams <[email protected]>
May I ask what for ? :-) Also, it's all arch/ppc, not arch/powerpc... nothing we want to improve to much on at this stage unless there's a really good reason.
Cheers,
Ben.
Quoted 117 lines
--- arch/ppc/platforms/4xx/ibm405ep.h | 3 +++ arch/ppc/platforms/4xx/ibm405gp.h | 9 +++++++++ arch/ppc/platforms/4xx/ibm405gpr.h | 9 +++++++++ include/asm-ppc/ibm405.h | 27 +++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 0 deletions(-)arch/ppc/platforms/4xx/ibm405ep.h +3
-0@@ -139,6 +139,9 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_STATUS 0x24/* SDRAM Controller Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405EP_H__ */ arch/ppc/platforms/4xx/ibm405gp.h +9
-0@@ -142,6 +142,15 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_BESR0 0x00/* Bus Error Syndrome Reg 0 */ +#define DCRN_SDRAM0_BESR1 0x08/* Bus Error Syndrome Reg 1 */ +#define DCRN_SDRAM0_BEAR 0x10/* Bus Error Address Reg */ +#define DCRN_SDRAM0_B2CR 0x48/* Memory Bank 2 Configuration Reg */ +#define DCRN_SDRAM0_B3CR 0x4c/* Memory Bank 3 Configuration Reg */ +#define DCRN_SDRAM0_ECCCFG 0x94/* ECC Configuration */ +#define DCRN_SDRAM0_ECCESR 0x98/* ECC Error Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405GP_H__ */ arch/ppc/platforms/4xx/ibm405gpr.h +9
-0@@ -142,6 +142,15 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_BESR0 0x00/* Bus Error Syndrome Reg 0 */ +#define DCRN_SDRAM0_BESR1 0x08/* Bus Error Syndrome Reg 1 */ +#define DCRN_SDRAM0_BEAR 0x10/* Bus Error Address Reg */ +#define DCRN_SDRAM0_B2CR 0x48/* Memory Bank 2 Configuration Reg */ +#define DCRN_SDRAM0_B3CR 0x4c/* Memory Bank 3 Configuration Reg */ +#define DCRN_SDRAM0_ECCCFG 0x94/* ECC Configuration */ +#define DCRN_SDRAM0_ECCESR 0x98/* ECC Error Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405GPR_H__ */ include/asm-ppc/ibm405.h +0
-0@@ -135,6 +135,26 @@#ifdef DCRN_EBC_BASE #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0)/* Peripheral Controller Address */
#defineDCRN_EBCCFGDATA(DCRN_EBC_BASE+0x1) /* Peripheral Controller
Data */include/asm-ppc/ibm405.h +20
-0+#define DCRN_EBC_PB0CR 0x00/* Peripheral Bank 0 Config Reg */ +#define DCRN_EBC_PB1CR 0x01/* Peripheral Bank 1 Config Reg */ +#define DCRN_EBC_PB2CR 0x02/* Peripheral Bank 2 Config Reg */ +#define DCRN_EBC_PB3CR 0x03/* Peripheral Bank 3 Config Reg */ +#define DCRN_EBC_PB4CR 0x04/* Peripheral Bank 4 Config Reg */ +#define DCRN_EBC_PB5CR 0x05/* Peripheral Bank 5 Config Reg */ +#define DCRN_EBC_PB6CR 0x06/* Peripheral Bank 6 Config Reg */ +#define DCRN_EBC_PB7CR 0x07/* Peripheral Bank 7 Config Reg */ +#define DCRN_EBC_PB0AP 0x10/* Peripheral Bank 0 Access Parameters */ +#define DCRN_EBC_PB1AP 0x11/* Peripheral Bank 1 Access parameters */ +#define DCRN_EBC_PB2AP 0x12/* Peripheral Bank 2 Access Parameters */ +#define DCRN_EBC_PB3AP 0x13/* Peripheral Bank 3 Access Parameters */ +#define DCRN_EBC_PB4AP 0x14/* Peripheral Bank 4 Access Parameters */ +#define DCRN_EBC_PB5AP 0x15/* Peripheral Bank 5 Access Parameters */ +#define DCRN_EBC_PB6AP 0x16/* Peripheral Bank 6 Access Parameters */ +#define DCRN_EBC_PB7AP 0x17/* Peripheral Bank 7 Access Parameters */ +#define DCRN_EBC_PBEAR 0x20/* Peripheral Bus Error Address Reg */ +#define DCRN_EBC_PBESR0 0x21/* Peripheral Bus Error Status Reg 0 */ +#define DCRN_EBC_PBESR1 0x22/* Peripheral Bus Error Status Reg 1 */ +#define DCRN_EBC_EPCR 0x23/* External Peripheral Control Reg */ #endif #ifdef DCRN_EXIER_BASE @@ -286,6 +306,13 @@#ifdef DCRN_SDRAM0_BASE #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0)/* Memory Controller Address */
#defineDCRN_SDRAM0_CFGDATA(DCRN_SDRAM0_BASE+0x1) /* Memory
Controller Data */include/asm-ppc/ibm405.h +7
-0+#define DCRN_SDRAM0_CFG 0x20/* SDRAM Configuration */ +#define DCRN_SDRAM0_STATUS 0x24/* SDRAM Controller Status */ +#define DCRN_SDRAM0_RTR 0x30/* Refresh Timer Reg */ +#define DCRN_SDRAM0_PMIT 0x34/* Power Management Idle Timer */ +#define DCRN_SDRAM0_B0CR 0x40/* Memory Bank 0 Configuration Reg */ +#define DCRN_SDRAM0_B1CR 0x44/* Memory Bank 1 Configuration Reg */ +#define DCRN_SDRAM0_TR 0x80/* SDRAM Timing Reg */ #endif #ifdef DCRN_OCM0_BASE _______________________________________________
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Quoted 8 lines · Benjamin Herrenschmidt
Quoted 3 lines · Joshua Williams
Various new ibm405 DCRN #defines.
Signed-off-by Joshua Williams <[email protected]>May I ask what for ? :-) Also, it's all
arch/ppc, notarch/powerpc... nothing we want to improve to much on at this stage unless there's a really good reason.
The 405x #defines were incomplete and this was meant to make them a bit tighter. Since arch/ppc is in life support mode this can wait until the 405x stuff gets moved over to arch/powerpc.
Thanks!
- Josh
Quoted 116 lines
Quoted 114 lines
--- arch/ppc/platforms/4xx/ibm405ep.h | 3 +++ arch/ppc/platforms/4xx/ibm405gp.h | 9 +++++++++ arch/ppc/platforms/4xx/ibm405gpr.h | 9 +++++++++ include/asm-ppc/ibm405.h | 27 +++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 0 deletions(-)arch/ppc/platforms/4xx/ibm405ep.h +3
-0@@ -139,6 +139,9 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_STATUS 0x24/* SDRAM Controller Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405EP_H__ */ arch/ppc/platforms/4xx/ibm405gp.h +9
-0@@ -142,6 +142,15 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_BESR0 0x00/* Bus Error Syndrome Reg 0 */ +#define DCRN_SDRAM0_BESR1 0x08/* Bus Error Syndrome Reg 1 */ +#define DCRN_SDRAM0_BEAR 0x10/* Bus Error Address Reg */ +#define DCRN_SDRAM0_B2CR 0x48/* Memory Bank 2 Configuration Reg */ +#define DCRN_SDRAM0_B3CR 0x4c/* Memory Bank 3 Configuration Reg */ +#define DCRN_SDRAM0_ECCCFG 0x94/* ECC Configuration */ +#define DCRN_SDRAM0_ECCESR 0x98/* ECC Error Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405GP_H__ */ arch/ppc/platforms/4xx/ibm405gpr.h +9
-0@@ -142,6 +142,15 @@#define DCRN_UIC0_BASE 0x0C0#define UIC0 DCRN_UIC0_BASE +/* DCRN_SDRAM0_BASE offsets - general 405 offsets in asm/ibm405.h */ +#define DCRN_SDRAM0_BESR0 0x00/* Bus Error Syndrome Reg 0 */ +#define DCRN_SDRAM0_BESR1 0x08/* Bus Error Syndrome Reg 1 */ +#define DCRN_SDRAM0_BEAR 0x10/* Bus Error Address Reg */ +#define DCRN_SDRAM0_B2CR 0x48/* Memory Bank 2 Configuration Reg */ +#define DCRN_SDRAM0_B3CR 0x4c/* Memory Bank 3 Configuration Reg */ +#define DCRN_SDRAM0_ECCCFG 0x94/* ECC Configuration */ +#define DCRN_SDRAM0_ECCESR 0x98/* ECC Error Status */ +#include <asm/ibm405.h> #endif /* __ASM_IBM405GPR_H__ */ include/asm-ppc/ibm405.h +0
-0@@ -135,6 +135,26 @@#ifdef DCRN_EBC_BASE #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0)/* Peripheral Controller Address */
#defineDCRN_EBCCFGDATA(DCRN_EBC_BASE+0x1) /* Peripheral Controller
Data */include/asm-ppc/ibm405.h +20
-0+#define DCRN_EBC_PB0CR 0x00/* Peripheral Bank 0 Config Reg */ +#define DCRN_EBC_PB1CR 0x01/* Peripheral Bank 1 Config Reg */ +#define DCRN_EBC_PB2CR 0x02/* Peripheral Bank 2 Config Reg */ +#define DCRN_EBC_PB3CR 0x03/* Peripheral Bank 3 Config Reg */ +#define DCRN_EBC_PB4CR 0x04/* Peripheral Bank 4 Config Reg */ +#define DCRN_EBC_PB5CR 0x05/* Peripheral Bank 5 Config Reg */ +#define DCRN_EBC_PB6CR 0x06/* Peripheral Bank 6 Config Reg */ +#define DCRN_EBC_PB7CR 0x07/* Peripheral Bank 7 Config Reg */ +#define DCRN_EBC_PB0AP 0x10/* Peripheral Bank 0 Access Parameters */ +#define DCRN_EBC_PB1AP 0x11/* Peripheral Bank 1 Access parameters */ +#define DCRN_EBC_PB2AP 0x12/* Peripheral Bank 2 Access Parameters */ +#define DCRN_EBC_PB3AP 0x13/* Peripheral Bank 3 Access Parameters */ +#define DCRN_EBC_PB4AP 0x14/* Peripheral Bank 4 Access Parameters */ +#define DCRN_EBC_PB5AP 0x15/* Peripheral Bank 5 Access Parameters */ +#define DCRN_EBC_PB6AP 0x16/* Peripheral Bank 6 Access Parameters */ +#define DCRN_EBC_PB7AP 0x17/* Peripheral Bank 7 Access Parameters */ +#define DCRN_EBC_PBEAR 0x20/* Peripheral Bus Error Address Reg */ +#define DCRN_EBC_PBESR0 0x21/* Peripheral Bus Error Status Reg 0 */ +#define DCRN_EBC_PBESR1 0x22/* Peripheral Bus Error Status Reg 1 */ +#define DCRN_EBC_EPCR 0x23/* External Peripheral Control Reg */ #endif #ifdef DCRN_EXIER_BASE @@ -286,6 +306,13 @@#ifdef DCRN_SDRAM0_BASE #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0)/* Memory Controller Address */
#defineDCRN_SDRAM0_CFGDATA(DCRN_SDRAM0_BASE+0x1) /* Memory
Controller Data */include/asm-ppc/ibm405.h +7
-0+#define DCRN_SDRAM0_CFG 0x20/* SDRAM Configuration */ +#define DCRN_SDRAM0_STATUS 0x24/* SDRAM Controller Status */ +#define DCRN_SDRAM0_RTR 0x30/* Refresh Timer Reg */ +#define DCRN_SDRAM0_PMIT 0x34/* Power Management Idle Timer */ +#define DCRN_SDRAM0_B0CR 0x40/* Memory Bank 0 Configuration Reg */ +#define DCRN_SDRAM0_B1CR 0x44/* Memory Bank 1 Configuration Reg */ +#define DCRN_SDRAM0_TR 0x80/* SDRAM Timing Reg */ #endif #ifdef DCRN_OCM0_BASE _______________________________________________
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Quoted 6 lines · On Tue, 22 Jan 2008 11:08:38 -0600 Joshua Williams…
Quoted 5 lines · Benjamin Herrenschmidt
Quoted 3 lines · Joshua Williams
Various new ibm405 DCRN #defines.
Signed-off-by Joshua Williams <[email protected]>
Quoted 8 lines
Quoted 3 lines
May I ask what for ? :-) Also, it's all
arch/ppc, notarch/powerpc... nothing we want to improve to much on at this stage unless there's a really good reason.The 405x #defines were incomplete and this was meant to make them a bit tighter. Since
arch/ppcis in life support mode this can wait until the 405x stuff gets moved over toarch/powerpc.
Which 405x stuff? Walnut is moved over already. Other boards will need to be ported by people that have those boards.
josh
Quoted 11 lines · Josh Boyer
Quoted 8 lines · On Tue, 22 Jan 2008 11:08:38 -0600 Joshua Williams…
Quoted 7 lines · Benjamin Herrenschmidt
Quoted 3 lines · Joshua Williams
Various new ibm405 DCRN #defines.
Signed-off-by Joshua Williams <[email protected]>May I ask what for ? :-) Also, it's all
arch/ppc, notarch/powerpc... nothing we want to improve to much on at this stage unless there's a really good reason.
Quoted 7 lines
Quoted 4 lines
The 405x #defines were incomplete and this was meant to make them a bit tighter. Since
arch/ppcis in life support mode this can wait until the 405x stuff gets moved over toarch/powerpc.Which 405x stuff? Walnut is moved over already. Other boards will need to be ported by people that have those boards.
Gotcha. I'll revisit this once everything has been moved over.
- Josh
Quoted 17 lines · On Tue, 22 Jan 2008 13:15:07 -0600 Joshua Williams…
Quoted 16 lines · Josh Boyer
Quoted 12 lines · On Tue, 22 Jan 2008 11:08:38 -0600 Joshua Williams…
Quoted 7 lines · Benjamin Herrenschmidt
Quoted 3 lines · Joshua Williams
Various new ibm405 DCRN #defines.
Signed-off-by Joshua Williams <[email protected]>May I ask what for ? :-) Also, it's all
arch/ppc, notarch/powerpc... nothing we want to improve to much on at this stage unless there's a really good reason.The 405x #defines were incomplete and this was meant to make them a bit tighter. Since
arch/ppcis in life support mode this can wait until the 405x stuff gets moved over toarch/powerpc.
Quoted 4 lines
Quoted 2 lines
Which 405x stuff? Walnut is moved over already. Other boards will need to be ported by people that have those boards.
Gotcha. I'll revisit this once everything has been moved over.
Sorry, maybe Ben and I aren't being clear. 405GP (Walnut) support is in arch/powerpc. There is also support for 405EX and 405EXr. The arch/ppc tree is going to die in June, whether the rest of the 405 boards are ported or not.
So are you trying to add defines for a new board, or? I don't see much of a reason not to go ahead and do what you're doing now rather than later but I'll leave that up to you :)
josh
Quoted 13 lines · Josh Boyer
Quoted 10 lines · On Tue, 22 Jan 2008 11:08:38 -0600 Joshua Williams…
Quoted 8 lines · Benjamin Herrenschmidt
Quoted 3 lines · Joshua Williams
Various new ibm405 DCRN #defines.
Signed-off-by Joshua Williams <[email protected]>May I ask what for ? :-) Also, it's all
arch/ppc, notarch/powerpc... nothing we want to improve to much on at this stage unless there's a really good reason.
Quoted 7 lines
Quoted 4 lines
The 405x #defines were incomplete and this was meant to make them a bit tighter. Since
arch/ppcis in life support mode this can wait until the 405x stuff gets moved over toarch/powerpc.Which 405x stuff? Walnut is moved over already. Other boards will need to be ported by people that have those boards.
I have no objection with adding #define's to arch/powerpc somewhere though I'd like to avoid having 36 different .h files per processor type.
Ben.
Quoted 9 lines · Joshua Williams
Various new ibm405 DCRN #defines.
Signed-off-by Joshua Williams <[email protected]>--- arch/ppc/platforms/4xx/ibm405ep.h | 3 +++ arch/ppc/platforms/4xx/ibm405gp.h | 9 +++++++++ arch/ppc/platforms/4xx/ibm405gpr.h | 9 +++++++++ include/asm-ppc/ibm405.h | 27 +++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 0 deletions(-)
Changes like this should only be done in conjunction with drivers/board support patches which actually use them.
Cheers,
g.
Signature · 2 lines
Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd.