gxfb: clean up register definitions
PATCH 2/6 gxfb: clean up register definitions
Note: this is a continuation of prior gxfb patches, and also depends upon the MSR cleanup patch. All those patches can be found here:
http://git.infradead.org/?p=geode.git;a=summary
This one simply makes register definitions consistent w/ the data book, saving much sanity when attempting to double-check that register handling is correct (especially in the later power management patches).
From 38f7c2c2032c96bcd86c26771d06909e81aacca9 Mon Sep 17 00:00:00 2001
From: Andres Salomon <[email protected]>
Date: Mon, 25 Feb 2008 13:12:14 -0500
Subject: [PATCH] gxfb: clean up register definitions
This does the following in preparation for register saving:
- moves the register definitions from video_gx.h and display_gx.h into
gxfb.h.
- renames GX_* registers to match their section (ie, VP_).
- renames register bitfields to match the data sheet (ie,
DC_DCFG_TGEN -> DC_DISPLAY_CFG_TGEN). - for DC registers, rather than defining to specific addresses, use an enum to number them sequentially and just multiply by 4(bytes) to access them (in read_dc/write_dc).
- for VP and FP registers, use an enum and multiple by 8 (bytes). They're 64bit registers.
Signed-off-by Andres Salomon <[email protected]>
--- drivers/video/geode/display_gx.c | 28 +++--- drivers/video/geode/display_gx.h | 78 -------------- drivers/video/geode/gxfb.h | 220 ++++++++++++++++++++++++++++++++++++- drivers/video/geode/video_gx.c | 92 ++++++++-------- drivers/video/geode/video_gx.h | 39 ------- 5 files changed, 275 insertions(+), 182 deletions(-)
drivers/video/geode/display_gx.c +15 -13
@@ -51,20 +51,21 @@ static void gx_set_mode(struct fb_info *info)int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;/* Unlock the display controller registers. */ -write_dc (DC_UNLOCK ,DC_UNLOCK_CODE ); +write_dc (DC_UNLOCK ,DC_UNLOCK_UNLOCK ); gcfg =read_dc (DC_GENERAL_CFG ); dcfg =read_dc (DC_DISPLAY_CFG );/* Disable the timing generator. */ - dcfg &= ~(DC_DCFG_TGEN ); + dcfg &= ~DC_DISPLAY_CFG_TGEN ;write_dc (DC_DISPLAY_CFG , dcfg);/* Wait for pending memory requests before disabling the FIFO load. */ udelay (100 );/* Disable FIFO load and compression. */ - gcfg &= ~(DC_GCFG_DFLE |DC_GCFG_CMPE |DC_GCFG_DECE ); + gcfg &= ~(DC_GENERAL_CFG_DFLE |DC_GENERAL_CFG_CMPE | +DC_GENERAL_CFG_DECE );write_dc (DC_GENERAL_CFG , gcfg);/* Setup DCLK and its divisor. */
@@ -75,12 +76,13 @@ static void gx_set_mode(struct fb_info *info)*/ /* Clear all unused feature bits. */ - gcfg &=DC_GCFG_YUVM |DC_GCFG_VDSE ; + gcfg &=DC_GENERAL_CFG_YUVM |DC_GENERAL_CFG_VDSE ; dcfg =0 ;/* Set FIFO priority (default 6/5) and enable. */ /* FIXME: increase fifo priority for 1280x1024 and higher modes? */ - gcfg |= (6 <<DC_GCFG_DFHPEL_POS ) | (5 <<DC_GCFG_DFHPSL_POS ) |DC_GCFG_DFLE ; + gcfg |= (6 <<DC_GENERAL_CFG_DFHPEL_SHIFT ) | + (5 <<DC_GENERAL_CFG_DFHPSL_SHIFT ) |DC_GENERAL_CFG_DFLE ;/* Framebuffer start offset. */ write_dc (DC_FB_ST_OFFSET ,0 );
@@ -92,25 +94,25 @@ static void gx_set_mode(struct fb_info *info)/* Enable graphics and video data and unmask address lines. */ - dcfg |=DC_DCFG_GDEN |DC_DCFG_VDEN |DC_DCFG_A20M |DC_DCFG_A18M ; + dcfg |=DC_DISPLAY_CFG_GDEN |DC_DISPLAY_CFG_VDEN | +DC_DISPLAY_CFG_A20M |DC_DISPLAY_CFG_A18M ;/* Set pixel format. */ switch (info->var.bits_per_pixel) {case 8 : - dcfg |=DC_DCFG_DISP_MODE_8BPP ; + dcfg |=DC_DISPLAY_CFG_DISP_MODE_8BPP ;break ;case 16 : - dcfg |=DC_DCFG_DISP_MODE_16BPP ; - dcfg |=DC_DCFG_16BPP_MODE_565 ; + dcfg |=DC_DISPLAY_CFG_DISP_MODE_16BPP ;break ;case 32 : - dcfg |=DC_DCFG_DISP_MODE_24BPP ; - dcfg |=DC_DCFG_PALB ; + dcfg |=DC_DISPLAY_CFG_DISP_MODE_24BPP ; + dcfg |=DC_DISPLAY_CFG_PALB ;break ; }/* Enable timing generator. */ - dcfg |=DC_DCFG_TGEN ; + dcfg |=DC_DISPLAY_CFG_TGEN ;/* Horizontal and vertical timings. */ hactive = info->var.xres;
@@ -144,7 +146,7 @@ static void gx_set_mode(struct fb_info *info) par->vid_ops->configure_display (info);/* Relock display controller registers */ -write_dc (DC_UNLOCK ,0 ); +write_dc (DC_UNLOCK ,DC_UNLOCK_LOCK ); } static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
drivers/video/geode/display_gx.h +0 -78
82 lines not on this page · raw message
drivers/video/geode/gxfb.h +214 -6
229 lines not on this page · raw message
drivers/video/geode/video_gx.c +46 -46
170 lines not on this page · raw message
drivers/video/geode/video_gx.h +0 -39
@@ -17,45 +17,6 @@ extern struct geode_vid_ops gx_vid_ops;#define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF#define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF -/* Geode GX video processor registers */ - -#define GX_DCFG 0x0008 -# define GX_DCFG_CRT_EN 0x00000001 -# define GX_DCFG_HSYNC_EN 0x00000002 -# define GX_DCFG_VSYNC_EN 0x00000004 -# define GX_DCFG_DAC_BL_EN 0x00000008 -# define GX_DCFG_FP_PWR_EN 0x00000040 -# define GX_DCFG_FP_DATA_EN 0x00000080 -# define GX_DCFG_CRT_HSYNC_POL 0x00000100 -# define GX_DCFG_CRT_VSYNC_POL 0x00000200 -# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 -# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000 -# define GX_DCFG_VG_CK 0x00100000 -# define GX_DCFG_GV_GAM 0x00200000 -# define GX_DCFG_DAC_VREF 0x04000000 - -/* Geode GX MISC video configuration */ - -#define GX_MISC 0x50 -#define GX_MISC_GAM_EN 0x00000001 -#define GX_MISC_DAC_PWRDN 0x00000400 -#define GX_MISC_A_PWRDN 0x00000800 - -/* Geode GX flat panel display control registers */ - -#define GX_FP_PT1 0x0400 -#define GX_FP_PT1_VSIZE_MASK 0x7FF0000 -#define GX_FP_PT1_VSIZE_SHIFT 16 - -#define GX_FP_PT2 0x408 -#define GX_FP_PT2_VSP (1 << 23) -#define GX_FP_PT2_HSP (1 << 22) - -#define GX_FP_PM 0x410 -# define GX_FP_PM_P 0x01000000 - -#define GX_FP_DFC 0x418 -/* Geode GX clock control MSRs */ # define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
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