rtc: Add M41T62 support

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index 3978773..c882720 100644
@@ -29,6 +29,11 @@
   |
   +-----------------------------------------------------------------------------*/
 
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>

@@ -38,7 +43,10 @@
 #include <405_mal.h>
 #include <miiphy.h>
 
-#undef ET_DEBUG
+#if !defined(CONFIG_PHY_CLK_FREQ)
+#define CONFIG_PHY_CLK_FREQ	0
+#endif
+
 /***********************************************************/
 /* Dump out to the screen PHY regs			   */
 /***********************************************************/

@@ -164,9 +172,21 @@ int phy_setup_aneg (char *devname, unsigned char addr)
 /***********************************************************/
 /* read a phy reg and return the value with a rc	   */
 /***********************************************************/
+/* AMCC_TODO:
+ * Find out of the choice for the emac for MDIO is from the bridges,
+ * i.e. ZMII or RGMII as approporiate.  If the bridges are not used
+ * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL]
+ * used?  If so, then this routine below does not apply to the 460EX/GT.
+ *
+ * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
+ * return EMAC0 offset here
+ */
 unsigned int miiphy_getemac_offset (void)
 {
-#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI)
+#if (defined(CONFIG_440) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_460EX) && !defined(CONFIG_460GT)) && \
+    defined(CONFIG_NET_MULTI)
 	unsigned long zmii;
 	unsigned long eoffset;
 

@@ -217,153 +237,97 @@ unsigned int miiphy_getemac_offset (void)
 #endif
 }
 
-int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
-			 unsigned short *value)
+static int emac_miiphy_wait(u32 emac_reg)
 {
-	unsigned long sta_reg;	/* STA scratch area */
-	unsigned long i;
-	unsigned long emac_reg;
+	u32 sta_reg;
+	int i;
 
-	emac_reg = miiphy_getemac_offset ();
-	/* see if it is ready for 1000 nsec */
+	/* wait for completion */
 	i = 0;
-
-	/* see if it is ready for  sec */
-	while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
-	       EMAC_STACR_OC_MASK) {
-		udelay (7);
-		if (i > 5) {
-#ifdef ET_DEBUG
-			sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-			printf ("read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
-			printf ("read err 1\n");
-#endif
+	do {
+		sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
+		if (i++ > 5) {
+			debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__,
+			      __LINE__, sta_reg);
 			return -1;
 		}
-		i++;
-	}
+		udelay(10);
+	} while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK);
+
+	return 0;
+}
+
+static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
+{
+	u32 emac_reg;
+	u32 sta_reg;
+
+	emac_reg = miiphy_getemac_offset();
+
+	/* wait for completion */
+	if (emac_miiphy_wait(emac_reg) != 0)
+		return -1;
+
 	sta_reg = reg;		/* reg address */
+
 	/* set clock (50Mhz) and read flags */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 #if defined(CONFIG_IBM_EMAC4_V4)	/* EMAC4 V4 changed bit setting */
-	sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
+	sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
 #else
-	sta_reg |= EMAC_STACR_READ;
+	sta_reg |= cmd;
 #endif
 #else
-	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+	sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
 #endif
 
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
-    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
-    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
-    !defined(CONFIG_405EX)
+	/* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
 	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
-#endif
-	sta_reg = sta_reg | (addr << 5);	/* Phy address */
+	sta_reg = sta_reg | ((u32)addr << 5);	/* Phy address */
 	sta_reg = sta_reg | EMAC_STACR_OC_MASK;	/* new IBM emac v4 */
+	if (cmd == EMAC_STACR_WRITE)
+		memcpy(&sta_reg, &value, 2);	/* put in data */
+
 	out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
-#ifdef ET_DEBUG
-	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
-#endif
+	debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
 
-	sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
-	printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
-#endif
-	i = 0;
-	while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
-		udelay (7);
-		if (i > 5)
-			return -1;
+	/* wait for completion */
+	if (emac_miiphy_wait(emac_reg) != 0)
+		return -1;
 
-		i++;
-		sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
-		printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
-#endif
-	}
+	debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
 	if ((sta_reg & EMAC_STACR_PHYE) != 0)
 		return -1;
 
-	*value = *(short *)(&sta_reg);
 	return 0;
+}
 
-}				/* phy_read */
-
-/***********************************************************/
-/* write a phy reg and return the value with a rc	    */
-/***********************************************************/
-
-int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg,
-			  unsigned short value)
+int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
+			 unsigned short *value)
 {
-	unsigned long sta_reg;	/* STA scratch area */
-	unsigned long i;
+	unsigned long sta_reg;
 	unsigned long emac_reg;
 
 	emac_reg = miiphy_getemac_offset ();
-	/* see if it is ready for 1000 nsec */
-	i = 0;
-
-	while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) ==
-	       EMAC_STACR_OC_MASK) {
-		if (i > 5)
-			return -1;
-
-		udelay (7);
-		i++;
-	}
-	sta_reg = 0;
-	sta_reg = reg;		/* reg address */
-	/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_405EX)
-#if defined(CONFIG_IBM_EMAC4_V4)	/* EMAC4 V4 changed bit setting */
-	sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
-#else
-	sta_reg |= EMAC_STACR_WRITE;
-#endif
-#else
-	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
-#endif
-
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
-    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
-    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
-    !defined(CONFIG_405EX)
-	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;	/* Set clock frequency (PLB freq. dependend) */
-#endif
-	sta_reg = sta_reg | ((unsigned long)addr << 5);	/* Phy address */
-	sta_reg = sta_reg | EMAC_STACR_OC_MASK;	/* new IBM emac v4 */
-	memcpy (&sta_reg, &value, 2);	/* put in data */
 
-	out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
+	if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
+		return -1;
 
-	/* wait for completion */
-	i = 0;
 	sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
-	printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
-#endif
-	while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
-		udelay (7);
-		if (i > 5)
-			return -1;
-
-		i++;
-		sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
-#ifdef ET_DEBUG
-		printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
-#endif
-	}
-
-	if ((sta_reg & EMAC_STACR_PHYE) != 0)
-		return -1;
+	*value = *(u16 *)(&sta_reg);
 
 	return 0;
+}
 
-} /* phy_write */
+/***********************************************************/
+/* write a phy reg and return the value with a rc	    */
+/***********************************************************/
+
+int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg,
+			  unsigned short value)
+{
+	return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value);
+}

index d3c2233..0b16b50 100644
@@ -70,8 +70,6 @@ void dflush(void);
 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
 	/* disable caching on DDR2 */
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
-
 void board_add_ram_info(int use_default)
 {
 	PPC4xx_SYS_INFO board_cfg;

index ed493f1..2bfcba1 100644
@@ -31,9 +31,9 @@
 #include <asm/mmu.h>
 
 typedef struct region {
-	unsigned long base;
-	unsigned long size;
-	unsigned long tlb_word2_i_value;
+	u64 base;
+	u32 size;
+	u32 tlb_word2_i_value;
 } region_t;
 
 void remove_tlb(u32 vaddr, u32 size)

@@ -182,10 +182,10 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
 	asm("isync");
 }
 
-static int add_tlb_entry(unsigned long phys_addr,
-			 unsigned long virt_addr,
-			 unsigned long tlb_word0_size_value,
-			 unsigned long tlb_word2_i_value)
+static int add_tlb_entry(u64 phys_addr,
+			 u32 virt_addr,
+			 u32 tlb_word0_size_value,
+			 u32 tlb_word2_i_value)
 {
 	int i;
 	unsigned long tlb_word0_value;

@@ -204,7 +204,8 @@ static int add_tlb_entry(unsigned long phys_addr,
 	/* Second, create the TLB entry */
 	tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
 		TLB_WORD0_TS_0 | tlb_word0_size_value;
-	tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
+	tlb_word1_value = TLB_WORD1_RPN_ENCODE((u32)phys_addr) |
+		TLB_WORD1_ERPN_ENCODE(phys_addr >> 32);
 	tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
 		TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
 		TLB_WORD2_W_DISABLE | tlb_word2_i_value |

@@ -228,10 +229,10 @@ static int add_tlb_entry(unsigned long phys_addr,
 	return 0;
 }
 
-static void program_tlb_addr(unsigned long phys_addr,
-			     unsigned long virt_addr,
-			     unsigned long mem_size,
-			     unsigned long tlb_word2_i_value)
+static void program_tlb_addr(u64 phys_addr,
+			     u32 virt_addr,
+			     u32 mem_size,
+			     u32 tlb_word2_i_value)
 {
 	int rc;
 	int tlb_i;

@@ -331,7 +332,7 @@ static void program_tlb_addr(unsigned long phys_addr,
  * Common usage for boards with SDRAM DIMM modules to dynamically
  * configure the TLB's for the SDRAM
  */
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
+void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
 {
 	region_t region_array;
 

index 5af22af..49d6860 100644
@@ -549,14 +549,14 @@ extern int num_tlb_entries;
 /*----------------------------------------------------------------------------+
 | TLB specific defines.
 +----------------------------------------------------------------------------*/
-#define TLB_256MB_ALIGN_MASK 0xF0000000
-#define TLB_16MB_ALIGN_MASK  0xFF000000
-#define TLB_1MB_ALIGN_MASK   0xFFF00000
-#define TLB_256KB_ALIGN_MASK 0xFFFC0000
-#define TLB_64KB_ALIGN_MASK  0xFFFF0000
-#define TLB_16KB_ALIGN_MASK  0xFFFFC000
-#define TLB_4KB_ALIGN_MASK   0xFFFFF000
-#define TLB_1KB_ALIGN_MASK   0xFFFFFC00
+#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
+#define TLB_16MB_ALIGN_MASK  0xFFF000000ULL
+#define TLB_1MB_ALIGN_MASK   0xFFFF00000ULL
+#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
+#define TLB_64KB_ALIGN_MASK  0xFFFFF0000ULL
+#define TLB_16KB_ALIGN_MASK  0xFFFFFC000ULL
+#define TLB_4KB_ALIGN_MASK   0xFFFFFF000ULL
+#define TLB_1KB_ALIGN_MASK   0xFFFFFFC00ULL
 #define TLB_256MB_SIZE       0x10000000
 #define TLB_16MB_SIZE        0x01000000
 #define TLB_1MB_SIZE         0x00100000

@@ -697,7 +697,7 @@ unsigned long mftlb1(unsigned long index);
 unsigned long mftlb2(unsigned long index);
 unsigned long mftlb3(unsigned long index);
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
+void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 void remove_tlb(u32 vaddr, u32 size);
 void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
 #endif /* __ASSEMBLY__ */

index c86a150..466ca92 100644
@@ -42,8 +42,6 @@
 
 #define CACHE_POST_SIZE	1024
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
-
 int cache_post_test1 (int tlb, void *p, int size);
 int cache_post_test2 (int tlb, void *p, int size);
 int cache_post_test3 (int tlb, void *p, int size);

index 2f3dc32..698bcb5 100644
@@ -38,7 +38,22 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/****************************************************************************/
+/*
+ * Define the number of UIC's
+ */
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define UIC_MAX		4
+#elif defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_405EX)
+#define UIC_MAX		3
+#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define UIC_MAX		2
+#else
+#define UIC_MAX		1
+#endif
 
 /*
  * CPM interrupt vector functions.

@@ -49,28 +64,15 @@ struct	irq_action {
 	int count;
 };
 
-static struct irq_action irq_vecs[32];
-void uic0_interrupt( void * parms); /* UIC0 handler */
+static struct irq_action irq_vecs[UIC_MAX * 32];
 
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-static struct irq_action irq_vecs1[32]; /* For UIC1 */
+u32 get_dcr(u16);
+void set_dcr(u16, u32);
 
-void uic1_interrupt( void * parms); /* UIC1 handler */
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-static struct irq_action irq_vecs2[32]; /* For UIC2 */
-void uic2_interrupt( void * parms); /* UIC2 handler */
-#endif /* CONFIG_440GX CONFIG_440SPE */
-
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-static struct irq_action irq_vecs3[32]; /* For UIC3 */
-void uic3_interrupt( void * parms); /* UIC3 handler */
-#endif /* CONFIG_440SPE */
-
-#endif /* CONFIG_440 */
+#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
+static void uic_cascade_interrupt(void *para);
+#endif
 
-/****************************************************************************/
 #if defined(CONFIG_440)
 
 /* SPRN changed in 440 */

@@ -99,8 +101,6 @@ static __inline__ void set_evpr(unsigned long val)
 }
 #endif /* defined(CONFIG_440 */
 
-/****************************************************************************/
-
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
 	int vec;

@@ -112,26 +112,10 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	/*
 	 * Mark all irqs as free
 	 */
-	for (vec=0; vec<32; vec++) {
+	for (vec = 0; vec < (UIC_MAX * 32); vec++) {
 		irq_vecs[vec].handler = NULL;
 		irq_vecs[vec].arg = NULL;
 		irq_vecs[vec].count = 0;
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-		irq_vecs1[vec].handler = NULL;
-		irq_vecs1[vec].arg = NULL;
-		irq_vecs1[vec].count = 0;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-		irq_vecs2[vec].handler = NULL;
-		irq_vecs2[vec].arg = NULL;
-		irq_vecs2[vec].count = 0;
-#endif /* CONFIG_440GX */
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-		irq_vecs3[vec].handler = NULL;
-		irq_vecs3[vec].arg = NULL;
-		irq_vecs3[vec].count = 0;
-#endif /* CONFIG_440SPE */
-#endif
 	}
 
 #ifdef CONFIG_4xx

@@ -172,15 +156,21 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	 */
 	set_evpr(0x00000000);
 
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
 #if !defined(CONFIG_440GX)
+#if (UIC_MAX > 1)
 	/* Install the UIC1 handlers */
-	irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
-	irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
+	irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0);
+	irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0);
 #endif
+#if (UIC_MAX > 2)
+	irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0);
+	irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0);
 #endif
-
-#if defined(CONFIG_440GX)
+#if (UIC_MAX > 3)
+	irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0);
+	irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0);
+#endif
+#else /* !defined(CONFIG_440GX) */
 	/* Take the GX out of compatibility mode
 	 * Travis Sawyer, 9 Mar 2004
 	 * NOTE: 440gx user manual inconsistency here

@@ -196,110 +186,24 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	mtdcr(uicb0er, 0x54000000);
 	/* None are critical */
 	mtdcr(uicb0cr, 0);
-#endif
+#endif /* !defined(CONFIG_440GX) */
 
 	return (0);
 }
 
-/****************************************************************************/
-
-/*
- * Handle external interrupts
- */
-#if defined(CONFIG_440GX)
-void external_interrupt(struct pt_regs *regs)
+/* Handler for UIC interrupt */
+static void uic_interrupt(u32 uic_base, int vec_base)
 {
-	ulong uic_msr;
-
-	/*
-	 * Read masked interrupt status register to determine interrupt source
-	 */
-	/* 440 GX uses base uic register */
-	uic_msr = mfdcr(uicb0msr);
-
-	if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
-		uic0_interrupt(0);
-
-	if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
-		uic1_interrupt(0);
-
-	if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
-		uic2_interrupt(0);
-
-	mtdcr(uicb0sr, uic_msr);
-
-	return;
-
-} /* external_interrupt CONFIG_440GX */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-void external_interrupt(struct pt_regs *regs)
-{
-	ulong uic_msr;
-
-	/*
-	 * Read masked interrupt status register to determine interrupt source
-	 */
-	/* 440 SPe uses base uic register */
-	uic_msr = mfdcr(uic0msr);
-
-	if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
-		uic1_interrupt(0);
-
-	if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
-		uic2_interrupt(0);
-
-	if (uic_msr & ~(UICB0_ALL))
-		uic0_interrupt(0);
-
-	mtdcr(uic0sr, uic_msr);
-
-	return;
-
-} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */
-
-#elif defined(CONFIG_440SPE)
-void external_interrupt(struct pt_regs *regs)
-{
-	ulong uic_msr;
-
-	/*
-	 * Read masked interrupt status register to determine interrupt source
-	 */
-	/* 440 SPe uses base uic register */
-	uic_msr = mfdcr(uic0msr);
-
-	if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
-		uic1_interrupt(0);
-
-	if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
-		uic2_interrupt(0);
-
-	if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) )
-		uic3_interrupt(0);
-
-	if (uic_msr & ~(UICB0_ALL))
-		uic0_interrupt(0);
-
-	mtdcr(uic0sr, uic_msr);
-
-	return;
-} /* external_interrupt CONFIG_440SPE */
-
-#else
-
-void external_interrupt(struct pt_regs *regs)
-{
-	ulong uic_msr;
-	ulong msr_shift;
+	u32 uic_msr;
+	u32 msr_shift;
 	int vec;
 
 	/*
 	 * Read masked interrupt status register to determine interrupt source
 	 */
-	uic_msr = mfdcr(uicmsr);
+	uic_msr = get_dcr(uic_base + UIC_MSR);
 	msr_shift = uic_msr;
-	vec = 0;
+	vec = vec_base;
 
 	while (msr_shift != 0) {
 		if (msr_shift & 0x80000000) {

@@ -312,14 +216,17 @@ void external_interrupt(struct pt_regs *regs)
 				/* call isr */
 				(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
 			} else {
-				mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
-				printf ("Masking bogus interrupt vector 0x%x\n", vec);
+				set_dcr(uic_base + UIC_ER,
+					get_dcr(uic_base + UIC_ER) &
+					~(0x80000000 >> vec));
+				printf("Masking bogus interrupt vector %d"
+				       " (UIC_BASE=0x%x)\n", vec, uic_base);
 			}
 
 			/*
 			 * After servicing the interrupt, we have to remove the status indicator.
 			 */
-			mtdcr(uicsr, (0x80000000 >> vec));
+			set_dcr(uic_base + UIC_SR, (0x80000000 >> vec));
 		}
 
 		/*

@@ -329,324 +236,150 @@ void external_interrupt(struct pt_regs *regs)
 		vec++;
 	}
 }
-#endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/* Handler for UIC0 interrupt */
-void uic0_interrupt( void * parms)
+#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
+static void uic_cascade_interrupt(void *para)
 {
-	ulong uic_msr;
-	ulong msr_shift;
-	int vec;
-
-	/*
-	 * Read masked interrupt status register to determine interrupt source
-	 */
-	uic_msr = mfdcr(uicmsr);
-	msr_shift = uic_msr;
-	vec = 0;
-
-	while (msr_shift != 0) {
-		if (msr_shift & 0x80000000) {
-			/*
-			 * Increment irq counter (for debug purpose only)
-			 */
-			irq_vecs[vec].count++;
-
-			if (irq_vecs[vec].handler != NULL) {
-				/* call isr */
-				(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
-			} else {
-				mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
-				printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec);
-			}
-
-			/*
-			 * After servicing the interrupt, we have to remove the status indicator.
-			 */
-			mtdcr(uicsr, (0x80000000 >> vec));
-		}
-
-		/*
-		 * Shift msr to next position and increment vector
-		 */
-		msr_shift <<= 1;
-		vec++;
-	}
+	external_interrupt(para);
 }
+#endif
 
-#endif /* CONFIG_440GX */
-
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-/* Handler for UIC1 interrupt */
-void uic1_interrupt( void * parms)
-{
-	ulong uic1_msr;
-	ulong msr_shift;
-	int vec;
-
-	/*
-	 * Read masked interrupt status register to determine interrupt source
-	 */
-	uic1_msr = mfdcr(uic1msr);
-	msr_shift = uic1_msr;
-	vec = 0;
-
-	while (msr_shift != 0) {
-		if (msr_shift & 0x80000000) {
-			/*
-			 * Increment irq counter (for debug purpose only)
-			 */
-			irq_vecs1[vec].count++;
-
-			if (irq_vecs1[vec].handler != NULL) {
-				/* call isr */
-				(*irq_vecs1[vec].handler)(irq_vecs1[vec].arg);
-			} else {
-				mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
-				printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
-			}
-
-			/*
-			 * After servicing the interrupt, we have to remove the status indicator.
-			 */
-			mtdcr(uic1sr, (0x80000000 >> vec));
-		}
-
-		/*
-		 * Shift msr to next position and increment vector
-		 */
-		msr_shift <<= 1;
-		vec++;
-	}
-}
-#endif /* defined(CONFIG_440) */
+#if defined(CONFIG_440)
+#if defined(CONFIG_440GX)
+/* 440GX uses base uic register */
+#define UIC_BMSR	uicb0msr
+#define UIC_BSR		uicb0sr
+#else
+#define UIC_BMSR	uic0msr
+#define UIC_BSR		uic0sr
+#endif
+#else /* CONFIG_440 */
+#define UIC_BMSR	uicmsr
+#define UIC_BSR		uicsr
+#endif /* CONFIG_440 */
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/* Handler for UIC2 interrupt */
-void uic2_interrupt( void * parms)
+/*
+ * Handle external interrupts
+ */
+void external_interrupt(struct pt_regs *regs)
 {
-	ulong uic2_msr;
-	ulong msr_shift;
-	int vec;
+	u32 uic_msr;
 
 	/*
 	 * Read masked interrupt status register to determine interrupt source
 	 */
-	uic2_msr = mfdcr(uic2msr);
-	msr_shift = uic2_msr;
-	vec = 0;
+	uic_msr = mfdcr(UIC_BMSR);
 
-	while (msr_shift != 0) {
-		if (msr_shift & 0x80000000) {
-			/*
-			 * Increment irq counter (for debug purpose only)
-			 */
-			irq_vecs2[vec].count++;
-
-			if (irq_vecs2[vec].handler != NULL) {
-				/* call isr */
-				(*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
-			} else {
-				mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
-				printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec);
-			}
-
-			/*
-			 * After servicing the interrupt, we have to remove the status indicator.
-			 */
-			mtdcr(uic2sr, (0x80000000 >> vec));
-		}
-
-		/*
-		 * Shift msr to next position and increment vector
-		 */
-		msr_shift <<= 1;
-		vec++;
-	}
-}
-#endif /* defined(CONFIG_440GX) */
-
-#if defined(CONFIG_440SPE)
-/* Handler for UIC3 interrupt */
-void uic3_interrupt( void * parms)
-{
-	ulong uic3_msr;
-	ulong msr_shift;
-	int vec;
+#if (UIC_MAX > 1)
+	if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr))
+		uic_interrupt(UIC1_DCR_BASE, 32);
+#endif
 
-	/*
-	 * Read masked interrupt status register to determine interrupt source
-	 */
-	uic3_msr = mfdcr(uic3msr);
-	msr_shift = uic3_msr;
-	vec = 0;
+#if (UIC_MAX > 2)
+	if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr))
+		uic_interrupt(UIC2_DCR_BASE, 64);
+#endif
 
-	while (msr_shift != 0) {
-		if (msr_shift & 0x80000000) {
-			/*
-			 * Increment irq counter (for debug purpose only)
-			 */
-			irq_vecs3[vec].count++;
+#if (UIC_MAX > 3)
+	if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr))
+		uic_interrupt(UIC3_DCR_BASE, 96);
+#endif
 
-			if (irq_vecs3[vec].handler != NULL) {
-				/* call isr */
-				(*irq_vecs3[vec].handler)(irq_vecs3[vec].arg);
-			} else {
-				mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec));
-				printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec);
-			}
+#if defined(CONFIG_440)
+#if !defined(CONFIG_440GX)
+	if (uic_msr & ~(UICB0_ALL))
+		uic_interrupt(UIC0_DCR_BASE, 0);
+#else
+	if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr))
+		uic_interrupt(UIC0_DCR_BASE, 0);
+#endif
+#else /* CONFIG_440 */
+	uic_interrupt(UIC0_DCR_BASE, 0);
+#endif /* CONFIG_440 */
 
-			/*
-			 * After servicing the interrupt, we have to remove the status indicator.
-			 */
-			mtdcr(uic3sr, (0x80000000 >> vec));
-		}
+	mtdcr(UIC_BSR, uic_msr);
 
-		/*
-		 * Shift msr to next position and increment vector
-		 */
-		msr_shift <<= 1;
-		vec++;
-	}
+	return;
 }
-#endif /* defined(CONFIG_440SPE) */
-
-/****************************************************************************/
 
 /*
  * Install and free a interrupt handler.
  */
-
-void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
+void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
 {
-	struct irq_action *irqa = irq_vecs;
-	int i = vec;
-
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	if ((vec > 31) && (vec < 64)) {
-		i = vec - 32;
-		irqa = irq_vecs1;
-	} else if (vec > 63) {
-		i = vec - 64;
-		irqa = irq_vecs2;
-	}
-#else  /* CONFIG_440GX */
-	if (vec > 31) {
-		i = vec - 32;
-		irqa = irq_vecs1;
-	}
-#endif /* CONFIG_440GX */
-#endif /* CONFIG_440 */
+	int i;
 
 	/*
-	 * print warning when replacing with a different irq vector
+	 * Print warning when replacing with a different irq vector
 	 */
-	if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) {
-		printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
-			vec, (uint) handler, (uint) irqa[i].handler);
+	if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) {
+		printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+		       vec, (uint) handler, (uint) irq_vecs[vec].handler);
 	}
-	irqa[i].handler = handler;
-	irqa[i].arg = arg;
-
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	if ((vec > 31) && (vec < 64))
-		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
-	else if (vec > 63)
-		mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
-	else
-#endif /* CONFIG_440GX */
-	if (vec > 31)
-		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
-	else
+	irq_vecs[vec].handler = handler;
+	irq_vecs[vec].arg = arg;
+
+	i = vec & 0x1f;
+	if ((vec >= 0) && (vec < 32))
+		mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
+#if (UIC_MAX > 1)
+	else if ((vec >= 32) && (vec < 64))
+		mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
+#endif
+#if (UIC_MAX > 2)
+	else if ((vec >= 64) && (vec < 96))
+		mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i));
 #endif
-		mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i));
-#if 0
-	printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
+#if (UIC_MAX > 3)
+	else if (vec >= 96)
+		mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i));
 #endif
+
+	debug("Install interrupt for vector %d ==> %p\n", vec, handler);
 }
 
 void irq_free_handler (int vec)
 {
-	struct irq_action *irqa = irq_vecs;
-	int i = vec;
-
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	if ((vec > 31) && (vec < 64)) {
-		irqa = irq_vecs1;
-		i = vec - 32;
-	} else if (vec > 63) {
-		irqa = irq_vecs2;
-		i = vec - 64;
-	}
-#endif /* CONFIG_440GX */
-	if (vec > 31) {
-		irqa = irq_vecs1;
-		i = vec - 32;
-	}
-#endif
+	int i;
 
-#if 0
-	printf ("Free interrupt for vector %d ==> %p\n",
-		vec, irq_vecs[vec].handler);
-#endif
+	debug("Free interrupt for vector %d ==> %p\n",
+	      vec, irq_vecs[vec].handler);
 
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	if ((vec > 31) && (vec < 64))
-		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
-	else if (vec > 63)
-		mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
-	else
-#endif /* CONFIG_440GX */
-	if (vec > 31)
-		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
-	else
+	i = vec & 0x1f;
+	if ((vec >= 0) && (vec < 32))
+		mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
+#if (UIC_MAX > 1)
+	else if ((vec >= 32) && (vec < 64))
+		mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
+#endif
+#if (UIC_MAX > 2)
+	else if ((vec >= 64) && (vec < 96))
+		mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i));
+#endif
+#if (UIC_MAX > 3)
+	else if (vec >= 96)
+		mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i));
 #endif
-		mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i));
 
-	irqa[i].handler = NULL;
-	irqa[i].arg = NULL;
+	irq_vecs[vec].handler = NULL;
+	irq_vecs[vec].arg = NULL;
 }
 
-/****************************************************************************/
-
 void timer_interrupt_cpu (struct pt_regs *regs)
 {
 	/* nothing to do here */
 	return;
 }
 
-/****************************************************************************/
-
 #if defined(CONFIG_CMD_IRQ)
-
-/*******************************************************************************
- *
- * irqinfo - print information about PCI devices
- *
- */
-int
-do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int vec;
 
-	printf ("\nInterrupt-Information:\n");
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-	printf ("\nUIC 0\n");
-#endif
+	printf ("Interrupt-Information:\n");
 	printf ("Nr  Routine   Arg       Count\n");
 
-	for (vec=0; vec<32; vec++) {
+	for (vec = 0; vec < (UIC_MAX * 32); vec++) {
 		if (irq_vecs[vec].handler != NULL) {
 			printf ("%02d  %08lx  %08lx  %d\n",
 				vec,

@@ -656,46 +389,6 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 	}
 
-#if defined(CONFIG_440) || defined(CONFIG_405EX)
-	printf ("\nUIC 1\n");
-	printf ("Nr  Routine   Arg       Count\n");
-
-	for (vec=0; vec<32; vec++) {
-		if (irq_vecs1[vec].handler != NULL)
-			printf ("%02d  %08lx  %08lx  %d\n",
-				vec+31, (ulong)irq_vecs1[vec].handler,
-				(ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
-	}
-	printf("\n");
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-	printf ("\nUIC 2\n");
-	printf ("Nr  Routine   Arg       Count\n");
-
-	for (vec=0; vec<32; vec++) {
-		if (irq_vecs2[vec].handler != NULL)
-			printf ("%02d  %08lx  %08lx  %d\n",
-				vec+63, (ulong)irq_vecs2[vec].handler,
-				(ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count);
-	}
-	printf("\n");
-#endif
-
-#if defined(CONFIG_440SPE)
-	printf ("\nUIC 3\n");
-	printf ("Nr  Routine   Arg       Count\n");
-
-	for (vec=0; vec<32; vec++) {
-		if (irq_vecs3[vec].handler != NULL)
-			printf ("%02d  %08lx  %08lx  %d\n",
-					vec+63, (ulong)irq_vecs3[vec].handler,
-					(ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count);
-	}
-	printf("\n");
-#endif
-
 	return 0;
 }
 #endif

index 3bafea3..9e722b9 100644
@@ -42,7 +42,8 @@
 #include <asm/mmu.h>
 
 #if defined(CONFIG_SPD_EEPROM) &&				\
-	(defined(CONFIG_440SP) || defined(CONFIG_440SPE))
+	(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+	 defined(CONFIG_460EX) || defined(CONFIG_460GT))
 
 /*-----------------------------------------------------------------------------+
  * Defines

@@ -579,6 +580,13 @@ long int initdram(int board_type)
 
 	ppc440sp_sdram_register_dump();
 
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
 	return dram_size;
 }
 

@@ -2125,6 +2133,7 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	unsigned long baseadd_size;
 	unsigned long i;
 	unsigned long bank_0_populated = 0;
+	unsigned long total_size = 0;
 
 	/*------------------------------------------------------------------
 	 * Reset the rank_base_address.

@@ -2147,28 +2156,38 @@ static void program_memory_queue(unsigned long *dimm_populated,
 			 * Set the sizes
 			 *-----------------------------------------------------------------*/
 			baseadd_size = 0;
-			rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
 			switch (rank_size_id) {
+			case 0x01:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
+				total_size = 1024;
+				break;
 			case 0x02:
-				baseadd_size |= SDRAM_RXBAS_SDSZ_8;
+				baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
+				total_size = 2048;
 				break;
 			case 0x04:
-				baseadd_size |= SDRAM_RXBAS_SDSZ_16;
+				baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
+				total_size = 4096;
 				break;
 			case 0x08:
 				baseadd_size |= SDRAM_RXBAS_SDSZ_32;
+				total_size = 32;
 				break;
 			case 0x10:
 				baseadd_size |= SDRAM_RXBAS_SDSZ_64;
+				total_size = 64;
 				break;
 			case 0x20:
 				baseadd_size |= SDRAM_RXBAS_SDSZ_128;
+				total_size = 128;
 				break;
 			case 0x40:
 				baseadd_size |= SDRAM_RXBAS_SDSZ_256;
+				total_size = 256;
 				break;
 			case 0x80:
 				baseadd_size |= SDRAM_RXBAS_SDSZ_512;
+				total_size = 512;
 				break;
 			default:
 				printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",

@@ -2178,6 +2197,7 @@ static void program_memory_queue(unsigned long *dimm_populated,
 				printf("Replace the DIMM module with a supported DIMM.\n\n");
 				spd_ddr_init_hang ();
 			}
+			rank_size_bytes = total_size << 20;
 
 			if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
 				bank_0_populated = 1;

@@ -2190,6 +2210,19 @@ static void program_memory_queue(unsigned long *dimm_populated,
 			}
 		}
 	}
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	/*
+	 * Enable high bandwidth access on 460EX/GT.
+	 * This should/could probably be done on other
+	 * PPC's too, like 440SPe.
+	 * This is currently not used, but with this setup
+	 * it is possible to use it later on in e.g. the Linux
+	 * EMAC driver for performance gain.
+	 */
+	mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
+	mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
+#endif
 }
 
 /*-----------------------------------------------------------------------------+

589 lines not on this page · raw message

index a5b9690..941d4dc 100644
@@ -531,7 +531,8 @@ int pci_440_init (struct pci_controller *hose)
 	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
 	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
 #elif defined(PCIX0_BRDGOPT1)

@@ -549,7 +550,8 @@ int pci_440_init (struct pci_controller *hose)
 	out32r( PCIX0_POM0SA, 0 ); /* disable */
 	out32r( PCIX0_POM1SA, 0 ); /* disable */
 	out32r( PCIX0_POM2SA, 0 ); /* disable */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	out32r( PCIX0_POM0LAL, 0x10000000 );
 	out32r( PCIX0_POM0LAH, 0x0000000c );
 #else

@@ -586,7 +588,8 @@ void pci_init_board(void)
 	int busno;
 
 	busno = pci_440_init (&ppc440_hose);
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	pcie_setup_hoses(busno + 1);
 #endif
 }

260 lines not on this page · raw message

index 3d1124e..ffbc222 100644
@@ -64,16 +64,22 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_440)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
-#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define UART0_BASE	(CFG_PERIPHERAL_BASE + 0x00000300)
+#define UART1_BASE	(CFG_PERIPHERAL_BASE + 0x00000400)
 #else
-#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
-#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#define UART0_BASE	(CFG_PERIPHERAL_BASE + 0x00000200)
+#define UART1_BASE	(CFG_PERIPHERAL_BASE + 0x00000300)
 #endif
 
 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
+#define UART2_BASE	(CFG_PERIPHERAL_BASE + 0x00000600)
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define UART2_BASE	(CFG_PERIPHERAL_BASE + 0x00000500)
+#define UART3_BASE	(CFG_PERIPHERAL_BASE + 0x00000600)
 #endif
 
 #if defined(CONFIG_440GP)

@@ -94,11 +100,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART1_SDR	sdr_uart1
 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
     defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPe)
+    defined(CONFIG_440SP) || defined(CONFIG_440SPe) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define UART2_SDR	sdr_uart2
 #endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
-    defined(CONFIG_440GR) || defined(CONFIG_440GRx)
+    defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define UART3_SDR	sdr_uart3
 #endif
 #define MFREG(a, d)	mfsdr(a, d)

index 9e9c685..54cc256 100644
@@ -54,7 +54,8 @@ static int pci_async_enabled(void)
 #endif
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
 	mfsdr(sdr_sdstp1, val);

@@ -86,7 +87,8 @@ static int pci_arbiter_enabled(void)
 	return (val & 0x80000000);
 #endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
 	mfsdr(sdr_pci0, val);

@@ -167,6 +169,21 @@ static char *bootstrap_str[] = {
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"EBC (16 bits)",
+	"PCI",
+	"PCI",
+	"EBC (16 bits)",
+	"NAND (8 bits)",
+	"I2C (Addr 0x54)",	/* A8 */
+	"I2C (Addr 0x52)",	/* A4 */
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
+#endif
+
 #if defined(CONFIG_405EZ)
 #define SDR0_PINSTP_SHIFT	28
 static char *bootstrap_str[] = {

@@ -257,8 +274,12 @@ int checkcpu (void)
 	puts("05");
 #endif
 #if defined(CONFIG_440)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	puts("60");
+#else
 	puts("40");
 #endif
+#endif
 
 	switch (pvr) {
 	case PVR_405GP_RB:

@@ -448,6 +469,26 @@ int checkcpu (void)
 		strcpy(addstr, "No RAID 6 support");
 		break;
 
+	case PVR_460EX_RA:
+		puts("EX Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
+		break;
+
+	case PVR_460EX_SE_RA:
+		puts("EX Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
+		break;
+
+	case PVR_460GT_RA:
+		puts("GT Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
+		break;
+
+	case PVR_460GT_SE_RA:
+		puts("GT Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
+		break;
+
 	default:
 		printf (" UNKNOWN (PVR=%08x)", pvr);
 		break;

index 2e0dd6f..5d15e2f 100644
@@ -302,5 +302,6 @@ int cpu_init_r (void)
 	}
 #endif  /* defined(CONFIG_405GP) */
 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
+
 	return (0);
 }

index 9e2229d..5b2ae88 100644
@@ -34,7 +34,8 @@
 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
 	(defined(CONFIG_440EP) || defined(CONFIG_440GR) ||	     \
 	 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	     \
-	 defined(CONFIG_405EZ) || defined(CONFIG_405EX))
+	 defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||	     \
+	 defined(CONFIG_460EX) || defined(CONFIG_460GT))
 
 #include <nand.h>
 #include <linux/mtd/ndfc.h>

141 lines not on this page · raw message

index 7ea4eb1..1415cbe 100644
@@ -94,6 +94,7 @@
       /* Mal IER		      */
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 #define MAL_IER_PT	  0x00000080
 #define MAL_IER_PRE	  0x00000040

index 7c79bd1..2df4fbd 100644
@@ -41,7 +41,8 @@
 #endif /* CONFIG_I2C_MULTI_BUS */
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define I2C_BASE_ADDR	(CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
 /* all remaining 440 variants */

99 lines not on this page · raw message

87 lines not on this page · raw message

index 86c5df2..b7a5b28 100644
@@ -802,6 +802,10 @@
 #define PVR_440SPe_RA	0x53521890 /* 440SPe rev A without RAID 6 support	*/
 #define PVR_440SPe_6_RB	0x53421891 /* 440SPe rev B with RAID 6 support enabled	*/
 #define PVR_440SPe_RB	0x53521891 /* 440SPe rev B without RAID 6 support	*/
+#define PVR_460EX_SE_RA	0x130218A2 /* 460EX rev A with Security Engine    */
+#define PVR_460EX_RA	0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460GT_SE_RA	0x130218A0 /* 460GT rev A with Security Engine    */
+#define PVR_460GT_RA	0x130218A1 /* 460GT rev A without Security Engine */
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000

index 2b31814..786ba03 100644
@@ -115,7 +115,8 @@ typedef struct bd_info {
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
     defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
 	int		bi_iic_fast[2];		/* Use fast i2c mode */
 #endif

@@ -123,7 +124,8 @@ typedef struct bd_info {
 	unsigned char	bi_sernum[8];
 #endif
 #if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	int 		bi_phynum[4];           /* Determines phy mapping */
 	int 		bi_phymode[4];          /* Determines phy mode */
 #elif defined(CONFIG_405EP) || defined(CONFIG_440)

index cd8aad0..673afdd 100644
@@ -273,7 +273,9 @@ void	pciinfo	      (int, int);
 	void	pci_master_init	     (struct pci_controller *);
 #   endif
     int	    is_pci_host		(struct pci_controller *);
-#if defined(CONFIG_440SPE) || defined(CONFIG_405EX)
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
    void pcie_setup_hoses(int busno);
 #endif
 #endif

index cbfe89e..37b121c 100644
@@ -118,7 +118,17 @@
 /******************************************************************************
  * Universal interrupt controller
  ******************************************************************************/
+#define UIC_SR	0x0			/* UIC status			   */
+#define UIC_ER	0x2			/* UIC enable			   */
+#define UIC_CR	0x3			/* UIC critical			   */
+#define UIC_PR	0x4			/* UIC polarity			   */
+#define UIC_TR	0x5			/* UIC triggering		   */
+#define UIC_MSR 0x6			/* UIC masked status		   */
+#define UIC_VR	0x7			/* UIC vector			   */
+#define UIC_VCR 0x8			/* UIC vector configuration	   */
+
 #define UIC_DCR_BASE 0xc0
+#define UIC0_DCR_BASE UIC_DCR_BASE
 #define uicsr        (UIC_DCR_BASE+0x0)  /* UIC status                       */
 #define uicsrs       (UIC_DCR_BASE+0x1)  /* UIC status set                   */
 #define uicer        (UIC_DCR_BASE+0x2)  /* UIC enable                       */

@@ -141,6 +151,7 @@
 #define uic0vcr       uicvcr		/* UIC vector configuration*/
 
 #define UIC_DCR_BASE1 0xd0
+#define UIC1_DCR_BASE 0xd0
 #define uic1sr        (UIC_DCR_BASE1+0x0)  /* UIC status            */
 #define uic1srs       (UIC_DCR_BASE1+0x1)  /* UIC status set        */
 #define uic1er        (UIC_DCR_BASE1+0x2)  /* UIC enable            */

@@ -152,6 +163,7 @@
 #define uic1vcr       (UIC_DCR_BASE1+0x8)  /* UIC vector configuration*/
 
 #define UIC_DCR_BASE2 0xe0
+#define UIC2_DCR_BASE 0xe0
 #define uic2sr        (UIC_DCR_BASE2+0x0)  /* UIC status            */
 #define uic2srs       (UIC_DCR_BASE2+0x1)  /* UIC status set        */
 #define uic2er        (UIC_DCR_BASE2+0x2)  /* UIC enable            */

@@ -237,10 +249,13 @@
 #define UIC_ENET1		0x00000040      /* */
 #define UIC_PCIEMSI2		0x00000020      /* */
 #define UIC_EIRQ4		0x00000010      /**/
-#define UIC_UIC2NC		0x00000008      /* */
-#define UIC_UIC2C		0x00000004      /* */
-#define UIC_UIC1NC		0x00000002      /* */
-#define UIC_UIC1C		0x00000001      /* */
+#define UICB0_UIC2NCI		0x00000008      /* */
+#define UICB0_UIC2CI		0x00000004      /* */
+#define UICB0_UIC1NCI		0x00000002      /* */
+#define UICB0_UIC1CI		0x00000001      /* */
+
+#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
+				 UICB0_UIC1CI | UICB0_UIC2NCI)
 
 #define UIC_MAL_TXEOB 		UIC_MTE/* MAL TXEOB                          */
 #define UIC_MAL_RXEOB 		UIC_MRE/* MAL RXEOB                          */

index 317604a..0208454 100644
@@ -131,7 +131,7 @@ typedef struct emac_4xx_hw_st {
 } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
 
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
 #define EMAC_NUM_DEV		4
 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) &&	\
 	defined(CONFIG_NET_MULTI) &&			\

@@ -155,7 +155,8 @@ typedef struct emac_4xx_hw_st {
 
 /* ZMII Bridge Register addresses */
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0D00)
 #else
 #define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0780)

@@ -164,9 +165,6 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_SSR		(ZMII_BASE + 4)
 #define ZMII_SMIISR		(ZMII_BASE + 8)
 
-#define ZMII_RMII		0x22000000
-#define ZMII_MDI0		0x80000000
-
 /* ZMII FER Register Bit Definitions */
 #define ZMII_FER_DIS		(0x0)
 #define ZMII_FER_MDI		(0x8)

@@ -205,6 +203,8 @@ typedef struct emac_4xx_hw_st {
 /* RGMII Register Addresses */
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1000)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1500)
 #elif defined(CONFIG_405EX)
 #define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0xB00)
 #else

@@ -223,19 +223,21 @@ typedef struct emac_4xx_hw_st {
 
 #define RGMII_FER_V(__x)	((__x - 2) * 4)
 
+#define RGMII_FER_MDIO(__x)	(1 << (19 - (__x)))
+
 /* RGMII Speed Selection Register Bit Definitions */
 #define RGMII_SSR_SP_10MBPS	(0x00)
 #define RGMII_SSR_SP_100MBPS	(0x02)
 #define RGMII_SSR_SP_1000MBPS	(0x04)
 
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 #define RGMII_SSR_V(__x)	((__x) * 8)
 #else
 #define RGMII_SSR_V(__x)	((__x -2) * 8)
 #endif
 
-
 /*---------------------------------------------------------------------------+
 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 +---------------------------------------------------------------------------*/

@@ -304,7 +306,8 @@ typedef struct emac_4xx_hw_st {
 /* Ethernet MAC Regsiter Addresses */
 #if defined(CONFIG_440)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0E00)
 #else
 #define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0800)

@@ -345,6 +348,7 @@ typedef struct emac_4xx_hw_st {
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 /* MODE Reg 1 */
 #define EMAC_M1_FDE		(0x80000000)

index 907744b..cf29fe7 100644
@@ -380,7 +380,8 @@
 #define SDR0_PEGPLLSTS		0x000003A2	/* PE Pll LC Tank Status */
 #endif /* CONFIG_440SPE */
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 /*----------------------------------------------------------------------------+
 | SDRAM Controller
 +----------------------------------------------------------------------------*/

@@ -416,7 +417,8 @@
 /*-----------------------------------------------------------------------------+
 |  Memory Bank 0-7 configuration
 +-----------------------------------------------------------------------------*/
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
 #define SDRAM_RXBAS_SDBA_ENCODE(n)	((((unsigned long)(n))&0xFFE00000)>>2)
 #define SDRAM_RXBAS_SDBA_DECODE(n)	((((unsigned long)(n))&0xFFE00000)<<2)

@@ -692,6 +694,7 @@
 #define SDRAM_CLKTR_CLKP_0_DEG		0x00000000
 #define SDRAM_CLKTR_CLKP_180_DEG_ADV	0x80000000
 #define SDRAM_CLKTR_CLKP_90_DEG_ADV	0x40000000
+#define SDRAM_CLKTR_CLKP_270_DEG_ADV	0xC0000000
 
 /*-----------------------------------------------------------------------------+
 |  SDRAM Write Timing Register

@@ -1577,49 +1580,6 @@
 
 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
 
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0                   0x4000
-#define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
-#define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
-#define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
-#define   SDR0_CUST0_MUX_GPIO_SEL     0xC0000000       /* GPIO Selection */
-
-#define   SDR0_CUST0_NDFC_EN_MASK     0x20000000     /* NDFC Enable Mask */
-#define   SDR0_CUST0_NDFC_ENABLE      0x20000000       /* NDFC Enable */
-#define   SDR0_CUST0_NDFC_DISABLE     0x00000000       /* NDFC Disable */
-
-#define   SDR0_CUST0_NDFC_BW_MASK     0x10000000     /* NDFC Boot Width */
-#define   SDR0_CUST0_NDFC_BW_16_BIT   0x10000000       /* NDFC Boot Width = 16 Bit */
-#define   SDR0_CUST0_NDFC_BW_8_BIT    0x00000000       /* NDFC Boot Width =  8 Bit */
-
-#define   SDR0_CUST0_NDFC_BP_MASK     0x0F000000     /* NDFC Boot Page */
-#define   SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define   SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
-
-#define   SDR0_CUST0_NDFC_BAC_MASK    0x00C00000     /* NDFC Boot Address Cycle */
-#define   SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
-#define   SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
-
-#define   SDR0_CUST0_NDFC_ARE_MASK    0x00200000     /* NDFC Auto Read Enable */
-#define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
-#define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
-
-#define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
-#define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
-#define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
-
-#define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
-#define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
-#define   SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
-
-#define   SDR0_CUST0_CHIPSELGAT_MASK  0x0000000F     /* Chip Select Gating Mask */
-#define   SDR0_CUST0_CHIPSELGAT_DIS   0x00000000       /* Chip Select Gating Disable */
-#define   SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F       /* All Chip Select Gating Enable */
-#define   SDR0_CUST0_CHIPSELGAT_EN0   0x00000008       /* Chip Select0 Gating Enable */
-#define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
-#define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
-#define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
-
 /* CUST1 Customer Configuration Register1 */
 #define   SDR0_CUST1                 0x4002
 #define   SDR0_CUST1_NDRSC_MASK       0xFFFF0000     /* NDRSC Device Read Count */

@@ -1666,25 +1626,34 @@
 #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
 #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
 
+#endif /* 440EP || 440GR || 440EPX || 440GRX */
+
 /*-----------------------------------------------------------------------------
- | Internal SRAM
+ | L2 Cache
  +----------------------------------------------------------------------------*/
-#define ISRAM0_DCR_BASE 0x380
-#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
-#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
-#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
-#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
-#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
-#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
-#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
-#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
+#if defined (CONFIG_440GX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define L2_CACHE_BASE	0x030
+#define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
+#define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
+#define l2_cache_addr	(L2_CACHE_BASE+0x02)	/* L2 Cache Address	*/
+#define l2_cache_data	(L2_CACHE_BASE+0x03)	/* L2 Cache Data	*/
+#define l2_cache_stat	(L2_CACHE_BASE+0x04)	/* L2 Cache Status	*/
+#define l2_cache_cver	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
+#define l2_cache_snp0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
+#define l2_cache_snp1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
 
-#else
+#endif /* CONFIG_440GX */
 
 /*-----------------------------------------------------------------------------
  | Internal SRAM
  +----------------------------------------------------------------------------*/
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define ISRAM0_DCR_BASE 0x380
+#else
 #define ISRAM0_DCR_BASE 0x020
+#endif
 #define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
 #define isram0_sb1cr	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
 #define isram0_sb2cr	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/

@@ -1697,22 +1666,52 @@
 #define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
 #define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
-/*-----------------------------------------------------------------------------
- | L2 Cache
- +----------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define L2_CACHE_BASE	0x030
-#define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
-#define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
-#define l2_cache_addr	(L2_CACHE_BASE+0x02)	/* L2 Cache Address	*/
-#define l2_cache_data	(L2_CACHE_BASE+0x03)	/* L2 Cache Data	*/
-#define l2_cache_stat	(L2_CACHE_BASE+0x04)	/* L2 Cache Status	*/
-#define l2_cache_cver	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
-#define l2_cache_snp0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
-#define l2_cache_snp1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0                   0x4000
+#define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
+#define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
+#define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
+#define   SDR0_CUST0_MUX_GPIO_SEL     0xC0000000       /* GPIO Selection */
 
-#endif /* CONFIG_440GX */
-#endif /* !CONFIG_440EP !CONFIG_440GR*/
+#define   SDR0_CUST0_NDFC_EN_MASK     0x20000000     /* NDFC Enable Mask */
+#define   SDR0_CUST0_NDFC_ENABLE      0x20000000       /* NDFC Enable */
+#define   SDR0_CUST0_NDFC_DISABLE     0x00000000       /* NDFC Disable */
+
+#define   SDR0_CUST0_NDFC_BW_MASK     0x10000000     /* NDFC Boot Width */
+#define   SDR0_CUST0_NDFC_BW_16_BIT   0x10000000       /* NDFC Boot Width = 16 Bit */
+#define   SDR0_CUST0_NDFC_BW_8_BIT    0x00000000       /* NDFC Boot Width =  8 Bit */
+
+#define   SDR0_CUST0_NDFC_BP_MASK     0x0F000000     /* NDFC Boot Page */
+#define   SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define   SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+
+#define   SDR0_CUST0_NDFC_BAC_MASK    0x00C00000     /* NDFC Boot Address Cycle */
+#define   SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
+#define   SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+
+#define   SDR0_CUST0_NDFC_ARE_MASK    0x00200000     /* NDFC Auto Read Enable */
+#define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
+#define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
+
+#define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
+#define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
+#define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
+
+#define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
+#define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
+#define   SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
+
+#define   SDR0_CUST0_CHIPSELGAT_MASK  0x0000000F     /* Chip Select Gating Mask */
+#define   SDR0_CUST0_CHIPSELGAT_DIS   0x00000000       /* Chip Select Gating Disable */
+#define   SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F       /* All Chip Select Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN0   0x00000008       /* Chip Select0 Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
+#endif
 
 /*-----------------------------------------------------------------------------
  | On-Chip Buses

@@ -1722,8 +1721,14 @@
 /*-----------------------------------------------------------------------------
  | Clocking, Power Management and Chip Control
  +----------------------------------------------------------------------------*/
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CNTRL_DCR_BASE 0x160
+#else
 #define CNTRL_DCR_BASE 0x0b0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#endif
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define cpc0_er		(CNTRL_DCR_BASE+0x00)	/* CPM enable register		*/
 #define cpc0_fr		(CNTRL_DCR_BASE+0x01)	/* CPM force register		*/
 #define cpc0_sr		(CNTRL_DCR_BASE+0x02)	/* CPM status register		*/

@@ -1751,6 +1756,15 @@
 /*-----------------------------------------------------------------------------
  | Universal interrupt controller
  +----------------------------------------------------------------------------*/
+#define UIC_SR	0x0			/* UIC status			   */
+#define UIC_ER	0x2			/* UIC enable			   */
+#define UIC_CR	0x3			/* UIC critical			   */
+#define UIC_PR	0x4			/* UIC polarity			   */
+#define UIC_TR	0x5			/* UIC triggering		   */
+#define UIC_MSR 0x6			/* UIC masked status		   */
+#define UIC_VR	0x7			/* UIC vector			   */
+#define UIC_VCR 0x8			/* UIC vector configuration	   */
+
 #define UIC0_DCR_BASE 0xc0
 #define uic0sr	(UIC0_DCR_BASE+0x0)   /* UIC0 status			   */
 #define uic0er	(UIC0_DCR_BASE+0x2)   /* UIC0 enable			   */

@@ -1771,7 +1785,9 @@
 #define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
 #define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
 
-#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define UIC2_DCR_BASE 0xe0
 #define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
 #define uic2srs	(UIC2_DCR_BASE+0x1)   /* UIC2 status-Read Set */

@@ -1927,7 +1943,11 @@
 /*-----------------------------------------------------------------------------
  | DMA
  +----------------------------------------------------------------------------*/
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define DMA_DCR_BASE 0x200
+#else
 #define DMA_DCR_BASE 0x100
+#endif
 #define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
 #define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
 #define dmasah0 (DMA_DCR_BASE+0x02)  /* DMA source address high 0	     */

@@ -1991,15 +2011,16 @@
 #define maltxctp3r  (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg   */
 #define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
 #define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
-#if defined(CONFIG_440GX)
-#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
-#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
-#endif /* CONFIG_440GX */
 #define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
 #define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
+#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
+#define malrxctp8r  (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg   */
 #define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
 #define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
+#define malrcbs8    (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg	    */
 #endif /* CONFIG_440GX */
 
 

@@ -2112,6 +2133,41 @@
 #define UIC_MAL_TXEOB	UIC_MTE
 #define UIC_MAL_RXEOB	UIC_MRE
 
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+#define UIC_RSVD0	0x80000000	/* N/A - unused			    */
+#define UIC_U1		0x40000000	/* UART 1			    */
+#define UIC_IIC0	0x20000000	/* IIC				    */
+#define UIC_IIC1	0x10000000	/* IIC				    */
+#define UIC_PIM		0x08000000	/* PCI inbound message		    */
+#define UIC_PCRW	0x04000000	/* PCI command register write	    */
+#define UIC_PPM		0x02000000	/* PCI power management		    */
+#define UIC_PCIVPD	0x01000000	/* PCI VPD			    */
+#define UIC_MSI0	0x00800000	/* PCI MSI level 0		    */
+#define UIC_EIR0	0x00400000	/* External interrupt 0		    */
+#define UIC_UIC2NC	0x00200000	/* UIC2 non-critical interrupt	    */
+#define UIC_UIC2C	0x00100000	/* UIC2 critical interrupt	    */
+#define UIC_D0		0x00080000	/* DMA channel 0		    */
+#define UIC_D1		0x00040000	/* DMA channel 1		    */
+#define UIC_D2		0x00020000	/* DMA channel 2		    */
+#define UIC_D3		0x00010000	/* DMA channel 3		    */
+#define UIC_UIC3NC	0x00008000	/* UIC3 non-critical interrupt	    */
+#define UIC_UIC3C	0x00004000	/* UIC3 critical interrupt	    */
+#define UIC_EIR1	0x00002000	/* External interrupt 1		    */
+#define UIC_TRNGDA	0x00001000	/* TRNG data available 		    */
+#define UIC_PKAR1	0x00000800	/* PKA ready (PKA[1])		    */
+#define UIC_D1CPFF	0x00000400	/* DMA1 cp fifo full		    */
+#define UIC_D1CSNS	0x00000200	/* DMA1 cs fifo needs service	    */
+#define UIC_I2OID	0x00000100	/* I2O inbound door bell	    */
+#define UIC_I2OLNE	0x00000080	/* I2O Inbound Post List FIFO Not Empty */
+#define UIC_I20R0LL	0x00000040	/* I2O Region 0 Low Latency PLB Write */
+#define UIC_I2OR1LL	0x00000020	/* I2O Region 1 Low Latency PLB Write */
+#define UIC_I20R0HB	0x00000010	/* I2O Region 0 High Bandwidth PLB Write */
+#define UIC_I2OR1HB	0x00000008	/* I2O Region 1 High Bandwidth PLB Write */
+#define UIC_EIP94	0x00000004	/* Security EIP94		    */
+#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
+#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
+
 #elif !defined(CONFIG_440SPE)
 #define UIC_U0		0x80000000	/* UART 0			    */
 #define UIC_U1		0x40000000	/* UART 1			    */

@@ -2221,6 +2277,41 @@
 #define UIC_ETH1	0x00000002	/* Ethernet 1			    */
 #define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
 
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+#define UIC_EIR2	0x80000000	/* External interrupt 2		    */
+#define UIC_U0		0x40000000	/* UART 0			    */
+#define UIC_SPI		0x20000000	/* SPI				    */
+#define UIC_TRNGAL	0x10000000	/* TRNG alarm			    */
+#define UIC_DEUE	0x08000000	/* DDR SDRAM ECC correct/uncorrectable error */
+#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
+#define UIC_NDFC	0x02000000	/* NDFC				    */
+#define UIC_EIPPKPSE	0x01000000	/* EIPPKP slave error		    */
+#define UIC_P0MSI1	0x00800000	/* PCI0 MSI level 1		    */
+#define UIC_P0MSI2	0x00400000	/* PCI0 MSI level 2		    */
+#define UIC_P0MSI3	0x00200000	/* PCI0 MSI level 3		    */
+#define UIC_L2C		0x00100000	/* L2 cache			    */
+#define UIC_CT0		0x00080000	/* GPT compare timer 0		    */
+#define UIC_CT1		0x00040000	/* GPT compare timer 1		    */
+#define UIC_CT2		0x00020000	/* GPT compare timer 2		    */
+#define UIC_CT3		0x00010000	/* GPT compare timer 3		    */
+#define UIC_CT4		0x00008000	/* GPT compare timer 4		    */
+#define UIC_CT5		0x00004000	/* GPT compare timer 5		    */
+#define UIC_CT6		0x00002000	/* GPT compare timer 6		    */
+#define UIC_GPTDC	0x00001000	/* GPT decrementer pulse	    */
+#define UIC_EIR3	0x00000800	/* External interrupt 3		    */
+#define UIC_EIR4	0x00000400	/* External interrupt 4		    */
+#define UIC_DMAE	0x00000200	/* DMA error			    */
+#define UIC_I2OE	0x00000100	/* I2O error			    */
+#define UIC_SRE		0x00000080	/* Serial ROM error		    */
+#define UIC_P0AE	0x00000040	/* PCI0 asynchronous error	    */
+#define UIC_EIR5	0x00000020	/* External interrupt 5		    */
+#define UIC_EIR6	0x00000010	/* External interrupt 6		    */
+#define UIC_U2		0x00000008	/* UART 2			    */
+#define UIC_U3		0x00000004	/* UART 3			    */
+#define UIC_EIR7	0x00000002	/* External interrupt 7		    */
+#define UIC_EIR8	0x00000001	/* External interrupt 8		    */
+
 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 #define UIC_MS        0x80000000  /* MAL SERR                           */

@@ -2340,6 +2431,41 @@
 #define UIC_RSVD30	0x00000002	/* Reserved			    */
 #define UIC_RSVD31	0x00000001	/* Reserved			    */
 
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+#define UIC_TAH0	0x80000000	/* TAHOE 0			    */
+#define UIC_TAH1	0x40000000	/* TAHOE 1			    */
+#define UIC_EIR9	0x20000000	/* External interrupt 9		    */
+#define UIC_MS		0x10000000	/* MAL SERR			    */
+#define UIC_MTDE	0x08000000	/* MAL TXDE			    */
+#define UIC_MRDE	0x04000000	/* MAL RXDE			    */
+#define UIC_MTE		0x02000000	/* MAL TXEOB			    */
+#define UIC_MRE		0x01000000	/* MAL RXEOB			    */
+#define UIC_MCTX0	0x00800000	/* MAL interrupt coalescence TX0    */
+#define UIC_MCTX1	0x00400000	/* MAL interrupt coalescence TX1    */
+#define UIC_MCTX2	0x00200000	/* MAL interrupt coalescence TX2    */
+#define UIC_MCTX3	0x00100000	/* MAL interrupt coalescence TX3    */
+#define UIC_MCTR0	0x00080000	/* MAL interrupt coalescence TR0    */
+#define UIC_MCTR1	0x00040000	/* MAL interrupt coalescence TR1    */
+#define UIC_MCTR2	0x00020000	/* MAL interrupt coalescence TR2    */
+#define UIC_MCTR3	0x00010000	/* MAL interrupt coalescence TR3    */
+#define UIC_ETH0	0x00008000	/* Ethernet 0			    */
+#define UIC_ETH1	0x00004000	/* Ethernet 1			    */
+#define UIC_ETH2	0x00002000	/* Ethernet 2			    */
+#define UIC_ETH3	0x00001000	/* Ethernet 3			    */
+#define UIC_EWU0	0x00000800	/* Ethernet 0 wakeup		    */
+#define UIC_EWU1	0x00000400	/* Ethernet 1 wakeup		    */
+#define UIC_EWU2	0x00000200	/* Ethernet 2 wakeup		    */
+#define UIC_EWU3	0x00000100	/* Ethernet 3 wakeup		    */
+#define UIC_EIR10	0x00000080	/* External interrupt 10	    */
+#define UIC_EIR11	0x00000040	/* External interrupt 11	    */
+#define UIC_RSVD2	0x00000020	/* Reserved			    */
+#define UIC_PLB4XAHB	0x00000010	/* PLB4XAHB / AHBARB error	    */
+#define UIC_OTG		0x00000008	/* USB2.0 OTG			    */
+#define UIC_EHCI	0x00000004	/* USB2.0 Host EHCI		    */
+#define UIC_OHCI	0x00000002	/* USB2.0 Host OHCI		    */
+#define UIC_OHCISMI	0x00000001	/* USB2.0 Host OHCI SMI		    */
+
 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
 
 #define UIC_EIR5    0x80000000  /* External interrupt 5                 */

@@ -2366,18 +2492,38 @@
 #define UICB0_UIC2CI	0x08000000	/* UIC2 Critical Interrupt	    */
 #define UICB0_UIC2NCI	0x04000000	/* UIC2 Noncritical Interrupt	    */
 
-#define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
-						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+#define UICB0_ALL	(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
+			 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+#define UICB0_UIC1NCI	0x00000002	/* UIC1 Noncritical Interrupt	    */
+#define UICB0_UIC1CI	0x00000001	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC2NCI	0x00200000	/* UIC2 Noncritical Interrupt	    */
+#define UICB0_UIC2CI	0x00100000	/* UIC2 Critical Interrupt	    */
+#define UICB0_UIC3NCI	0x00008000	/* UIC3 Noncritical Interrupt	    */
+#define UICB0_UIC3CI	0x00004000	/* UIC3 Critical Interrupt	    */
+
+#define UICB0_ALL	(UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
+			 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
 
 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
-#define UICB0_UIC1CI	0x00000000	/* UIC1 Critical Interrupt	    */
-#define UICB0_UIC1NCI	0x00000000	/* UIC1 Noncritical Interrupt	    */
-#define UICB0_UIC2CI	0x00000000	/* UIC2 Critical Interrupt	    */
-#define UICB0_UIC2NCI	0x00000000	/* UIC2 Noncritical Interrupt	    */
+#define UICB0_UIC1CI	0x00000001	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC1NCI	0x00000002	/* UIC1 Noncritical Interrupt	    */
+#define UICB0_UIC2CI	0x00000004	/* UIC2 Critical Interrupt	    */
+#define UICB0_UIC2NCI	0x00000008	/* UIC2 Noncritical Interrupt	    */
+
+#define UICB0_ALL	(UICB0_UIC1CI | UICB0_UIC1NCI | \
+			 UICB0_UIC1CI | UICB0_UIC2NCI)
 
-#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
-						 UICB0_UIC1CI | UICB0_UIC2NCI)
+#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#define UICB0_UIC1CI	0x00000001	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC1NCI	0x00000002	/* UIC1 Noncritical Interrupt	    */
+
+#define UICB0_ALL	(UICB0_UIC1CI | UICB0_UIC1NCI)
 
 #endif /* CONFIG_440GX */
 /*---------------------------------------------------------------------------+

@@ -3018,6 +3164,198 @@
 #define SDR0_MFR			0x4300
 #endif	/* CONFIG_440SPE	*/
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+/* Pin Function Control Register 0 (SDR0_PFC0) */
+#define SDR0_PFC0		0x4100
+#define SDR0_PFC0_DBG		0x00008000	/* debug enable */
+#define SDR0_PFC0_G49E		0x00004000	/* GPIO 49 enable */
+#define SDR0_PFC0_G50E		0x00002000	/* GPIO 50 enable */
+#define SDR0_PFC0_G51E		0x00001000	/* GPIO 51 enable */
+#define SDR0_PFC0_G52E		0x00000800	/* GPIO 52 enable */
+#define SDR0_PFC0_G53E		0x00000400	/* GPIO 53 enable */
+#define SDR0_PFC0_G54E		0x00000200	/* GPIO 54 enable */
+#define SDR0_PFC0_G55E		0x00000100	/* GPIO 55 enable */
+#define SDR0_PFC0_G56E		0x00000080	/* GPIO 56 enable */
+#define SDR0_PFC0_G57E		0x00000040	/* GPIO 57 enable */
+#define SDR0_PFC0_G58E		0x00000020	/* GPIO 58 enable */
+#define SDR0_PFC0_G59E		0x00000010	/* GPIO 59 enable */
+#define SDR0_PFC0_G60E		0x00000008	/* GPIO 60 enable */
+#define SDR0_PFC0_G61E		0x00000004	/* GPIO 61 enable */
+#define SDR0_PFC0_G62E		0x00000002	/* GPIO 62 enable */
+#define SDR0_PFC0_G63E		0x00000001	/* GPIO 63 enable */
+
+/* Pin Function Control Register 1 (SDR0_PFC1) */
+#define SDR0_PFC1		0x4101
+#define SDR0_PFC1_U1ME_MASK	0x02000000	/* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR	0x00000000	/* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS	0x02000000	/* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK	0x00080000	/* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR	0x00000000	/* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS	0x00080000	/* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK	0x00040000	/* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS	0x00000000	/* UART0 Interface Mode 8 pins*/
+#define SDR0_PFC1_U0IM_4PINS	0x00040000	/* UART0 Interface Mode 4 pins*/
+#define SDR0_PFC1_SIS_MASK	0x00020000	/* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL	0x00000000	/* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL	0x00020000	/* IIC1 Selected */
+
+/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
+#define SDR0_ETH_PLL		0x4102
+#define SDR0_ETH_PLL_PLLLOCK	 0x80000000	/*Ethernet PLL lock indication*/
+#define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000	/* Ethernet reference clock */
+#define SDR0_ETH_PLL_BYPASS	 0x08000000	/* bypass mode enable */
+#define SDR0_ETH_PLL_STOPCLK	 0x04000000	/* output clock disable */
+#define SDR0_ETH_PLL_TUNE_MASK	 0x03FF0000	/* loop stability tuning bits */
+#define SDR0_ETH_PLL_TUNE_ENCODE(n)	((((unsigned long)(n))&0x3ff)<<16)
+#define SDR0_ETH_PLL_MULTI_MASK	 0x0000FF00	/* frequency multiplication */
+#define SDR0_ETH_PLL_MULTI_ENCODE(n)	((((unsigned long)(n))&0xff)<<8)
+#define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0	/* PLLOUTB/C frequency */
+#define SDR0_ETH_PLL_RANGEB_ENCODE(n)	((((unsigned long)(n))&0x0f)<<4)
+#define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F	/* PLLOUTA frequency */
+#define SDR0_ETH_PLL_RANGEA_ENCODE(n)	(((unsigned long)(n))&0x0f)
+
+/* Ethernet Configuration Register (SDR0_ETH_CFG) */
+#define SDR0_ETH_CFG		0x4103
+#define SDR0_ETH_CFG_SGMII3_LPBK	0x00800000	/* SGMII3 port loopback enable */
+#define SDR0_ETH_CFG_SGMII2_LPBK	0x00400000	/* SGMII2 port loopback enable */
+#define SDR0_ETH_CFG_SGMII1_LPBK	0x00200000	/* SGMII1 port loopback enable */
+#define SDR0_ETH_CFG_SGMII0_LPBK	0x00100000	/* SGMII0 port loopback enable */
+#define SDR0_ETH_CFG_SGMII_MASK		0x00070000	/* SGMII Mask */
+#define SDR0_ETH_CFG_SGMII2_ENABLE	0x00040000	/* SGMII2 port enable */
+#define SDR0_ETH_CFG_SGMII1_ENABLE	0x00020000	/* SGMII1 port enable */
+#define SDR0_ETH_CFG_SGMII0_ENABLE	0x00010000	/* SGMII0 port enable */
+#define SDR0_ETH_CFG_TAHOE1_BYPASS	0x00002000	/* TAHOE1 Bypass selector */
+#define SDR0_ETH_CFG_TAHOE0_BYPASS	0x00001000	/* TAHOE0 Bypass selector */
+#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL	0x00000800	/* EMAC 3 PHY clock selector */
+#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL	0x00000400	/* EMAC 2 PHY clock selector */
+#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL	0x00000200	/* EMAC 1 PHY clock selector */
+#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL	0x00000100	/* EMAC 0 PHY clock selector */
+#define SDR0_ETH_CFG_EMAC_2_1_SWAP	0x00000080	/* Swap EMAC2 with EMAC1 */
+#define SDR0_ETH_CFG_EMAC_0_3_SWAP	0x00000040	/* Swap EMAC0 with EMAC3 */
+#define SDR0_ETH_CFG_MDIO_SEL_MASK	0x00000030	/* MDIO source selector mask */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC0	0x00000000	/* MDIO source - EMAC0 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC1	0x00000010	/* MDIO source - EMAC1 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC2	0x00000020	/* MDIO source - EMAC2 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC3	0x00000030	/* MDIO source - EMAC3 */
+#define SDR0_ETH_CFG_ZMII_MODE_MASK	0x0000000C	/* ZMII bridge mode selector mask */
+#define SDR0_ETH_CFG_ZMII_SEL_MII	0x00000000	/* ZMII bridge mode - MII */
+#define SDR0_ETH_CFG_ZMII_SEL_SMII	0x00000004	/* ZMII bridge mode - SMII */
+#define SDR0_ETH_CFG_ZMII_SEL_RMII_10	0x00000008	/* ZMII bridge mode - RMII (10 Mbps) */
+#define SDR0_ETH_CFG_ZMII_SEL_RMII_100	0x0000000C	/* ZMII bridge mode - RMII (100 Mbps) */
+#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL	0x00000002	/* GMC Port 1 bridge selector */
+#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL	0x00000001	/* GMC Port 0 bridge selector */
+
+#define SDR0_ETH_CFG_ZMII_MODE_SHIFT		4
+#define SDR0_ETH_CFG_ZMII_MII_MODE		0x00
+#define SDR0_ETH_CFG_ZMII_SMII_MODE		0x01
+#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M		0x10
+#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M	0x11
+
+/* Miscealleneaous Function Reg. (SDR0_MFR) */
+#define SDR0_MFR		0x4300
+#define SDR0_MFR_T0TxFL		0x00800000	/* force parity error TAHOE0 Tx FIFO bits 0:63 */
+#define SDR0_MFR_T0TxFH		0x00400000	/* force parity error TAHOE0 Tx FIFO bits 64:127 */
+#define SDR0_MFR_T1TxFL		0x00200000	/* force parity error TAHOE1 Tx FIFO bits 0:63 */
+#define SDR0_MFR_T1TxFH		0x00100000	/* force parity error TAHOE1 Tx FIFO bits 64:127 */
+#define SDR0_MFR_E0TxFL		0x00008000	/* force parity error EMAC0 Tx FIFO bits 0:63 */
+#define SDR0_MFR_E0TxFH		0x00004000	/* force parity error EMAC0 Tx FIFO bits 64:127 */
+#define SDR0_MFR_E0RxFL		0x00002000	/* force parity error EMAC0 Rx FIFO bits 0:63 */
+#define SDR0_MFR_E0RxFH		0x00001000	/* force parity error EMAC0 Rx FIFO bits 64:127 */
+#define SDR0_MFR_E1TxFL		0x00000800	/* force parity error EMAC1 Tx FIFO bits 0:63 */
+#define SDR0_MFR_E1TxFH		0x00000400	/* force parity error EMAC1 Tx FIFO bits 64:127 */
+#define SDR0_MFR_E1RxFL		0x00000200	/* force parity error EMAC1 Rx FIFO bits 0:63 */
+#define SDR0_MFR_E1RxFH		0x00000100	/* force parity error EMAC1 Rx FIFO bits 64:127 */
+#define SDR0_MFR_E2TxFL		0x00000080	/* force parity error EMAC2 Tx FIFO bits 0:63 */
+#define SDR0_MFR_E2TxFH		0x00000040	/* force parity error EMAC2 Tx FIFO bits 64:127 */
+#define SDR0_MFR_E2RxFL		0x00000020	/* force parity error EMAC2 Rx FIFO bits 0:63 */
+#define SDR0_MFR_E2RxFH		0x00000010	/* force parity error EMAC2 Rx FIFO bits 64:127 */
+#define SDR0_MFR_E3TxFL		0x00000008	/* force parity error EMAC3 Tx FIFO bits 0:63 */
+#define SDR0_MFR_E3TxFH		0x00000004	/* force parity error EMAC3 Tx FIFO bits 64:127 */
+#define SDR0_MFR_E3RxFL		0x00000002	/* force parity error EMAC3 Rx FIFO bits 0:63 */
+#define SDR0_MFR_E3RxFH		0x00000001	/* force parity error EMAC3 Rx FIFO bits 64:127 */
+
+/* EMACx TX Status Register (SDR0_EMACxTXST)*/
+#define SDR0_EMAC0TXST		0x4400
+#define SDR0_EMAC1TXST		0x4401
+#define SDR0_EMAC2TXST		0x4402
+#define SDR0_EMAC3TXST		0x4403
+
+#define SDR0_EMACxTXST_FUR	0x02000000	/* TX FIFO underrun */
+#define SDR0_EMACxTXST_BC	0x01000000	/* broadcase address */
+#define SDR0_EMACxTXST_MC	0x00800000	/* multicast address */
+#define SDR0_EMACxTXST_UC	0x00400000	/* unicast address */
+#define SDR0_EMACxTXST_FP	0x00200000	/* frame paused by control packet */
+#define SDR0_EMACxTXST_BFCS	0x00100000	/* bad FCS in the transmitted frame */
+#define SDR0_EMACxTXST_CPF	0x00080000	/* TX control pause frame */
+#define SDR0_EMACxTXST_CF	0x00040000	/* TX control frame */
+#define SDR0_EMACxTXST_MSIZ	0x00020000	/* 1024-maxsize bytes transmitted */
+#define SDR0_EMACxTXST_1023	0x00010000	/* 512-1023 bytes transmitted */
+#define SDR0_EMACxTXST_511	0x00008000	/* 256-511 bytes transmitted */
+#define SDR0_EMACxTXST_255	0x00004000	/* 128-255 bytes transmitted */
+#define SDR0_EMACxTXST_127	0x00002000	/* 65-127 bytes transmitted */
+#define SDR0_EMACxTXST_64	0x00001000	/* 64 bytes transmitted */
+#define SDR0_EMACxTXST_SQE	0x00000800	/* SQE indication */
+#define SDR0_EMACxTXST_LOC	0x00000400	/* loss of carrier sense */
+#define SDR0_EMACxTXST_IERR	0x00000080	/* EMAC internal error */
+#define SDR0_EMACxTXST_EDF	0x00000040	/* excessive deferral */
+#define SDR0_EMACxTXST_ECOL	0x00000020	/* excessive collisions */
+#define SDR0_EMACxTXST_LCOL	0x00000010	/* late collision */
+#define SDR0_EMACxTXST_DFFR	0x00000008	/* deferred frame */
+#define SDR0_EMACxTXST_MCOL	0x00000004	/* multiple collision frame */
+#define SDR0_EMACxTXST_SCOL	0x00000002	/* single collision frame */
+#define SDR0_EMACxTXST_TXOK	0x00000001	/* transmit OK */
+
+/* EMACx RX Status Register (SDR0_EMACxRXST)*/
+#define SDR0_EMAC0RXST		0x4404
+#define SDR0_EMAC1RXST		0x4405
+#define SDR0_EMAC2RXST		0x4406
+#define SDR0_EMAC3RXST		0x4407
+
+#define SDR0_EMACxRXST_FOR	0x20000000	/* RX FIFO overrun */
+#define SDR0_EMACxRXST_BC	0x10000000	/* broadcast address */
+#define SDR0_EMACxRXST_MC	0x08000000	/* multicast address */
+#define SDR0_EMACxRXST_UC	0x04000000	/* unicast address */
+#define SDR0_EMACxRXST_UPR_MASK	0x03800000	/* user priority field */
+#define SDR0_EMACxRXST_UPR_ENCODE(n)	((((unsigned long)(n))&0x07)<<23)
+#define SDR0_EMACxRXST_VLAN	0x00400000	/* RX VLAN tagged frame */
+#define SDR0_EMACxRXST_LOOP	0x00200000	/* received in loop-back mode */
+#define SDR0_EMACxRXST_UOP	0x00100000	/* RX unsupported opcode */
+#define SDR0_EMACxRXST_CPF	0x00080000	/* RX control pause frame */
+#define SDR0_EMACxRXST_CF	0x00040000	/* RX control frame*/
+#define SDR0_EMACxRXST_MSIZ	0x00020000	/* 1024-MaxSize bytes recieved*/
+#define SDR0_EMACxRXST_1023	0x00010000	/* 512-1023 bytes received */
+#define SDR0_EMACxRXST_511	0x00008000	/* 128-511 bytes received */
+#define SDR0_EMACxRXST_255	0x00004000	/* 128-255 bytes received */
+#define SDR0_EMACxRXST_127	0x00002000	/* 65-127 bytes received */
+#define SDR0_EMACxRXST_64	0x00001000	/* 64 bytes received */
+#define SDR0_EMACxRXST_RUNT	0x00000800	/* runt frame */
+#define SDR0_EMACxRXST_SEVT	0x00000400	/* short event */
+#define SDR0_EMACxRXST_AERR	0x00000200	/* alignment error */
+#define SDR0_EMACxRXST_SERR	0x00000100	/* received with symbol error */
+#define SDR0_EMACxRXST_BURST	0x00000040	/* received burst */
+#define SDR0_EMACxRXST_F2L	0x00000020	/* frame is to long */
+#define SDR0_EMACxRXST_OERR	0x00000010	/* out of range length error */
+#define SDR0_EMACxRXST_IERR	0x00000008	/* in range length error */
+#define SDR0_EMACxRXST_LOST	0x00000004	/* frame lost due to internal EMAC receive error */
+#define SDR0_EMACxRXST_BFCS	0x00000002	/* bad FCS in the recieved frame */
+#define SDR0_EMACxRXST_RXOK	0x00000001	/* Recieve OK */
+
+/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
+#define SDR0_EMAC0REJCNT	0x4408
+#define SDR0_EMAC1REJCNT	0x4409
+#define SDR0_EMAC2REJCNT	0x440A
+#define SDR0_EMAC3REJCNT	0x440B
+
+#define SDR0_DDR0			0x00E1
+#define SDR0_DDR0_DPLLRST		0x80000000
+#define SDR0_DDR0_DDRM_MASK		0x60000000
+#define SDR0_DDR0_DDRM_DDR1		0x20000000
+#define SDR0_DDR0_DDRM_DDR2		0x40000000
+#define SDR0_DDR0_DDRM_ENCODE(n)	((((unsigned long)(n))&0x03)<<29)
+#define SDR0_DDR0_DDRM_DECODE(n)	((((unsigned long)(n))>>29)&0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n)	((((unsigned long)(n))&0x2FF)<<0)
+#define SDR0_DDR0_TUNE_DECODE(n)	((((unsigned long)(n))>>0)&0x2FF)
+#endif /* CONFIG_460EX || CONFIG_460GT */
 
 #define SDR0_SDCS_SDD			(0x80000000 >> 31)
 

@@ -3232,6 +3570,73 @@
 #define SDR0_SRST1_FPU          0x00004000 /* Floating Point Unit */
 #define SDR0_SRST1_KASU0        0x00002000 /* Kasumi Engine */
 
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+
+#define SDR0_SRST0		0x0200
+#define SDR0_SRST		SDR0_SRST0 /* for compatability reasons */
+#define SDR0_SRST0_BGO		0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4		0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC		0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB		0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0	0x08000000 /* Universal asynchronous receiver/transmitter 0 */
+#define SDR0_SRST0_UART1	0x04000000 /* Universal asynchronous receiver/transmitter 1 */
+#define SDR0_SRST0_IIC0		0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_IIC1		0x01000000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_GPIO0	0x00800000 /* General purpose I/O 0 */
+#define SDR0_SRST0_GPT		0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC		0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI		0x00100000 /* PCI */
+#define SDR0_SRST0_CPM0		0x00020000 /* Clock and power management */
+#define SDR0_SRST0_IMU		0x00010000 /* I2O DMA */
+#define SDR0_SRST0_UIC0		0x00008000 /* Universal interrupt controller 0*/
+#define SDR0_SRST0_UIC1		0x00004000 /* Universal interrupt controller 1*/
+#define SDR0_SRST0_SRAM		0x00002000 /* Universal interrupt controller 0*/
+#define SDR0_SRST0_UIC2		0x00001000 /* Universal interrupt controller 2*/
+#define SDR0_SRST0_UIC3		0x00000800 /* Universal interrupt controller 3*/
+#define SDR0_SRST0_OCM		0x00000400 /* Universal interrupt controller 0*/
+#define SDR0_SRST0_UART2	0x00000200 /* Universal asynchronous receiver/transmitter 2 */
+#define SDR0_SRST0_MAL		0x00000100 /* Media access layer */
+#define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
+#define SDR0_SRST0_L2CACHE	0x00000004 /* L2 Cache */
+#define SDR0_SRST0_UART3	0x00000002 /* Universal asynchronous receiver/transmitter 3 */
+#define SDR0_SRST0_GPIO1	0x00000001 /* General purpose I/O 1 */
+
+#define SDR0_SRST1		0x201
+#define SDR0_SRST1_RLL		0x80000000 /* SRIO RLL */
+#define SDR0_SRST1_SCP		0x40000000 /* Serial communications port */
+#define SDR0_SRST1_PLBARB	0x20000000 /* PLB Arbiter */
+#define SDR0_SRST1_EIPPKP	0x10000000 /* EIPPPKP */
+#define SDR0_SRST1_EIP94	0x08000000 /* EIP 94 */
+#define SDR0_SRST1_EMAC0	0x04000000 /* Ethernet media access controller 0 */
+#define SDR0_SRST1_EMAC1	0x02000000 /* Ethernet media access controller 1 */
+#define SDR0_SRST1_EMAC2	0x01000000 /* Ethernet media access controller 2 */
+#define SDR0_SRST1_EMAC3	0x00800000 /* Ethernet media access controller 3 */
+#define SDR0_SRST1_ZMII		0x00400000 /* Ethernet ZMII/RMII/SMII */
+#define SDR0_SRST1_RGMII0	0x00200000 /* Ethernet RGMII/RTBI 0 */
+#define SDR0_SRST1_RGMII1	0x00100000 /* Ethernet RGMII/RTBI 1 */
+#define SDR0_SRST1_DMA4		0x00080000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH	0x00040000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_SATAPHY	0x00020000 /* Serial ATA PHY */
+#define SDR0_SRST1_SRIODEV	0x00010000 /* Serial Rapid IO core, PCS, and serdes */
+#define SDR0_SRST1_SRIOPCS	0x00008000 /* Serial Rapid IO core and PCS */
+#define SDR0_SRST1_NDFC		0x00004000 /* Nand flash controller */
+#define SDR0_SRST1_SRIOPLB	0x00002000 /* Serial Rapid IO PLB */
+#define SDR0_SRST1_ETHPLL	0x00001000 /* Ethernet PLL */
+#define SDR0_SRST1_TAHOE1	0x00000800 /* Ethernet Tahoe 1 */
+#define SDR0_SRST1_TAHOE0	0x00000400 /* Ethernet Tahoe 0 */
+#define SDR0_SRST1_SGMII0	0x00000200 /* Ethernet SGMII 0 */
+#define SDR0_SRST1_SGMII1	0x00000100 /* Ethernet SGMII 1 */
+#define SDR0_SRST1_SGMII2	0x00000080 /* Ethernet SGMII 2 */
+#define SDR0_SRST1_AHB		0x00000040 /* PLB4XAHB bridge */
+#define SDR0_SRST1_USBOTGPHY	0x00000020 /* USB 2.0 OTG PHY */
+#define SDR0_SRST1_USBOTG	0x00000010 /* USB 2.0 OTG controller */
+#define SDR0_SRST1_USBHOST	0x00000008 /* USB 2.0 Host controller */
+#define SDR0_SRST1_AHBDMAC	0x00000004 /* AHB DMA controller */
+#define SDR0_SRST1_AHBICM	0x00000002 /* AHB inter-connect matrix */
+#define SDR0_SRST1_SATA		0x00000001 /* Serial ATA controller */
+
+#define SDR0_PCI0		0x1c0		/* PCI Configuration Register */
+
 #else
 
 #define SDR0_SRST_BGO			0x80000000

@@ -3270,7 +3675,15 @@
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && \
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
+#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
+#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
+#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000	/* PLB Early Clock Divisor */
+#define PLLSYS0_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
+#elif !defined (CONFIG_440GX) && \
     !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
     !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
     !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)

@@ -3624,7 +4037,8 @@
 #endif /* CONFIG_440GP */
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
 #define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
 

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new file mode 100644
index 0000000..6d8f230
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * canyonlands.h - configuration for Canyonlands (460EX)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_CANYONLANDS	1	/* Board is Canyonlands	*/
+#define CONFIG_440		1
+#define CONFIG_4xx		1	/* ... PPC4xx family */
+#define CONFIG_460EX		1	/* Specific PPC460EX support */
+
+#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0	*/
+
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CFG_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
+#define CFG_PCIE_BASE		0xc4000000	/* PCIe UTL regs */
+
+#define CFG_PCIE0_CFGBASE	0xc0000000
+#define CFG_PCIE1_CFGBASE	0xc1000000
+#define CFG_PCIE0_XCFGBASE	0xc3000000
+#define CFG_PCIE1_XCFGBASE	0xc3001000
+
+#define	CFG_PCIE0_UTLBASE	0xc08010000ULL	/* 36bit physical addr	*/
+
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE	0x000000000ULL	/* 36bit physical addr	*/
+
+/* EBC stuff */
+#define CFG_NAND_ADDR		0xE0000000
+#define CFG_BCSR_BASE		0xE1000000
+#define CFG_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space: 0xFF000000	*/
+#define CFG_FLASH_BASE		0xFC000000	/* later mapped to this addr	*/
+#define CFG_FLASH_BASE_PHYS_H	0x4
+#define CFG_FLASH_BASE_PHYS_L	0xCC000000
+#define CFG_FLASH_BASE_PHYS	(((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
+				 (u64)CFG_FLASH_BASE_PHYS_L)
+#define CFG_FLASH_SIZE		(64 << 20)
+
+#define CFG_OCM_BASE		0xE3000000	/* OCM: 16k		*/
+#define CFG_SRAM_BASE		0xE8000000	/* SRAM: 256k		*/
+#define CFG_LOCAL_CONF_REGS	0xEF000000
+
+#define CFG_PERIPHERAL_BASE	0xEF600000	/* internal peripherals */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()*/
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in OCM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+#define CFG_INIT_RAM_END	(4 << 10)
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI	1
+#undef CONFIG_UART1_CONSOLE	/* define this if you want console on UART1 */
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define	CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CFG_NAND_CS		3	/* NAND chip connected to CSx */
+#else
+#define	CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars  */
+#define CFG_NAND_CS		0	/* NAND chip connected to CSx */
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CFG_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
+
+#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+
+/*------------------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x50, 0x51}	/* SPD i2c spd addresses*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* fixed value for RQDC	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR		(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 	1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+/* RTC configuration */
+#define CONFIG_RTC_M41T62	1
+#define CFG_I2C_RTC_ADDR	0x68
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	1
+#define CONFIG_HAS_ETH0		1
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
+#define CONFIG_NET_MULTI	1
+
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG	1
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=canyonlands\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addtty;"				\
+		"bootm 200000\0"					\
+	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
+		"tftp ${fdt_addr} ${fdt_file};"				\
+		"run nfsargs addip addtty;"				\
+		"bootm 200000 - ${fdt_addr}\0"				\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
+	"bootfile=canyonlands/uImage\0"					\
+	"fdt_file=canyonlands/canyonlands.dtb\0"			\
+	"fdt_addr=400000\0"						\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc200000\0"					\
+	"initrd_high=30000000\0"					\
+	"load=tftp 200000 canyonlands/u-boot.bin\0"			\
+	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
+		"cp.b ${fileaddr} fffa0000 ${filesize};"		\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+	"nload=tftp 200000 canyonlands/u-boot-nand.bin\0"		\
+	"nupdate=nand erase 0 60000;nand write 200000 0 60000;"		\
+		"setenv filesize;saveenv\0"				\
+	"nupd=run nload nupdate\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Internal Definitions
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/*
+ * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ *
+ * For this we have to remap the CS0 and re-relocate the envrironment,
+ * since the original FLASH location which was needed upon startup is
+ * now not correct anymore.
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x10055e00
+#define CFG_EBC_PB0CR		(CFG_BOOT_BASE_ADDR | 0x9a000)
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CFG_EBC_PB2AP		0x00804240
+#define CFG_EBC_PB2CR		(CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
+
+/* Memory Bank 3 (NAND-FLASH) initialization						*/
+#define CFG_EBC_PB3AP		0x018003c0
+#define CFG_EBC_PB3CR		(CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
+
+#define CFG_EBC_CFG		0xB8400000		/*  EBC0_CFG */
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#endif	/* __CONFIG_H */