A bit of new code and sparse cleanups along the way

This is needed to support other localbus peripherals, such as NAND on FSL UPM.

Signed-off-by Anton Vorontsov <[email protected]>

---

Would be great if someone from the MTD community will ack this patch to go through powerpc trees.

Thanks,

drivers/mtd/nand/fsl_elbc_nand.c | 219 +

+-----------------------------------
include/asm-powerpc/fsl_lbc.h    |  223 +++++++++++++++++++++++++++++ 
+++++++++
2 files changed, 235 insertions(+), 207 deletions(-)

create mode 100644 include/asm-powerpc/fsl_lbc.h

drivers/mtd/nand/fsl_elbc_nand.c +1 -13

index b025dfe..378b7aa 100644
@@ -36,207 +36,12 @@
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-
+#include <asm/fsl_lbc.h>
 
 #define MAX_BANKS 8
 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
 
-struct elbc_bank {
-	__be32 br;             /**< Base Register  */
-#define BR_BA           0xFFFF8000
-#define BR_BA_SHIFT             15
-#define BR_PS           0x00001800
-#define BR_PS_SHIFT             11
-#define BR_PS_8         0x00000800  /* Port Size 8 bit */
-#define BR_PS_16        0x00001000  /* Port Size 16 bit */
-#define BR_PS_32        0x00001800  /* Port Size 32 bit */
-#define BR_DECC         0x00000600
-#define BR_DECC_SHIFT            9
-#define BR_DECC_OFF     0x00000000  /* HW ECC checking and  

generation off */
-#define BR_DECC_CHK 0x00000200 /* HW ECC checking on,
generation off */
-#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */

drivers/mtd/nand/fsl_elbc_nand.c +0 -63

-#define BR_WP           0x00000100
-#define BR_WP_SHIFT              8
-#define BR_MSEL         0x000000E0
-#define BR_MSEL_SHIFT            5
-#define BR_MS_GPCM      0x00000000  /* GPCM */
-#define BR_MS_FCM       0x00000020  /* FCM */
-#define BR_MS_SDRAM     0x00000060  /* SDRAM */
-#define BR_MS_UPMA      0x00000080  /* UPMA */
-#define BR_MS_UPMB      0x000000A0  /* UPMB */
-#define BR_MS_UPMC      0x000000C0  /* UPMC */
-#define BR_V            0x00000001
-#define BR_V_SHIFT               0
-#define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
-
-	__be32 or;             /**< Base Register  */
-#define OR0 0x5004
-#define OR1 0x500C
-#define OR2 0x5014
-#define OR3 0x501C
-#define OR4 0x5024
-#define OR5 0x502C
-#define OR6 0x5034
-#define OR7 0x503C
-
-#define OR_FCM_AM               0xFFFF8000
-#define OR_FCM_AM_SHIFT                 15
-#define OR_FCM_BCTLD            0x00001000
-#define OR_FCM_BCTLD_SHIFT              12
-#define OR_FCM_PGS              0x00000400
-#define OR_FCM_PGS_SHIFT                10
-#define OR_FCM_CSCT             0x00000200
-#define OR_FCM_CSCT_SHIFT                9
-#define OR_FCM_CST              0x00000100
-#define OR_FCM_CST_SHIFT                 8
-#define OR_FCM_CHT              0x00000080
-#define OR_FCM_CHT_SHIFT                 7
-#define OR_FCM_SCY              0x00000070
-#define OR_FCM_SCY_SHIFT                 4
-#define OR_FCM_SCY_1            0x00000010
-#define OR_FCM_SCY_2            0x00000020
-#define OR_FCM_SCY_3            0x00000030
-#define OR_FCM_SCY_4            0x00000040
-#define OR_FCM_SCY_5            0x00000050
-#define OR_FCM_SCY_6            0x00000060
-#define OR_FCM_SCY_7            0x00000070
-#define OR_FCM_RST              0x00000008
-#define OR_FCM_RST_SHIFT                 3
-#define OR_FCM_TRLX             0x00000004
-#define OR_FCM_TRLX_SHIFT                2
-#define OR_FCM_EHTR             0x00000002
-#define OR_FCM_EHTR_SHIFT                1
-};
-
-struct elbc_regs {
-	struct elbc_bank bank[8];
-	u8 res0[0x28];
-	__be32 mar;             /**< UPM Address Register */
-	u8 res1[0x4];
-	__be32 mamr;            /**< UPMA Mode Register */
-	__be32 mbmr;            /**< UPMB Mode Register */
-	__be32 mcmr;            /**< UPMC Mode Register */
-	u8 res2[0x8];
-	__be32 mrtpr;           /**< Memory Refresh Timer Prescaler  

Register */

drivers/mtd/nand/fsl_elbc_nand.c +0 -3

-	__be32 mdr;             /**< UPM Data Register */
-	u8 res3[0x4];
-	__be32 lsor;            /**< Special Operation Initiation Register  

*/

drivers/mtd/nand/fsl_elbc_nand.c +0 -74

-	__be32 lsdmr;           /**< SDRAM Mode Register */
-	u8 res4[0x8];
-	__be32 lurt;            /**< UPM Refresh Timer */
-	__be32 lsrt;            /**< SDRAM Refresh Timer */
-	u8 res5[0x8];
-	__be32 ltesr;           /**< Transfer Error Status Register */
-#define LTESR_BM   0x80000000
-#define LTESR_FCT  0x40000000
-#define LTESR_PAR  0x20000000
-#define LTESR_WP   0x04000000
-#define LTESR_ATMW 0x00800000
-#define LTESR_ATMR 0x00400000
-#define LTESR_CS   0x00080000
-#define LTESR_CC   0x00000001
-#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
-	__be32 ltedr;           /**< Transfer Error Disable Register */
-	__be32 lteir;           /**< Transfer Error Interrupt Register */
-	__be32 lteatr;          /**< Transfer Error Attributes Register */
-	__be32 ltear;           /**< Transfer Error Address Register */
-	u8 res6[0xC];
-	__be32 lbcr;            /**< Configuration Register */
-#define LBCR_LDIS  0x80000000
-#define LBCR_LDIS_SHIFT    31
-#define LBCR_BCTLC 0x00C00000
-#define LBCR_BCTLC_SHIFT   22
-#define LBCR_AHD   0x00200000
-#define LBCR_LPBSE 0x00020000
-#define LBCR_LPBSE_SHIFT   17
-#define LBCR_EPAR  0x00010000
-#define LBCR_EPAR_SHIFT    16
-#define LBCR_BMT   0x0000FF00
-#define LBCR_BMT_SHIFT      8
-#define LBCR_INIT  0x00040000
-	__be32 lcrr;            /**< Clock Ratio Register */
-#define LCRR_DBYP    0x80000000
-#define LCRR_DBYP_SHIFT      31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_SHIFT   28
-#define LCRR_ECL     0x03000000
-#define LCRR_ECL_SHIFT       24
-#define LCRR_EADC    0x00030000
-#define LCRR_EADC_SHIFT      16
-#define LCRR_CLKDIV  0x0000000F
-#define LCRR_CLKDIV_SHIFT     0
-	u8 res7[0x8];
-	__be32 fmr;             /**< Flash Mode Register */
-#define FMR_CWTO     0x0000F000
-#define FMR_CWTO_SHIFT       12
-#define FMR_BOOT     0x00000800
-#define FMR_ECCM     0x00000100
-#define FMR_AL       0x00000030
-#define FMR_AL_SHIFT          4
-#define FMR_OP       0x00000003
-#define FMR_OP_SHIFT          0
-	__be32 fir;             /**< Flash Instruction Register */
-#define FIR_OP0      0xF0000000
-#define FIR_OP0_SHIFT        28
-#define FIR_OP1      0x0F000000
-#define FIR_OP1_SHIFT        24
-#define FIR_OP2      0x00F00000
-#define FIR_OP2_SHIFT        20
-#define FIR_OP3      0x000F0000
-#define FIR_OP3_SHIFT        16
-#define FIR_OP4      0x0000F000
-#define FIR_OP4_SHIFT        12
-#define FIR_OP5      0x00000F00
-#define FIR_OP5_SHIFT         8
-#define FIR_OP6      0x000000F0
-#define FIR_OP6_SHIFT         4
-#define FIR_OP7      0x0000000F
-#define FIR_OP7_SHIFT         0
-#define FIR_OP_NOP   0x0	/* No operation and end of sequence */
-#define FIR_OP_CA    0x1        /* Issue current column address */
-#define FIR_OP_PA    0x2        /* Issue current block+page address  

*/

drivers/mtd/nand/fsl_elbc_nand.c +0 -6

-#define FIR_OP_UA    0x3        /* Issue user defined address */
-#define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
-#define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
-#define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
-#define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
-#define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer  

*/

drivers/mtd/nand/fsl_elbc_nand.c +0 -35

-#define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
-#define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
-#define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
-#define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
-#define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
-#define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
-#define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
-	__be32 fcr;             /**< Flash Command Register */
-#define FCR_CMD0     0xFF000000
-#define FCR_CMD0_SHIFT       24
-#define FCR_CMD1     0x00FF0000
-#define FCR_CMD1_SHIFT       16
-#define FCR_CMD2     0x0000FF00
-#define FCR_CMD2_SHIFT        8
-#define FCR_CMD3     0x000000FF
-#define FCR_CMD3_SHIFT        0
-	__be32 fbar;            /**< Flash Block Address Register */
-#define FBAR_BLK     0x00FFFFFF
-	__be32 fpar;            /**< Flash Page Address Register */
-#define FPAR_SP_PI   0x00007C00
-#define FPAR_SP_PI_SHIFT     10
-#define FPAR_SP_MS   0x00000200
-#define FPAR_SP_CI   0x000001FF
-#define FPAR_SP_CI_SHIFT      0
-#define FPAR_LP_PI   0x0003F000
-#define FPAR_LP_PI_SHIFT     12
-#define FPAR_LP_MS   0x00000800
-#define FPAR_LP_CI   0x000007FF
-#define FPAR_LP_CI_SHIFT      0
-	__be32 fbcr;            /**< Flash Byte Count Register */
-#define FBCR_BC      0x00000FFF
-	u8 res11[0x8];
-	u8 res8[0xF00];
-};
-

struct fsl_elbc_ctrl;

/* mtd information per set */

drivers/mtd/nand/fsl_elbc_nand.c +2 -2

@@ -261,7 +66,7 @@ struct fsl_elbc_ctrl {
 
 	/* device info */
 	struct device *dev;
-	struct elbc_regs __iomem *regs;
+	struct fsl_lbc_regs __iomem *regs;
 	int irq;
 	wait_queue_head_t irq_wait;
 	unsigned int irq_status; /* status read from LTESR by irq handler */

@@ -322,7 +127,7 @@ static void set_addr(struct mtd_info *mtd, int  
 column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	int buf_num;
 

	ctrl->page = page_addr;

drivers/mtd/nand/fsl_elbc_nand.c +1 -1

@@ -363,7 +168,7 @@ static int fsl_elbc_run_command(struct mtd_info  
 *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
 	/* Setup the FMR[OP] to execute without write protection */

	out_be32(&lbc->fmr, priv->fmr | 3);

drivers/mtd/nand/fsl_elbc_nand.c +1 -1

@@ -406,7 +211,7 @@ static void fsl_elbc_do_read(struct nand_chip  
 *chip, int oob)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
 	if (priv->page_size) {

		out_be32(&lbc->fir,

drivers/mtd/nand/fsl_elbc_nand.c +2 -2

@@ -439,7 +244,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info  
 *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
 	ctrl->use_mdr = 0;

@@ -775,7 +580,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd,  
 struct nand_chip *chip)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
 	if (ctrl->status != LTESR_CC)

		return NAND_STATUS_FAIL;

drivers/mtd/nand/fsl_elbc_nand.c +1 -1

@@ -807,7 +612,7 @@ static int fsl_elbc_chip_init_tail(struct  
 mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	unsigned int al;
 

	/* calculate FMR Address Length field */

drivers/mtd/nand/fsl_elbc_nand.c +1 -1

@@ -922,7 +727,7 @@ static void fsl_elbc_write_page(struct mtd_info  
 *mtd,
 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 {
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	struct nand_chip *chip = &priv->chip;
 

	dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);

drivers/mtd/nand/fsl_elbc_nand.c +1 -1

@@ -986,7 +791,7 @@ static int fsl_elbc_chip_remove(struct  
 fsl_elbc_mtd *priv)
 static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
                               struct device_node *node)
 {
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	struct fsl_elbc_mtd *priv;
 	struct resource res;

#ifdef CONFIG_MTD_PARTITIONS

drivers/mtd/nand/fsl_elbc_nand.c +2 -2

@@ -1083,7 +888,7 @@ err:
 
 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
 {
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
 	/* clear event registers */
 	setbits32(&lbc->ltesr, LTESR_NAND_MASK);

@@ -1128,7 +933,7 @@ static int __devexit  
 fsl_elbc_ctrl_remove(struct of_device *ofdev)
 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
 {
 	struct fsl_elbc_ctrl *ctrl = data;
-	struct elbc_regs __iomem *lbc = ctrl->regs;
+	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	__be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
 

	if (status) {

include/asm-powerpc/fsl_lbc.h new file +8 -0

new file mode 100644
index 0000000..13a3c28
@@ -0,0 +1,223 @@
+/* Freescale Local Bus Controller
+ *
+ * Copyright (c) 2006-2007 Freescale Semiconductor
+ *
+ * Authors: Nick Spence <[email protected]>,
+ *          Scott Wood <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or  

modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */

include/asm-powerpc/fsl_lbc.h new file +18 -0

+
+#ifndef __ASM_FSL_LBC_H
+#define __ASM_FSL_LBC_H
+
+#include <linux/types.h>
+
+struct fsl_lbc_bank {
+	__be32 br;             /**< Base Register  */
+#define BR_BA           0xFFFF8000
+#define BR_BA_SHIFT             15
+#define BR_PS           0x00001800
+#define BR_PS_SHIFT             11
+#define BR_PS_8         0x00000800  /* Port Size 8 bit */
+#define BR_PS_16        0x00001000  /* Port Size 16 bit */
+#define BR_PS_32        0x00001800  /* Port Size 32 bit */
+#define BR_DECC         0x00000600
+#define BR_DECC_SHIFT            9
+#define BR_DECC_OFF     0x00000000  /* HW ECC checking and  

generation off */
+#define BR_DECC_CHK 0x00000200 /* HW ECC checking on,
generation off */
+#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */

include/asm-powerpc/fsl_lbc.h new file +63 -0

+#define BR_WP           0x00000100
+#define BR_WP_SHIFT              8
+#define BR_MSEL         0x000000E0
+#define BR_MSEL_SHIFT            5
+#define BR_MS_GPCM      0x00000000  /* GPCM */
+#define BR_MS_FCM       0x00000020  /* FCM */
+#define BR_MS_SDRAM     0x00000060  /* SDRAM */
+#define BR_MS_UPMA      0x00000080  /* UPMA */
+#define BR_MS_UPMB      0x000000A0  /* UPMB */
+#define BR_MS_UPMC      0x000000C0  /* UPMC */
+#define BR_V            0x00000001
+#define BR_V_SHIFT               0
+#define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+	__be32 or;             /**< Base Register  */
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_FCM_AM               0xFFFF8000
+#define OR_FCM_AM_SHIFT                 15
+#define OR_FCM_BCTLD            0x00001000
+#define OR_FCM_BCTLD_SHIFT              12
+#define OR_FCM_PGS              0x00000400
+#define OR_FCM_PGS_SHIFT                10
+#define OR_FCM_CSCT             0x00000200
+#define OR_FCM_CSCT_SHIFT                9
+#define OR_FCM_CST              0x00000100
+#define OR_FCM_CST_SHIFT                 8
+#define OR_FCM_CHT              0x00000080
+#define OR_FCM_CHT_SHIFT                 7
+#define OR_FCM_SCY              0x00000070
+#define OR_FCM_SCY_SHIFT                 4
+#define OR_FCM_SCY_1            0x00000010
+#define OR_FCM_SCY_2            0x00000020
+#define OR_FCM_SCY_3            0x00000030
+#define OR_FCM_SCY_4            0x00000040
+#define OR_FCM_SCY_5            0x00000050
+#define OR_FCM_SCY_6            0x00000060
+#define OR_FCM_SCY_7            0x00000070
+#define OR_FCM_RST              0x00000008
+#define OR_FCM_RST_SHIFT                 3
+#define OR_FCM_TRLX             0x00000004
+#define OR_FCM_TRLX_SHIFT                2
+#define OR_FCM_EHTR             0x00000002
+#define OR_FCM_EHTR_SHIFT                1
+};
+
+struct fsl_lbc_regs {
+	struct fsl_lbc_bank bank[8];
+	u8 res0[0x28];
+	__be32 mar;             /**< UPM Address Register */
+	u8 res1[0x4];
+	__be32 mamr;            /**< UPMA Mode Register */
+	__be32 mbmr;            /**< UPMB Mode Register */
+	__be32 mcmr;            /**< UPMC Mode Register */
+	u8 res2[0x8];
+	__be32 mrtpr;           /**< Memory Refresh Timer Prescaler  

Register */

include/asm-powerpc/fsl_lbc.h new file +3 -0

+	__be32 mdr;             /**< UPM Data Register */
+	u8 res3[0x4];
+	__be32 lsor;            /**< Special Operation Initiation Register  

*/

include/asm-powerpc/fsl_lbc.h new file +74 -0

+	__be32 lsdmr;           /**< SDRAM Mode Register */
+	u8 res4[0x8];
+	__be32 lurt;            /**< UPM Refresh Timer */
+	__be32 lsrt;            /**< SDRAM Refresh Timer */
+	u8 res5[0x8];
+	__be32 ltesr;           /**< Transfer Error Status Register */
+#define LTESR_BM   0x80000000
+#define LTESR_FCT  0x40000000
+#define LTESR_PAR  0x20000000
+#define LTESR_WP   0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS   0x00080000
+#define LTESR_CC   0x00000001
+#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+	__be32 ltedr;           /**< Transfer Error Disable Register */
+	__be32 lteir;           /**< Transfer Error Interrupt Register */
+	__be32 lteatr;          /**< Transfer Error Attributes Register */
+	__be32 ltear;           /**< Transfer Error Address Register */
+	u8 res6[0xC];
+	__be32 lbcr;            /**< Configuration Register */
+#define LBCR_LDIS  0x80000000
+#define LBCR_LDIS_SHIFT    31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT   22
+#define LBCR_AHD   0x00200000
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT   17
+#define LBCR_EPAR  0x00010000
+#define LBCR_EPAR_SHIFT    16
+#define LBCR_BMT   0x0000FF00
+#define LBCR_BMT_SHIFT      8
+#define LBCR_INIT  0x00040000
+	__be32 lcrr;            /**< Clock Ratio Register */
+#define LCRR_DBYP    0x80000000
+#define LCRR_DBYP_SHIFT      31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT   28
+#define LCRR_ECL     0x03000000
+#define LCRR_ECL_SHIFT       24
+#define LCRR_EADC    0x00030000
+#define LCRR_EADC_SHIFT      16
+#define LCRR_CLKDIV  0x0000000F
+#define LCRR_CLKDIV_SHIFT     0
+	u8 res7[0x8];
+	__be32 fmr;             /**< Flash Mode Register */
+#define FMR_CWTO     0x0000F000
+#define FMR_CWTO_SHIFT       12
+#define FMR_BOOT     0x00000800
+#define FMR_ECCM     0x00000100
+#define FMR_AL       0x00000030
+#define FMR_AL_SHIFT          4
+#define FMR_OP       0x00000003
+#define FMR_OP_SHIFT          0
+	__be32 fir;             /**< Flash Instruction Register */
+#define FIR_OP0      0xF0000000
+#define FIR_OP0_SHIFT        28
+#define FIR_OP1      0x0F000000
+#define FIR_OP1_SHIFT        24
+#define FIR_OP2      0x00F00000
+#define FIR_OP2_SHIFT        20
+#define FIR_OP3      0x000F0000
+#define FIR_OP3_SHIFT        16
+#define FIR_OP4      0x0000F000
+#define FIR_OP4_SHIFT        12
+#define FIR_OP5      0x00000F00
+#define FIR_OP5_SHIFT         8
+#define FIR_OP6      0x000000F0
+#define FIR_OP6_SHIFT         4
+#define FIR_OP7      0x0000000F
+#define FIR_OP7_SHIFT         0
+#define FIR_OP_NOP   0x0	/* No operation and end of sequence */
+#define FIR_OP_CA    0x1        /* Issue current column address */
+#define FIR_OP_PA    0x2        /* Issue current block+page address  

*/

include/asm-powerpc/fsl_lbc.h new file +6 -0

+#define FIR_OP_UA    0x3        /* Issue user defined address */
+#define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer  

*/

include/asm-powerpc/fsl_lbc.h new file +36 -0

+#define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
+#define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
+	__be32 fcr;             /**< Flash Command Register */
+#define FCR_CMD0     0xFF000000
+#define FCR_CMD0_SHIFT       24
+#define FCR_CMD1     0x00FF0000
+#define FCR_CMD1_SHIFT       16
+#define FCR_CMD2     0x0000FF00
+#define FCR_CMD2_SHIFT        8
+#define FCR_CMD3     0x000000FF
+#define FCR_CMD3_SHIFT        0
+	__be32 fbar;            /**< Flash Block Address Register */
+#define FBAR_BLK     0x00FFFFFF
+	__be32 fpar;            /**< Flash Page Address Register */
+#define FPAR_SP_PI   0x00007C00
+#define FPAR_SP_PI_SHIFT     10
+#define FPAR_SP_MS   0x00000200
+#define FPAR_SP_CI   0x000001FF
+#define FPAR_SP_CI_SHIFT      0
+#define FPAR_LP_PI   0x0003F000
+#define FPAR_LP_PI_SHIFT     12
+#define FPAR_LP_MS   0x00000800
+#define FPAR_LP_CI   0x000007FF
+#define FPAR_LP_CI_SHIFT      0
+	__be32 fbcr;            /**< Flash Byte Count Register */
+#define FBCR_BC      0x00000FFF
+	u8 res11[0x8];
+	u8 res8[0xF00];
+};
+
+#endif /* __ASM_FSL_LBC_H */

Signature · 6 lines

1.5.2.2

_______________________________________________
Linuxppc-dev mailing list
[email protected]
https://ozlabs.org/mailman/listinfo/linuxppc-dev

David, can you ack this. It looks good to me but want a MTD maintainer ack before having it go through the powerpc tree.

This is needed to support other localbus peripherals, such as NAND on FSL UPM.

Signed-off-by Anton Vorontsov <[email protected]>

---

Would be great if someone from the MTD community will ack this patch to go through powerpc trees.

Thanks,

drivers/mtd/nand/fsl_elbc_nand.c | 219 +

+-----------------------------------
include/asm-powerpc/fsl_lbc.h    |  223 +++++++++++++++++++++++++++++ 
+++++++++
2 files changed, 235 insertions(+), 207 deletions(-)

create mode 100644 include/asm-powerpc/fsl_lbc.h

These will be used by the FSL UPM NAND driver.

Signed-off-by Anton Vorontsov <[email protected]>

---

arch/powerpc/Kconfig          |    5 ++
arch/powerpc/sysdev/Makefile  |    1 +
arch/powerpc/sysdev/fsl_lbc.c |   99 ++++++++++++++++++++++++++++++++ 
+++++++++
include/asm-powerpc/fsl_lbc.h |   63 ++++++++++++++++++++++++++
4 files changed, 168 insertions(+), 0 deletions(-)

create mode 100644 arch/powerpc/sysdev/fsl_lbc.c

arch/powerpc/Kconfig +5 -0

index ef12db0..9c68592 100644
@@ -491,6 +491,11 @@ config FSL_PCI
 	bool
 	select PPC_INDIRECT_PCI
 
+config FSL_LBC
+	bool
+	help
+	  Freescale Localbus support
+
 # Yes MCA RS/6000s exist but Linux-PPC does not currently support any

config MCA
bool

arch/powerpc/sysdev/Makefile +0 -0

index 15f3e85..62b6ef0 100644
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART)		+= dart_iommu.o

obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o
+obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/

arch/powerpc/sysdev/fsl_lbc.c new file +8 -0

new file mode 100644
index 0000000..b59f2f4
@@ -0,0 +1,99 @@
+/*
+ * Freescale UPM routines.
+ *
+ * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or  

modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */

arch/powerpc/sysdev/fsl_lbc.c new file +29 -0

+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <asm/fsl_lbc.h>
+
+spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
+
+struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+EXPORT_SYMBOL(fsl_lbc_regs);
+
+static char __initdata *compat_lbc[] = {
+	"fsl,pq2-localbus",
+	"fsl,pq2pro-localbus",
+	"fsl,pq3-localbus",
+	"fsl,elbc",
+};
+
+static int __init fsl_lbc_init(void)
+{
+	struct device_node *lbus;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
+		lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
+		if (lbus)
+			goto found;
+	}
+	return -ENODEV;
+

arch/powerpc/sysdev/fsl_lbc.c new file +48 -0

+{
+	int i;
+	__be32 br;
+	__be32 or;
+
+	if (!fsl_lbc_regs)
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
+		br = in_be32(&fsl_lbc_regs->bank[i].br);
+		or = in_be32(&fsl_lbc_regs->bank[i].or);
+
+		if (br & BR_V && (br & or & BR_BA) == base)
+			goto found;
+	}
+
+	return -ENOENT;
+found:
+	switch (br & BR_MSEL) {
+	case BR_MS_UPMA:
+		upm->mxmr = &fsl_lbc_regs->mamr;
+		break;
+	case BR_MS_UPMB:
+		upm->mxmr = &fsl_lbc_regs->mbmr;
+		break;
+	case BR_MS_UPMC:
+		upm->mxmr = &fsl_lbc_regs->mcmr;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (br & BR_PS) {
+	case BR_PS_8:
+		upm->width = 8;
+		break;
+	case BR_PS_16:
+		upm->width = 16;
+		break;
+	case BR_PS_32:
+		upm->width = 32;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}

Quoted 1 line · Anton Vorontsov

These will be used by the FSL UPM NAND driver.

can this be a bit more descriptive. What exactly are these functions trying to accomplish.

Quoted 1 line

+int fsl_upm_find(u32 base, struct fsl_upm *upm)

what is base?

Quoted 3 lines · Kumar Gala

Quoted 1 line · Anton Vorontsov

These will be used by the FSL UPM NAND driver.

can this be a bit more descriptive. What exactly are these functions trying to accomplish.

Yeah, sorry about that. Here is updated patch, with a bit more descriptive comment, and highly kernel-doc'ed functions.

Quoted 2 lines

Quoted 1 line

+int fsl_upm_find(u32 base, struct fsl_upm *upm)

what is base?

Address base, as in LBC Base address register. Fixed down below.

+/**
+ * fsl_upm_find - find pre-programmed UPM via base address
+ * @addr_base: base address of the memory bank controlled by the UPM
+ * @upm: pointer to the allocated fsl_upm structure
+ *
+ * This function walks UPMs comparing "Base address" field of the BR registers
+ * with the supplied addr_base argument. When bases are match, this function
+ * fills fsl_upm structure so you can use it with the rest of UPM API. On
+ * success this function returns 0, otherwise it returns appropriate errno
+ * value.
+ */

Quoted 9 lines · Anton Vorontsov

Quoted 4 lines · Kumar Gala

Quoted 1 line · Anton Vorontsov

These will be used by the FSL UPM NAND driver.

can this be a bit more descriptive. What exactly are these functions
trying to accomplish.

Yeah, sorry about that. Here is updated patch, with a bit more descriptive comment, and highly kernel-doc'ed functions.

Quoted 4 lines

Quoted 2 lines

Quoted 1 line

+int fsl_upm_find(u32 base, struct fsl_upm *upm)

what is base?

Address base, as in LBC Base address register. Fixed down below.

Should it be phys_addr_t?

Quoted 11 lines

+/**
+ * fsl_upm_find - find pre-programmed UPM via base address
+ * @addr_base: base address of the memory bank controlled by the UPM
+ * @upm: pointer to the allocated fsl_upm structure
+ *
+ * This function walks UPMs comparing "Base address" field of the BR registers
+ * with the supplied addr_base argument. When bases are match, this function
+ * fills fsl_upm structure so you can use it with the rest of UPM API. On
+ * success this function returns 0, otherwise it returns appropriate errno
+ * value.
+ */

The FCM driver does something very similar; could we name this something more generic such as fsl_lbc_find?

Ok. Updated patch follows.

Thanks!

- - - -
From: Anton Vorontsov <[email protected]>
Subject: [POWERPC] fsl_lbc: implement few UPM routines

Subject: [POWERPC] fsl_lbc: implement few UPM routines

Freescale UPM can be used to adjust localbus timings or to generate orbitrary, pre-programmed "patterns" on the external Localbus signals. This patch implements few routines so drivers could work with UPMs in safe and generic manner.

So far there is just one user of these routines: Freescale UPM NAND driver.

Signed-off-by Anton Vorontsov <[email protected]>

---

arch/powerpc/Kconfig          |    5 ++
arch/powerpc/sysdev/Makefile  |    1 +
arch/powerpc/sysdev/fsl_lbc.c |  129 ++++++++++++++++++++++++++++++++ 
+++++++++
include/asm-powerpc/fsl_lbc.h |   88 ++++++++++++++++++++++++++++
4 files changed, 223 insertions(+), 0 deletions(-)

create mode 100644 arch/powerpc/sysdev/fsl_lbc.c

qe_muram_offset is the reverse of the qe_muram_addr, will be used for the Freescale QE USB Host Controller driver.

This patch also moves qe_muram_addr into the qe.h header, plus adds __iomem hints to use with sparse.

qe_muram_offset is the reverse of the qe_muram_addr, will be used for the Freescale QE USB Host Controller driver.

This patch also moves qe_muram_addr into the qe.h header, plus adds __iomem hints to use with sparse.

Signed-off-by Anton Vorontsov <[email protected]>

---

arch/powerpc/sysdev/qe_lib/qe.c |    8 +-------
include/asm-powerpc/immap_qe.h  |    2 +-
include/asm-powerpc/qe.h        |   11 ++++++++++-
3 files changed, 12 insertions(+), 9 deletions(-)

Headers should include prototypes they use, otherwise build will break if we use it without explicitly including io.h:

CC arch/powerpc/sysdev/qe_lib/gtm.o
In file included from include/asm/qe.h:20,
from arch/powerpc/sysdev/qe_lib/gtm.c:18:
include/asm/immap_qe.h: In function =E2=80=98immrbar_virt_to_phys=E2=80=99=

include/asm/immap_qe.h:480: error: implicit declaration of function =E2=20=

=80=98virt_to_phys=E2=80=99
make[2]: *** [arch/powerpc/sysdev/qe_lib/gtm.o] Error 1 make[1]: *** [arch/powerpc/sysdev/qe_lib] Error 2

gtm.c needs qe.h (which includes immap_qe.h) to use qe_get_brg_clk().

Signed-off-by Anton Vorontsov <[email protected]>

---
include/asm-powerpc/immap_qe.h | 1 +

1 files changed, 1 insertions(+), 0 deletions(-)

qe_get_brg_clk() will be used by the fsl_gtm routines.

Quoted 1 line · Anton Vorontsov

qe_get_brg_clk() will be used by the fsl_gtm routines.

What is the GTM code going to be used for?

qe_get_brg_clk() will be used by the fsl_gtm routines.

Signed-off-by Anton Vorontsov <[email protected]>

---

arch/powerpc/sysdev/qe_lib/qe.c |    5 +++--
include/asm-powerpc/qe.h        |    1 +
2 files changed, 4 insertions(+), 2 deletions(-)

Documentation/powerpc/booting-without-of.txt +5 -0

+    Example:
+
+    gtm@500 {
+    	compatible = "fsl,gtm";
+    	reg = <0x500 0x40>;

+static int __init gtm_init_gtm(void)

arch/powerpc/sysdev/qe_lib/gtm.c new file +17 -0

+/*
+ * For now we just fixing up the clock -- it's brg-frequency for QE
+ * chips, generic code does not and should not know these details.
+ *
+ * Later we might want to set up BRGs, when QE will actually use
+ * them (there are TIMERCS bits in the CMXGCR register, but today
+ * these bits seem to be no-ops.
+ */
+static int __init qe_init_gtm(void)
+{
+	struct device_node *np;
+
+	for_each_compatible_node(np, NULL, "fsl,qe-gtm") {
+		struct gtm *gtm = np->data;
+
+		if (!gtm) {
+			/* fsl,qe-gtm without fsl,gtm compatible? */

+ * @ffr: free run flag

+ * Thus function (re)sets GTM timer so it counts up to the reference value and
+ * fires the interrupt when the value is reached. If ffr flag is set, timer
+ * will also reset itself upon reference value, otherwise it continues to
+ * increment.
+ */

include/asm-powerpc/fsl_gtm.h new file +1 -0

+extern int gtm_reset_ref_timer_16(struct gtm_timer *tmr, unsigned int hz,

Documentation/powerpc/booting-without-of.txt platforms are moved over to use the flattened-device-tree model. · line 2822

Quoted 6 lines · Anton Vorontsov

Documentation/powerpc/booting-without-of.txt +6 -0

+    Required properties:
+      - compatible : should be "fsl,gtm" ("fsl,qe-gtm" in addition for QE
+                     GTMs).
+      - reg : should contain gtm registers location and length (0x40).
+      - interrupts : should contain four interrupts.
+      - interrupt-parent : interrupt source phandle.

interrupt-parent isn't required; it's perfectly valid to specify that in the parent node instead.

Quoted 10 lines

Documentation/powerpc/booting-without-of.txt +9 -0

+    Example:
+
+    gtm@500 {
+    	compatible = "fsl,gtm";
+    	reg = <0x500 0x40>;
+    	interrupts = <90 8 78 8 84 8 72 8>;
+    	interrupt-parent = <&ipic>;
+    };
+

Documentation/powerpc/booting-without-of.txt platforms are moved over to use the flattened-device-tree model. · line 2838

Quoted 6 lines

Documentation/powerpc/booting-without-of.txt +6 -0

+    gtm@440 {
+    	compatible = "fsl,qe-gtm", "fsl,gtm";
+    	reg = <0x440 0x40>;
+    	interrupts = <12 13 14 15>;
+    	interrupt-parent = <&qeic>;
+    };

"timer" would be a better node name than "gtm".

Quoted 1 line

+static int __init gtm_init_gtm(void)

Name seems rather redundant... what's wrong with gtm_init()?

Quoted 21 lines

arch/powerpc/sysdev/qe_lib/gtm.c new file +21 -0

+/*
+ * For now we just fixing up the clock -- it's brg-frequency for QE
+ * chips, generic code does not and should not know these details.
+ *
+ * Later we might want to set up BRGs, when QE will actually use
+ * them (there are TIMERCS bits in the CMXGCR register, but today
+ * these bits seem to be no-ops.
+ */
+static int __init qe_init_gtm(void)
+{
+	struct device_node *np;
+
+	for_each_compatible_node(np, NULL, "fsl,qe-gtm") {
+		struct gtm *gtm = np->data;
+
+		if (!gtm) {
+			/* fsl,qe-gtm without fsl,gtm compatible? */
+			WARN_ON(1);
+			continue;
+		}
+

arch/powerpc/sysdev/qe_lib/gtm.c line 47

Quoted 6 lines

arch/powerpc/sysdev/qe_lib/gtm.c new file +6 -0

+		gtm->clock = qe_get_brg_clk();
+	}
+
+	return 0;
+}
+arch_initcall(qe_init_gtm);

If this happens before the gtm_init_gtm(),

then np->data will not be set.

If this happens after gtm_init_gtm(), then gtm_init_gtm() will fail in gtm_get_clock(), if there's no clock-frequency -- and if there is, then why do we need qe_init_gtm() at all?

Quoted 5 lines

+/**
+ * gtm_get_timer - request GTM timer for use with the rest of GTM API
+ * @width: timer width (only 16 bits wide timers implemented so far)
+ *
+ * This function reserves GTM timer for later use. It returns gtm_timer

Quoted 4 lines

+ * structure to use with the rest of GTM API, you should use timer->irq
+ * to manage timer interrupt.
+ */
+extern struct gtm_timer *gtm_get_timer(int width);

To support using the GTM as a wakeup from deep sleep on 831x (which I've had a patch pending for quite a while now), we'll need some way of reserving a specific timer (only GTM1, timer 4 is supported).

Quoted 10 lines

include/asm-powerpc/fsl_gtm.h new file +10 -0

+/**
+ * gtm_put_timer - release GTM timer
+ * @width:	timer width (only 16 bits wide timers implemented so far)
+ *
+ * This function releases GTM timer sp others might request it.
+ */
+extern void gtm_put_timer(struct gtm_timer *tmr);
+
+/**
+ * gtm_reset_ref_timer_16 - (re)set single (16 bits) timer in reference mode

Quoted 3 lines

+ * @tmr: pointer to the gtm_timer structure obtained from gtm_get_timer
+ * @hz: timer rate in Hz
+ * @ref: refernce value

How about "period" or "expiry"? And it'd be better to let the caller request a time in some real unit (e.g. microseconds), and let the gtm driver figure out how to divide that between prescaler and reference value, especially in the absence of a way to ask for the allowable hz ranges.

Quoted 1 line

+ * @ffr: free run flag

Could we call it something more intuitive such as "freerun"?

Quoted 6 lines

+ * Thus function (re)sets GTM timer so it counts up to the reference value and
+ * fires the interrupt when the value is reached. If ffr flag is set, timer
+ * will also reset itself upon reference value, otherwise it continues to
+ * increment.
+ */

include/asm-powerpc/fsl_gtm.h new file +1 -0

+extern int gtm_reset_ref_timer_16(struct gtm_timer *tmr, unsigned int hz,

include/asm-powerpc/fsl_gtm.h line 125

Quoted 10 lines

include/asm-powerpc/fsl_gtm.h new file +10 -0

+				  u16 ref, bool ffr);
+
+/**
+ * gtm_ack_ref_timer_16 - acknowledge timer event (free-run timers only)
+ * @tmr:	pointer to the gtm_timer structure obtained from gtm_get_timer
+ *
+ * Thus function used to acknowledge timer interrupt event, use it inside the
+ * interrupt handler.
+ */
+static inline void gtm_ack_ref_timer_16(struct gtm_timer *tmr)

What does the "ref" mean in these names?

How about "gtm_arm_timer16" and "gtm_ack_timer16"?

arch/powerpc/sysdev/fsl_gtm.c line 127

Quoted 4 lines

arch/powerpc/sysdev/fsl_gtm.c new file +3 -0

+{
+	out_be16(tmr->gtevr, 0xFFFF);
+}

You need to include <asm/io.h> for this.

Don't blindly clear all events, just the events that have been acted upon. Either take the events as an argument, or make the ack function specifi

Quoted 2 lines

Quoted 1 line

+arch_initcall(qe_init_gtm);

If this happens before the gtm_init_gtm(),

"If" isn't possible, order is guaranteed.

Quoted 1 line

then np->data will not be set.

It's a bug in the device tree or in the Linux code then.

Quoted 3 lines

If this happens after gtm_init_gtm(), then gtm_init_gtm() will fail in gtm_get_clock(), if there's no clock-frequency -- and if there is, then why do we need qe_init_gtm() at all?

Because for the QE clock-frequency != brg-frequency.

Quoted 4 lines

Quoted 1 line

+extern struct gtm_timer *gtm_get_timer(int width);

To support using the GTM as a wakeup from deep sleep on 831x (which I've had a patch pending for quite a while now), we'll need some way of reserving a specific timer (only GTM1, timer 4 is supported).

You can add reserve function either in the PM driver (if any), or

you can do something in the device tree (wakeup-timer = <..>). I don't see any problems if you want to implement it.

Quoted 4 lines · Anton Vorontsov

Quoted 2 lines

Quoted 1 line

+arch_initcall(qe_init_gtm);

If this happens before the gtm_init_gtm(),

"If" isn't possible, order is guaranteed.

You use arch_initcall for both, so you're relying on link order. I think this at least merits a comment.

Quoted 3 lines

Quoted 1 line

then np->data will not be set.

It's a bug in the device tree or in the Linux code then.

Hmm? It's set by gtm_init_gtm(). If this code runs before gtm_init_gtm(), what are you expecting to initialize np->data?

Quoted 6 lines

Quoted 4 lines

If this happens after gtm_init_gtm(), then gtm_init_gtm() will fail in gtm_get_clock(), if there's no clock-frequency -- and if there is, then why
do we need qe_init_gtm() at all?

Because for the QE clock-frequency != brg-frequency.

Sorry, I missed that you were getting clock-frequency from the parent, rather than the gtm node. If you do the latter, then you can just stick the relevant frequency in the gtm node and not worry about where it comes from. This would be analogous to how UART clocks are specified.

Also, what if some arch_initcall runs between gtm_init_gtm and qe_init_gtm, that registers itself as a client of the gtm driver, and uses the wrong clock value?

Quoted 7 lines

Quoted 5 lines

Quoted 1 line

+extern struct gtm_timer *gtm_get_timer(int width);

To support using the GTM as a wakeup from deep sleep on 831x (which I've had
a patch pending for quite a while now), we'll need some way of reserving a specific timer (only GTM1, timer 4 is supported).

You can add reserve function either in the PM driver (if any), or

What I meant was that there needs to be some way of telling this driver not to hand the reserved timer out to some other client.

Quoted 2 lines

you can do something in the device tree (wakeup-timer = <..>). I don't see any problems if you want to implement it.

How about simply having optional arguments to gtm_get_timer() to specify the GTM device and timer number, which will fail if it's already in use?
Then, the PM driver simply needs to run early enough to grab the timer
it needs.

Quoted 8 lines · Scott Wood

Quoted 3 lines · Anton Vorontsov

Quoted 2 lines

Quoted 1 line

+arch_initcall(qe_init_gtm);

If this happens before the gtm_init_gtm(),

"If" isn't possible, order is guaranteed.

You use arch_initcall for both, so you're relying on link order. I think this at least merits a comment.

Quoted 2 lines

Quoted 1 line

then np->data will not be set.

It's a bug in the device tree or in the Linux code then.

Hmm? It's set by gtm_init_gtm(). If this code runs before gtm_init_gtm(), what are you expecting to initialize np->data?

What code exactly?

Quoted 1 line

Also, what if some arch_initcall runs between gtm_init_gtm and qe_init_gtm, that registers itself as a client of the gtm driver, and uses the wrong clock value?

Again, what code exactly? If it is a driver (for what this API is
created for), it hardly will run earlier than arch/ code. If this is
platform code (arch/powerpc/platform/), then it is hardly will run earlier than arch/sysdev/. Inside the arch/sysdev/ fsl_gtm.c is guaranteed to run earlier than qe_lib/gtm.c. So, where is the problem?

Since I'll implement clock-frequency inside the timer node, this isn't relevant anymore...

Ah. You need specific timer. No problem. I don't like idea of new arguments to the gtm_get_timer() function (complicates things), but we can just implement another one. gtm_get_timer_<name>, choice the name please. _specific, _2, _for, __gtm_get_timer, ...

How about:

struct gtm_timer *gtm_get_specific_timer(struct gtm *gtm, int timer,

                                         int width);

...with np->data used by the caller to figure out which gtm pointer to pass in.

arch/powerpc/sysdev/fsl_gtm.c line 188

Quoted 12 lines · Anton Vorontsov

arch/powerpc/sysdev/fsl_gtm.c new file +12 -0

+/**
+ * gtm_reset_utimer16 - reset 16 bits timer
+ * @tmr:	pointer to the gtm_timer structure obtained from gtm_get_timer
+ * @usec:	timer interval in microseconds
+ * @free_run:	free run flag
+ *
+ * This function (re)sets GTM timer so it counts up to the interval value and
+ * fires the interrupt when the value is reached. If free_run flag was set,
+ * timer will also reset itself upon reference value, otherwise it continues to
+ * increment.
+ */
+int gtm_reset_utimer16(struct gtm_timer *tmr, u16 usec, bool free_run)

A maximal timeout of ~65 ms is a little low... For use as a wakeup from sleep mode, I'd like to be able to request timeouts as large as the hardware allows.

Quoted 3 lines · Scott Wood

A maximal timeout of ~65 ms is a little low... For use as a wakeup from sleep mode, I'd like to be able to request timeouts as large as the hardware allows.

That is about precision. You just need to implement gtm_reset_stimer() is you want precision with a seconds, this will run a timer at 1 Hz.

Quoted 5 lines · Anton Vorontsov

Quoted 3 lines · Scott Wood

A maximal timeout of ~65 ms is a little low... For use as a wakeup from sleep mode, I'd like to be able to request timeouts as large as the hardware allows.

Quoted 2 lines

That is about precision. You just need to implement gtm_reset_stimer() is you want precision with a seconds, this will run a timer at 1 Hz.

Enh. I'm not crazy about having to call separately named functions, rather than have the timer code set the reference clock to the highest precision that has the needed range.

Heh. Scott, think about it. You have single 16bit timer with variable frequency. To use it, you'd better know what exactly precision you need.

Then you limited to u16 for the interval for this chosen precision.

Yes, you can implement this:

#define MAX_PRESCALER (256 * 256 * 16)

int gtm_reset_weird_behaving_utimer16(struct gtm_timer *tmr,
unsigned long long usec, bool free_run)

{
	int freq = 1000000;
	int min_hz2 = (tmr->gtm->freq / MAX_PRESCALER) << 1;

	while (!(freq & 1) && !(usec & 1) && freq >= min_hz2) {
		freq >>= 1;
		usec >>= 1;
	}

	if (usec > 0xffff)
		return -EINVAL;

	return gtm_reset_ref_timer16(tmr, freq, (u16)usec, free_run);
}

Quoted 2 lines · Anton Vorontsov

Heh. Scott, think about it. You have single 16bit timer with variable frequency. To use it, you'd better know what exactly precision you need.

Why? I know the timeout I need.

Quoted 9 lines

Then you limited to u16 for the interval for this chosen precision.

Yes, you can implement this:

#define MAX_PRESCALER (256 * 256 * 16)

int gtm_reset_weird_behaving_utimer16(struct gtm_timer *tmr,
unsigned long long usec, bool free_run)

Quoted 14 lines

{
	int freq = 1000000;
	int min_hz2 = (tmr->gtm->freq / MAX_PRESCALER) << 1;

	while (!(freq & 1) && !(usec & 1) && freq >= min_hz2) {
		freq >>= 1;
		usec >>= 1;
	}

	if (usec > 0xffff)
		return -EINVAL;

	return gtm_reset_ref_timer16(tmr, freq, (u16)usec, free_run);
}

Try something like this:

int gtm_reset_sane_behaving_timer(struct gtm_timer *tmr,
u64 usec, bool free_run)

{
	int freq = 1000000;
	int min_hz2 = (tmr->gtm->freq / MAX_PRESCALER) << 1;

	while (usec > 0xffff && freq >= min_hz2) {

		freq >>= 1;
		usec >>= 1;
	}

	if (usec > 0xffff)
		return -EINVAL;

	return gtm_reset_ref_timer16(tmr, freq, usec, free_run);
}

It could be made faster using cntlzw.

This isn't a timer with usec precision! This is a timer that silently crops precision as it wants to. Ahh, I see you dropped "u" prefix.

Well. I'm not going to use it anyway, so just give it some name you prefer and I'll wrap it into the patch. Preferably, drop a line here with kerneldoc for it, so I'll not have to document its drawbacks. :-)

Quoted 1 line

It could be made faster using cntlzw.

No need to cntlzw, there is fls() already.

Though, here you'll need two because of u64.

Btw, I hope you aware that single GTM timer running at 166MHz will give you 6 minutes of sleep, maximum.

With cascaded timer you'll get much better
result of 310 days. Is that possible to use cascaded timer as a wakeup event on 8313?

Quoted 2 lines · Anton Vorontsov

This isn't a timer with usec precision! This is a timer that silently crops precision as it wants to. Ahh, I see you dropped "u" prefix.

It is a timer with usec precision, unless you ask for a timeout of more than 65535 usec -- at which point the hardware can't provide usec precision.

And s/as it wants to/as it needs to/.

Quoted 3 lines

Well. I'm not going to use it anyway, so just give it some name you prefer and I'll wrap it into the patch. Preferably, drop a line here with kerneldoc for it, so I'll not have to document its drawbacks. :-)

/**
* gtm_reset_timer16 - reset 16 bit timer with arbitrary precision
* @tmr: pointer to the gtm_timer structure obtained from gtm_get_timer
* @usec: timer interval in microseconds
* @reload: if set, the timer will reset upon expiry rather than
* continue running free.
*
* This function (re)sets the GTM timer so that it counts up to the
* requested interval value, and fires the interrupt when the value is
* reached. This function will reduce the precision of the timer as
* needed in order for the requested timeout to fit in a 16-bit
* register.
*/
int gtm_reset_timer16(struct gtm_timer *tmr, unsigned long usec,
bool reload)

{
	...
}

Quoted 3 lines

Quoted 1 line

It could be made faster using cntlzw.

No need to cntlzw, there is fls() already.

fls() uses cntlzw, does it not? I was just too lazy to look up what Linux calls it. :-)

Quoted 1 line

Though, here you'll need two because of u64.

We can probably get away with 32 bits.

Quoted 2 lines

Btw, I hope you aware that single GTM timer running at 166MHz will give you 6 minutes of sleep, maximum.

Yes, but it's all we have on-chip that can do the job.

Quoted 3 lines

With cascaded timer you'll get much better
result of 310 days. Is that possible to use cascaded timer as a wakeup event on 8313?

No, unfortunately. Only timer4 can be a wakeup source, and when cascaded, timer4 is the input to timer3, rather than the other way around.

On Tue, Mar 18, 2008 at 03:48:12PM -0500, Scott Wood wrote:
[...]

Quoted 7 lines

How about:

struct gtm_timer *gtm_get_specific_timer(struct gtm *gtm, int timer,

                                         int width);

...with np->data used by the caller to figure out which gtm pointer to pass in.

Thanks for the comments, I've tried to address them all.

Updated patch below (not for applying, still waiting for further comments, if any).

- - - -
From: Anton Vorontsov <[email protected]>
Subject: [POWERPC] sysdev,qe_lib: implement FSL GTM support

GTM stands for General-purpose Timers Module and able to generate timer{1,2,3,4} interrupts.

There are several limitations in this support:
1. Cascaded (32 bit) timers unimplemented (1-2, 3-4).
This is straightforward to implement when needed, two timers should be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers unimplemented (1-2-3-4). This is also straightforward to implement when needed, all timers should be marked as "requested" and configured as appropriate.

Signed-off-by Anton Vorontsov <[email protected]>

---
 Documentation/powerpc/booting-without-of.txt |   32 +++-
 arch/powerpc/Kconfig                         |    5 +
 arch/powerpc/sysdev/Makefile                 |    1 +
 arch/powerpc/sysdev/fsl_gtm.c                |  322 ++++++++++++++++++++++++++
 include/asm-powerpc/fsl_gtm.h                |  106 +++++++++
 5 files changed, 465 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/sysdev/fsl_gtm.c
 create mode 100644 include/asm-powerpc/fsl_gtm.h

arch/powerpc/sysdev/fsl_gtm.c new file +26 -0

+/*
+ * This is back-end for the exported functions, it's used to reset single
+ * timer in reference mode.
+ */
+static int gtm_reset_ref_timer16(struct gtm_timer *tmr, int frequency,
+				 int reference_value, bool free_run)
+{
+	struct gtm *gtm = tmr->gtm;
+	int num = tmr - &gtm->timers[0];
+	unsigned int prescaler;
+	u8 iclk = GTMDR_ICLK_ICLK;
+	u8 psr;
+	u8 sps;
+	unsigned long flags;
+
+	prescaler = gtm->clock / frequency;
+	/*
+	 * We have two 8 bit prescalers -- primary and secondary (psr, sps),
+	 * plus "slow go" mode (clk / 16). So, total prescale value is
+	 * 16 * (psr + 1) * (sps + 1).
+	 */
+	if (prescaler > 256 * 256 * 16)
+		return -EINVAL;
+
+	if (prescaler > 256 * 256) {
+		iclk = GTMDR_ICLK_SLGO;

arch/powerpc/sysdev/fsl_gtm.c new file +25 -0

+	spin_lock_irqsave(&gtm->lock, flags);
+
+	/*
+	 * Properly reset timers: stop, reset, set up prescalers, reference
+	 * value and clear event register.
+	 */
+	clrsetbits_8(tmr->gtcfr, ~(GTCFR_STP(num) | GTCFR_RST(num)),
+				 GTCFR_STP(num) | GTCFR_RST(num));
+
+	setbits8(tmr->gtcfr, GTCFR_STP(num));
+
+	out_be16(tmr->gtpsr, psr);
+	clrsetbits_be16(tmr->gtmdr, 0xFFFF, iclk | GTMDR_SPS(sps) |
+			GTMDR_ORI | (free_run ? GTMDR_FFR : 0));
+	out_be16(tmr->gtcnr, 0);
+	out_be16(tmr->gtrfr, reference_value);
+	out_be16(tmr->gtevr, 0xFFFF);
+
+	/* Let it be. */
+	clrbits8(tmr->gtcfr, GTCFR_STP(num));
+
+	spin_unlock_irqrestore(&gtm->lock, flags);
+
+	return 0;
+}

Quoted 14 lines

arch/powerpc/sysdev/fsl_gtm.c new file +14 -0

+	/*
+	 * We have two 8 bit prescalers -- primary and secondary (psr, sps),
+	 * plus "slow go" mode (clk / 16). So, total prescale value is
+	 * 16 * (psr + 1) * (sps + 1).
+	 */
+	if (prescaler > 256 * 256 * 16)
+		return -EINVAL;
+
+	if (prescaler > 256 * 256) {
+		iclk = GTMDR_ICLK_SLGO;
+		prescaler /= 16;
+	}
+
+	if (prescaler > 256) {

arch/powerpc/sysdev/fsl_gtm.c line 149

Quoted 6 lines

arch/powerpc/sysdev/fsl_gtm.c new file +6 -0

+		psr = 256 - 1;
+		sps = prescaler / 256 - 1;
+	} else {
+		psr = prescaler - 1;
+		sps = 1 - 1;
+	}

Don't forget that the CPM2 doesn't support the primary prescaler.

Quoted 14 lines

(quoted diff) +14 -0

+	/*
+	 * We have two 8 bit prescalers -- primary and secondary (psr, sps),
+	 * plus "slow go" mode (clk / 16). So, total prescale value is
+	 * 16 * (psr + 1) * (sps + 1).
+	 */
+	if (prescaler > 256 * 256 * 16)
+		return -EINVAL;
+
+	if (prescaler > 256 * 256) {
+		iclk = GTMDR_ICLK_SLGO;
+		prescaler /= 16;
+	}
+
+	if (prescaler > 256) {

Review

Quoted 6 lines

(quoted diff) +6 -0

+		psr = 256 - 1;
+		sps = prescaler / 256 - 1;
+	} else {
+		psr = prescaler - 1;
+		sps = 1 - 1;
+	}

Don't forget that the CPM2 doesn't support the primary prescaler.

GTM stands for General-purpose Timers Module and able to generate timer{1,2,3,4} interrupts.

There are several limitations in this support:
1. Cascaded (32 bit) timers unimplemented (1-2, 3-4).
This is straightforward to implement when needed, two timers should be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers unimplemented (1-2-3-4). This is also straightforward to implement when needed, all timers should be marked as "requested" and configured as appropriate.

Signed-off-by Anton Vorontsov <[email protected]>

arch/powerpc/sysdev/fsl_gtm.c new file +4 -0

+
+	spin_unlock_irqrestore(&gtm->lock, flags);
+}
+EXPORT_SYMBOL(gtm_stop_timer_16);

Quoted 12 lines · Anton Vorontsov

GTM stands for General-purpose Timers Module and able to generate timer{1,2,3,4} interrupts.

There are several limitations in this support:
1. Cascaded (32 bit) timers unimplemented (1-2, 3-4).
This is straightforward to implement when needed, two timers should be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers unimplemented (1-2-3-4). This is also straightforward to implement when needed, all timers should be marked as "requested" and configured as appropriate.

Signed-off-by Anton Vorontsov <[email protected]>

[snip]

arch/powerpc/sysdev/fsl_gtm.c line 138

Quoted 9 lines

arch/powerpc/sysdev/fsl_gtm.c new file +9 -0

+void gtm_stop_timer_16(struct gtm_timer *tmr)
+{
+	struct gtm *gtm = tmr->gtm;
+	int num = tmr - &gtm->timers[0];
+	unsigned long flags;
+
+	spin_lock_irqsave(&gtm->lock, flags);
+
+	setbits8(tmr->gtcfr, GTCFR_STP(num));

Shouldn't we clear the timer events with

out_be16(tmr->gtevr, 0xFFFF);

here ? Otherwise the timer interrupt could still fire after the timer is stopped. This introduces a race condition in drivers that blindly re-arm the timer in the interrupt handler. I've been bitten by this while porting your FHCI USB driver to a CPM2 platform.

I believe QE USB clocks routing is qe_lib authority, so usb.c created. Also, now cmxgcr needs its own lock.

This patch also fixes QE_USB_RESTART_TX command definition.

Signed-off-by Anton Vorontsov <[email protected]>

---

arch/powerpc/sysdev/qe_lib/Kconfig  |    6 ++++
arch/powerpc/sysdev/qe_lib/Makefile |    1 +
arch/powerpc/sysdev/qe_lib/ucc.c    |    7 ++--
arch/powerpc/sysdev/qe_lib/usb.c    |   57 ++++++++++++++++++++++++++ 
+++++++++
include/asm-powerpc/qe.h            |   18 ++++++++++-
5 files changed, 85 insertions(+), 4 deletions(-)

create mode 100644 arch/powerpc/sysdev/qe_lib/usb.c

arch/powerpc/sysdev/qe_lib/Kconfig +6 -0

index c1f2849..f09dae4 100644
@@ -25,3 +25,9 @@ config QE_GTM
 	default y if FSL_GTM
 	help
 	  QE General-purpose Timers Module support
+
+config QE_USB
+	bool
+	default y if USB_FHCI_HCD
+	help
+	  QE USB Host Controller support

arch/powerpc/sysdev/qe_lib/Makefile +0 -0

index 3297a52..c666a59 100644
@@ -7,3 +7,4 @@ obj-$(CONFIG_UCC)	+= ucc.o

obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
obj-$(CONFIG_UCC_FAST) += ucc_fast.o
obj-$(CONFIG_QE_GTM) += gtm.o

arch/powerpc/sysdev/qe_lib/Makefile +1 -0

+obj-$(CONFIG_QE_USB)	+= usb.o

arch/powerpc/sysdev/qe_lib/ucc.c +4 -3

index 0e348d9..d3c7f5a 100644
@@ -26,7 +26,8 @@
 #include <asm/qe.h>
 #include <asm/ucc.h>
 
-static DEFINE_SPINLOCK(ucc_lock);
+DEFINE_SPINLOCK(cmxgcr_lock);
+EXPORT_SYMBOL(cmxgcr_lock);
 
 int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
 {

@@ -35,10 +36,10 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
 	if (ucc_num > UCC_MAX_NUM - 1)
 		return -EINVAL;
 
-	spin_lock_irqsave(&ucc_lock, flags);
+	spin_lock_irqsave(&cmxgcr_lock, flags);
 	clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
 		ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
-	spin_unlock_irqrestore(&ucc_lock, flags);
+	spin_unlock_irqrestore(&cmxgcr_lock, flags);
 
 	return 0;
 }

arch/powerpc/sysdev/qe_lib/usb.c new file +10 -0

new file mode 100644
index 0000000..60ce676
@@ -0,0 +1,57 @@
+/*
+ * QE USB routines
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ *               Shlomi Gridish <[email protected]>
+ *               Jerry Huang <[email protected]>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *               Anton Vorontsov <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or  

modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */

arch/powerpc/sysdev/qe_lib/usb.c new file +43 -0

+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+int qe_usb_clock_set(enum qe_clock clk, int rate)
+{
+	struct qe_mux __iomem *mux = &qe_immr->qmx;
+	unsigned long flags;
+	const bool is_brg = clk < QE_CLK1;
+	u32 val;
+
+	switch (clk) {
+	case QE_CLK3:  val = QE_CMXGCR_USBCS_CLK3;  break;
+	case QE_CLK5:  val = QE_CMXGCR_USBCS_CLK5;  break;
+	case QE_CLK7:  val = QE_CMXGCR_USBCS_CLK7;  break;
+	case QE_CLK9:  val = QE_CMXGCR_USBCS_CLK9;  break;
+	case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break;
+	case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break;
+	case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break;
+	case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break;
+	case QE_BRG9:  val = QE_CMXGCR_USBCS_BRG9;  break;
+	case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break;
+	default:
+		pr_err("%s: requested unknown clock %d\n", __func__, clk);
+		return -EINVAL;
+	}
+
+	if (is_brg)
+		qe_setbrg(clk, rate, 1);
+
+	spin_lock_irqsave(&cmxgcr_lock, flags);
+
+	clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
+
+	spin_unlock_irqrestore(&cmxgcr_lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(qe_usb_clock_set);

include/asm-powerpc/qe.h +6 -0

index c3be6e2..3276b06 100644
@@ -16,6 +16,7 @@
 #define _ASM_POWERPC_QE_H
 #ifdef __KERNEL__
 
+#include <linux/spinlock.h>
 #include <asm/immap_qe.h>
 
 #define QE_NUM_OF_SNUM	28

@@ -74,6 +75,8 @@ enum qe_clock {
 	QE_CLK_DUMMY
 };
 
+extern spinlock_t cmxgcr_lock;
+
 /* Export QE common operations */
 extern void qe_reset(void);
 extern int par_io_init(struct device_node *np);

@@ -156,6 +159,9 @@ int qe_upload_firmware(const struct qe_firmware  
 *firmware);
 /* Obtain information on the uploaded firmware */
 struct qe_firmware_info *qe_get_firmware_info(void);
 
+/* QE USB */
+int qe_usb_clock_set(enum qe_clock clk, int rate);
+
 /* Buffer descriptors */
 struct qe_bd {

	__be16 status;

include/asm-powerpc/qe.h +11 -1

@@ -254,6 +260,16 @@ enum comm_dir {
 #define QE_CMXGCR_MII_ENET_MNG		0x00007000
 #define QE_CMXGCR_MII_ENET_MNG_SHIFT	12
 #define QE_CMXGCR_USBCS			0x0000000f
+#define QE_CMXGCR_USBCS_CLK3		0x1
+#define QE_CMXGCR_USBCS_CLK5		0x2
+#define QE_CMXGCR_USBCS_CLK7		0x3
+#define QE_CMXGCR_USBCS_CLK9		0x4
+#define QE_CMXGCR_USBCS_CLK13		0x5
+#define QE_CMXGCR_USBCS_CLK17		0x6
+#define QE_CMXGCR_USBCS_CLK19		0x7
+#define QE_CMXGCR_USBCS_CLK21		0x8
+#define QE_CMXGCR_USBCS_BRG9		0x9
+#define QE_CMXGCR_USBCS_BRG10		0xa
 
 /* QE CECR Commands.
 */

@@ -283,7 +299,7 @@ enum comm_dir {
 #define QE_HPAC_START_TX		0x0000060b
 #define QE_HPAC_START_RX		0x0000070b
 #define QE_USB_STOP_TX			0x0000000a
-#define QE_USB_RESTART_TX		0x0000000b
+#define QE_USB_RESTART_TX		0x0000000c
 #define QE_QMC_STOP_TX			0x0000000c
 #define QE_QMC_STOP_RX			0x0000000d
 #define QE_SS7_SU_FIL_RESET		0x0000000e

Signature · 6 lines

1.5.2.2

_______________________________________________
Linuxppc-dev mailing list
[email protected]
https://ozlabs.org/mailman/listinfo/linuxppc-dev

Signed-off-by Anton Vorontsov <[email protected]>

---
arch/powerpc/sysdev/qe_lib/qe_io.c | 5 +++--

1 files changed, 3 insertions(+), 2 deletions(-)

Hi all,

Please consider these patches for the 2.6.26.

Quoted 3 lines · Anton Vorontsov

Hi all,

Please consider these patches for the 2.6.26.

I've applied most of these patches to my powerpc-next branch.

The
following two patches have NOT been applied:

[POWERPC] sysdev,qe_lib: implement FSL GTM support [POWERPC] qe_lib: add support for QE USB

It seemed there was rework required to the sysdev,qe_lib patch.