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Few MPC8360E-RDK related patches

PATCH New Anton Vorontsov 2 participants 13 messages Mar 24, 2008 – Mar 25, 2008

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Anton Vorontsov

author
#0 lore raw

cover Few MPC8360E-RDK related patches

This are few fixes and enhancements I have sitting in my rdk branch for a while now...

Signature · 3 lines
Anton Vorontsov
email: cboumailru at gmail.com
irc://irc.freenode.net/bd2
author
#1 lore raw

PATCH 1/11 uec: add support for gbit mii status readings

Signed-off-by Anton Vorontsov <[email protected]>
---
 drivers/qe/uec_phy.c |   28 +++++++++++++++++++---------
 drivers/qe/uec_phy.h |    5 +++++
 2 files changed, 24 insertions(+), 9 deletions(-)
drivers/qe/uec_phy.c +19 -9
index a42701c..8c4a558 100644
@@ -318,16 +318,26 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
 		return err;
 
 	if (mii_info->autoneg) {
-		status = phy_read (mii_info, PHY_ANLPAR);
+		status = phy_read(mii_info, MII_1000BASETSTATUS);
 
-		if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
-			mii_info->duplex = DUPLEX_FULL;
-		else
-			mii_info->duplex = DUPLEX_HALF;
-		if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
-			mii_info->speed = SPEED_100;
-		else
-			mii_info->speed = SPEED_10;
+		if (status & (LPA_1000FULL | LPA_1000HALF)) {
+			mii_info->speed = SPEED_1000;
+			if (status & LPA_1000FULL)
+				mii_info->duplex = DUPLEX_FULL;
+			else
+				mii_info->duplex = DUPLEX_HALF;
+		} else {
+			status = phy_read(mii_info, PHY_ANLPAR);
+
+			if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+				mii_info->duplex = DUPLEX_FULL;
+			else
+				mii_info->duplex = DUPLEX_HALF;
+			if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+				mii_info->speed = SPEED_100;
+			else
+				mii_info->speed = SPEED_10;
+		}
 		mii_info->pause = 0;
 	}
 	/* On non-aneg, we assume what we put in BMCR is the speed,
drivers/qe/uec_phy.h +5 -0
index e59a940..6f769fb 100644
@@ -29,6 +29,11 @@
 #define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
 #define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100
 
+/* 1000BT status */
+#define MII_1000BASETSTATUS	0x0a
+#define LPA_1000FULL		0x0400
+#define LPA_1000HALF		0x0200
+
 /* Cicada Extended Control Register 1 */
 #define MII_CIS8201_EXT_CON1	    0x17
 #define MII_CIS8201_EXTCON1_INIT    0x0000
Signature · 1 line
1.5.2.2
#2 lore raw

PATCH 1/11 uec: add support for gbit mii status readings

Quoted 5 lines · On Mon, 24 Mar 2008 20:46:24 +0300 Anton Vorontsov <[email protected]>…
Signed-off-by Anton Vorontsov <[email protected]>
---
 drivers/qe/uec_phy.c |   28 +++++++++++++++++++---------
 drivers/qe/uec_phy.h |    5 +++++
 2 files changed, 24 insertions(+), 9 deletions(-)

applied 1-11.

Thanks,

Kim

author
#3 lore raw

PATCH 2/11 uec: add support for RGMII_RXID interface mode

In reply to Anton Vorontsov

PHY drivers will use it to setup software delay between RXD and RXC signals.

Signed-off-by Anton Vorontsov <[email protected]>
---
 drivers/qe/uec.c |    1 +
 drivers/qe/uec.h |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)
drivers/qe/uec.c +1 -0
index 55f37cb..d34430c 100644
@@ -417,6 +417,7 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 			upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 			break;
+		case ENET_1000_RGMII_RXID:
 		case ENET_1000_RGMII:
 			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 			upsmr |= UPSMR_RPM;
drivers/qe/uec.h +1 -0
index c384055..7762de6 100644
@@ -642,6 +642,7 @@ typedef enum enet_interface {
 	ENET_100_RGMII,
 	ENET_1000_GMII,
 	ENET_1000_RGMII,
+	ENET_1000_RGMII_RXID,
 	ENET_1000_TBI,
 	ENET_1000_RTBI
 } enet_interface_e;
Signature · 1 line
1.5.2.2
author
#4 lore raw

PATCH 3/11 uec: add support for Broadcom BCM5481 Gigabit PHY

In reply to Anton Vorontsov

This patch adds basic support for Broadcom BCM5481 PHY.

RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is Peter Barada <[email protected]>.

Signed-off-by Anton Vorontsov <[email protected]>
---
 drivers/qe/uec_phy.c |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)
drivers/qe/uec_phy.c +41 -0
index 8c4a558..423ba78 100644
@@ -347,6 +347,37 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
 	return 0;
 }
 
+static int bcm_init(struct uec_mii_info *mii_info)
+{
+	struct eth_device *edev = mii_info->dev;
+	uec_private_t *uec = edev->priv;
+
+	gbit_config_aneg(mii_info);
+
+	if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) {
+		u16 val;
+		int cnt = 50;
+
+		/* Wait for aneg to complete. */
+		do
+			val = phy_read(mii_info, PHY_BMSR);
+		while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
+
+		/* Set RDX clk delay. */
+		phy_write(mii_info, 0x18, 0x7 | (7 << 12));
+
+		val = phy_read(mii_info, 0x18);
+		/* Set RDX-RXC skew. */
+		val |= (1 << 8);
+		val |= (7 | (7 << 12));
+		/* Write bits 14:0. */
+		val |= (1 << 15);
+		phy_write(mii_info, 0x18, val);
+	}
+
+	 return 0;
+}
+
 static int marvell_read_status (struct uec_mii_info *mii_info)
 {
 	u16 status;

@@ -515,6 +546,15 @@ static struct phy_info phy_info_marvell = {
 	.config_intr = &marvell_config_intr,
 };
 
+static struct phy_info phy_info_bcm5481 = {
+	.phy_id = 0x0143bca0,
+	.phy_id_mask = 0xffffff0,
+	.name = "Broadcom 5481",
+	.features = MII_GBIT_FEATURES,
+	.read_status = genmii_read_status,
+	.init = bcm_init,
+};
+
 static struct phy_info phy_info_genmii = {
 	.phy_id = 0x00000000,
 	.phy_id_mask = 0x00000000,

@@ -528,6 +568,7 @@ static struct phy_info *phy_info[] = {
 	&phy_info_dm9161,
 	&phy_info_dm9161a,
 	&phy_info_marvell,
+	&phy_info_bcm5481,
 	&phy_info_genmii,
 	NULL
 };
Signature · 1 line
1.5.2.2
author
#5 lore raw

PATCH 4/11 mpc83xx: MPC8360E-RDK: use RGMII_RXID interface mode

In reply to Anton Vorontsov

This is needed for BCM PHYs to work on this board.

Signed-off-by Anton Vorontsov <[email protected]>
---
 include/configs/MPC8360ERDK.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
include/configs/MPC8360ERDK.h +2 -2
index 27b037a..1588610 100644
@@ -290,7 +290,7 @@
 #define CFG_UEC1_TX_CLK		QE_CLK9
 #define CFG_UEC1_ETH_TYPE	GIGA_ETH
 #define CFG_UEC1_PHY_ADDR	2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */

@@ -301,7 +301,7 @@
 #define CFG_UEC2_TX_CLK		QE_CLK4
 #define CFG_UEC2_ETH_TYPE	GIGA_ETH
 #define CFG_UEC2_PHY_ADDR	4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 /*
Signature · 1 line
1.5.2.2
author
#6 lore raw

PATCH 5/11 mpc83xx: MPC8360E-RDK: add support for NAND

In reply to Anton Vorontsov
Signed-off-by Anton Vorontsov <[email protected]>
---
 board/freescale/mpc8360erdk/Makefile |    4 +-
 board/freescale/mpc8360erdk/nand.c   |   72 ++++++++++++++++++++++++++++++++++
 include/configs/MPC8360ERDK.h        |   24 +++++++++++
 3 files changed, 99 insertions(+), 1 deletions(-)
 create mode 100644 board/freescale/mpc8360erdk/nand.c
board/freescale/mpc8360erdk/Makefile +3 -1
index acc9544..53e0c48 100644
@@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
+COBJS-y += $(BOARD).o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
board/freescale/mpc8360erdk/nand.c new file +72 -0

72 lines not on this page · raw message

include/configs/MPC8360ERDK.h +24 -0
index 1588610..97797cc 100644
@@ -184,6 +184,11 @@
  * NAND flash on the local bus
  */
 #define CFG_NAND_BASE		0x60000000
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_UPM	1
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
 #define CFG_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */

@@ -503,23 +508,42 @@
    "fdtfile=dtb\0"\
    "fsfile=fs\0"\
    "ubootfile=u-boot.bin\0"\
+   "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
    "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
    		"$mtdparts panic=1\0"\
    "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
    "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
    		"$gatewayip:$netmask:$hostname:$netdev:off "\
    		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
+   "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
+   		"rootfstype=jffs2 rw\0"\
    "tftp_get_uboot=tftp 100000 $ubootfile\0"\
    "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
    "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
    "tftp_get_fs=tftp c00000 $fsfile\0"\
+   "nand_erase_kernel=nand erase 0 400000\0"\
+   "nand_erase_dtb=nand erase 400000 20000\0"\
+   "nand_erase_fs=nand erase 420000 3be0000\0"\
+   "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
+   "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
+   "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
+   "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
+   "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
    "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
    		"cp.b 100000 ff800000 $filesize\0"\
+   "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
+   		"nand_write_kernel\0"\
+   "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
+   "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
+   "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
+   		"nand_reflash_fs\0"\
    "boot_m=bootm $loadaddr - $fdtaddr\0"\
    "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
    		"boot_m\0"\
    "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
    		"boot_m\0"\
+   "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
+   		"boot_m\0"\
    ""
 
 #define CONFIG_BOOTCOMMAND "run dhcpboot"
Signature · 1 line
1.5.2.2
author
#7 lore raw

PATCH 6/11 mpc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCI

In reply to Anton Vorontsov

This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen controller and FHCI (QE USB).

Signed-off-by Anton Vorontsov <[email protected]>
---
 board/freescale/mpc8360erdk/mpc8360erdk.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)
board/freescale/mpc8360erdk/mpc8360erdk.c +17 -0
index 8005a50..3bcdda7 100644
@@ -186,6 +186,23 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{1,  7, 1, 0, 0}, /* LVDS_BKLT_CTR */
 	{2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
 
+	/* AD7843 ADC/Touchscreen controller */
+	{4, 14, 1, 0, 0}, /* SPI_nCS0 */
+	{4, 28, 3, 0, 3}, /* SPI_MOSI */
+	{4, 29, 3, 0, 3}, /* SPI_MISO */
+	{4, 30, 3, 0, 3}, /* SPI_CLK */
+
+	/* Freescale QUICC Engine USB Host Controller (FHCI) */
+	{1,  2, 1, 0, 3}, /* USBOE */
+	{1,  3, 1, 0, 3}, /* USBTP */
+	{1,  8, 1, 0, 1}, /* USBTN */
+	{1,  9, 2, 1, 3}, /* USBRP */
+	{1, 10, 2, 0, 3}, /* USBRXD */
+	{1, 11, 2, 1, 3}, /* USBRN */
+	{2, 20, 2, 0, 1}, /* CLK21 */
+	{4, 20, 1, 0, 0}, /* SPEED */
+	{4, 21, 1, 0, 0}, /* SUSPND */
+
 	/* END of table */
 	{0,  0, 0, 0, QE_IOP_TAB_END},
 };
Signature · 1 line
1.5.2.2
author
#8 lore raw

PATCH 7/11 mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc

In reply to Anton Vorontsov

Current DDR setup easily causes memory corruption, this patch fixes it.

Also fix TIMING_CFG0_MRS_CYC definition.

Signed-off-by Anton Vorontsov <[email protected]>
---
 include/configs/MPC8360ERDK.h |   48 ++++++++++++++++++++++++++++++----------
 include/mpc83xx.h             |    3 +-
 2 files changed, 38 insertions(+), 13 deletions(-)
include/configs/MPC8360ERDK.h +36 -12
index 97797cc..ba25a59 100644
@@ -89,8 +89,8 @@
 
 #define CFG_83XX_DDR_USES_CS0
 
-#undef CONFIG_DDR_ECC		/* support DDR ECC function */
-#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+#define CONFIG_DDR_ECC		/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
 
 /*
  * DDRCDR - DDR Control Driver Register

@@ -104,20 +104,44 @@
  */
 #define CONFIG_DDR_II
 #define CFG_DDR_SIZE		256 /* MB */
-#define CFG_DDRCDR		0x80080001
 #define CFG_DDR_CS0_BNDS	0x0000000f
 #define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
-				 CSCONFIG_COL_BIT_10)
-#define CFG_DDR_TIMING_0	0x00330903
-#define CFG_DDR_TIMING_1	0x3835a322
-#define CFG_DDR_TIMING_2	0x00104909
-#define CFG_DDR_TIMING_3	0x00000000
-#define CFG_DDR_CLK_CNTL	0x02000000
+				 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
+#define CFG_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
+#define CFG_DDR_SDRAM_CFG2	0x00001000
+#define CFG_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CFG_DDR_INTERVAL	((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 #define CFG_DDR_MODE		0x47800432
 #define CFG_DDR_MODE2		0x8000c000
-#define CFG_DDR_INTERVAL	0x045b0100
-#define CFG_DDR_SDRAM_CFG	0x03000000
-#define CFG_DDR_SDRAM_CFG2	0x00001000
+
+#define CFG_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CFG_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_30) | \
+				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (10 << TIMING_CFG1_REFREC_SHIFT) | \
+				 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CFG_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (0 << TIMING_CFG2_CPO_SHIFT))
+
+#define CFG_DDR_TIMING_3	0x00000000
 
 /*
  * Memory test
include/mpc83xx.h +2 -1
index df052e3..20df166 100644
@@ -880,7 +880,7 @@
 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT	16
 #define TIMING_CFG0_ODT_PD_EXIT		0x00000F00
 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT	8
-#define TIMING_CFG0_MRS_CYC		0x00000F00
+#define TIMING_CFG0_MRS_CYC		0x0000000F
 #define TIMING_CFG0_MRS_CYC_SHIFT	0
 
 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1

@@ -903,6 +903,7 @@
 #define TIMING_CFG1_WRTORD_SHIFT	0
 #define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
 #define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30		0x00050000	/* CAS latency = 2.5 */
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
Signature · 1 line
1.5.2.2
author
#9 lore raw

PATCH 8/11 mpc83xx: MPC8360E-RDK: add dhcp command

In reply to Anton Vorontsov

Plus modify environment to use it and remove bootfile env variable, it is internal and CONFIG_BOOTFILE is used for these purposes.

Signed-off-by Anton Vorontsov <[email protected]>
---
 include/configs/MPC8360ERDK.h |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)
include/configs/MPC8360ERDK.h +2 -3
index ba25a59..2bf0a35 100644
@@ -369,6 +369,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI

@@ -528,7 +529,6 @@
    "consoledev=ttyS0\0"\
    "loadaddr=a00000\0"\
    "fdtaddr=900000\0"\
-   "bootfile=uImage\0"\
    "fdtfile=dtb\0"\
    "fsfile=fs\0"\
    "ubootfile=u-boot.bin\0"\

@@ -562,8 +562,7 @@
    "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
    		"nand_reflash_fs\0"\
    "boot_m=bootm $loadaddr - $fdtaddr\0"\
-   "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
-   		"boot_m\0"\
+   "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
    "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
    		"boot_m\0"\
    "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
Signature · 1 line
1.5.2.2
author
#10 lore raw

PATCH 9/11 mpc83xx: MPC8360E-RDK: define CONFIG_OF_STDOUT_VIA_ALIAS

In reply to Anton Vorontsov

This is needed to update /choosen/linux,stdout-path properly.

Signed-off-by Anton Vorontsov <[email protected]>
---
 include/configs/MPC8360ERDK.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
include/configs/MPC8360ERDK.h +1 -0
index 2bf0a35..1b66087 100644
@@ -259,6 +259,7 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS
 
 /* I2C */
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
Signature · 1 line
1.5.2.2
author
#11 lore raw

PATCH 10/11 mpc83xx: MPC8360E-RDK: use 33.3(3)MHz CLKIN/SYS_CLK

In reply to Anton Vorontsov

At least on the "33MHz Pilot" board crystal is actually 33.3MHz. This patch fixes "system time drifting" problem.

Signed-off-by Anton Vorontsov <[email protected]>
---
 include/configs/MPC8360ERDK.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
include/configs/MPC8360ERDK.h +2 -2
index 1b66087..c7136bf 100644
@@ -30,8 +30,8 @@
  * System Clock Setup
  */
 #ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_83XX_CLKIN		33000000
-#define CONFIG_SYS_CLK_FREQ		33000000
+#define CONFIG_83XX_CLKIN		33333333
+#define CONFIG_SYS_CLK_FREQ		33333333
 #define PCI_33M				1
 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_10X1
 #else
Signature · 1 line
1.5.2.2
author
#12 lore raw

PATCH 11/11 mpc83xx: add "fsl, soc" and "fsl, immr" compatible fixups

In reply to Anton Vorontsov

device_type = "soc" is being deprecated, newer device trees will use "fsl,soc" and/or "fsl,immr" for the soc nodes.

This patch also adds clock-frequency property for soc nodes (the same value as bus-frequency).

Signed-off-by Anton Vorontsov <[email protected]>
---
 cpu/mpc83xx/fdt.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
cpu/mpc83xx/fdt.c +8 -0
index 6f55932..e7be4ee 100644
@@ -49,6 +49,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		"clock-frequency", gd->core_clk, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,soc",
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,soc",
+		"clock-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,immr",
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,immr",
+		"clock-frequency", bd->bi_busfreq, 1);
 #ifdef CONFIG_QE
 	ft_qe_setup(blob);
 #endif
Signature · 1 line
1.5.2.2