Microblaze updates

index 1a116ea..becafc8 100644
@@ -66,10 +66,4 @@
 #define XILINX_SYSACE_MEM_WIDTH	16
 
 /* Ethernet controller is Ethernet_MAC */
-#define XPAR_XEMAC_NUM_INSTANCES	1
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
-#define XPAR_OPB_ETHERNET_0_BASEADDR	0x40c00000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0ffff
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST	1
+#define XILINX_EMACLITE_BASEADDR       0x40C00000

index a96c693..19b81fd 100644
@@ -55,10 +55,4 @@
 #define XILINX_SYSACE_MEM_WIDTH	16
 
 /* Ethernet controller is Ethernet_MAC */
-#define XPAR_XEMAC_NUM_INSTANCES	1
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
-#define XPAR_OPB_ETHERNET_0_BASEADDR	0x40c00000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0ffff
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST	1
+#define XILINX_EMACLITE_BASEADDR       0x40C00000

index b320438..6db1c1a 100644
@@ -41,8 +41,14 @@
 /*#define	CFG_RESET_ADDRESS	TEXT_BASE*/
 
 /* ethernet */
-#define CONFIG_EMACLITE		1
-#define XPAR_EMAC_0_DEVICE_ID	XPAR_OPB_ETHERNET_0_DEVICE_ID
+#ifdef XILINX_EMAC_BASEADDR
+#define CONFIG_XILINX_EMAC	1
+#else
+#ifdef XILINX_EMACLITE_BASEADDR
+#define CONFIG_XILINX_EMACLITE	1
+#endif
+#endif
+#undef ET_DEBUG
 
 /* gpio */
 #define	CFG_GPIO_0		1

index c9320c2..eef4f72 100644
@@ -36,10 +36,6 @@
 #define	CONFIG_BAUDRATE		XILINX_UART_BAUDRATE
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
-/* ethernet */
-#define CONFIG_EMAC	1
-#define XPAR_EMAC_0_DEVICE_ID	XPAR_XEMAC_NUM_INSTANCES
-
 /*
  * setting reset address
  *

@@ -51,6 +47,16 @@
  */
 /* #define	CFG_RESET_ADDRESS	0x36000000 */
 
+/* ethernet */
+#ifdef XILINX_EMAC_BASEADDR
+#define CONFIG_XILINX_EMAC	1
+#else
+#ifdef XILINX_EMACLITE_BASEADDR
+#define CONFIG_XILINX_EMACLITE	1
+#endif
+#endif
+#undef ET_DEBUG
+
 /* gpio */
 #ifdef XILINX_GPIO_BASEADDR
 #define	CFG_GPIO_0		1

new file mode 100644
index 0000000..9ba4096
@@ -0,0 +1,351 @@
+/******************************************************************************
+ *
+ * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+ * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+ * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+ * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+ * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+ * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+ * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+ * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+ * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+ * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+ * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE.
+ *
+ * (C) Copyright 2007-2008 Michal Simek
+ * Michal SIMEK <[email protected]>
+ *
+ * (c) Copyright 2003 Xilinx Inc.
+ * All rights reserved.
+ *
+ ******************************************************************************/
+
+#include <common.h>
+#include <net.h>
+#include <config.h>
+#include <asm/io.h>
+
+#undef DEBUG
+
+#define ENET_MAX_MTU		PKTSIZE
+#define ENET_MAX_MTU_ALIGNED	PKTSIZE_ALIGN
+#define ENET_ADDR_LENGTH	6
+
+/* EmacLite constants */
+#define XEL_BUFFER_OFFSET	0x0800	/* Next buffer's offset */
+#define XEL_TPLR_OFFSET		0x07F4	/* Tx packet length */
+#define XEL_TSR_OFFSET		0x07FC	/* Tx status */
+#define XEL_RSR_OFFSET		0x17FC	/* Rx status */
+#define XEL_RXBUFF_OFFSET	0x1000	/* Receive Buffer */
+
+/* Xmit complete */
+#define XEL_TSR_XMIT_BUSY_MASK		0x00000001UL
+/* Xmit interrupt enable bit */
+#define XEL_TSR_XMIT_IE_MASK		0x00000008UL
+/* Buffer is active, SW bit only */
+#define XEL_TSR_XMIT_ACTIVE_MASK	0x80000000UL
+/* Program the MAC address */
+#define XEL_TSR_PROGRAM_MASK		0x00000002UL
+/* define for programming the MAC address into the EMAC Lite */
+#define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
+
+/* Transmit packet length upper byte */
+#define XEL_TPLR_LENGTH_MASK_HI		0x0000FF00UL
+/* Transmit packet length lower byte */
+#define XEL_TPLR_LENGTH_MASK_LO		0x000000FFUL
+
+/* Recv complete */
+#define XEL_RSR_RECV_DONE_MASK		0x00000001UL
+/* Recv interrupt enable bit */
+#define XEL_RSR_RECV_IE_MASK		0x00000008UL
+
+typedef struct {
+	unsigned int baseaddress;	/* Base address for device (IPIF) */
+	unsigned int nexttxbuffertouse;	/* Next TX buffer to write to */
+	unsigned int nextrxbuffertouse;	/* Next RX buffer to read from */
+	unsigned char deviceid;		/* Unique ID of device - for future */
+} xemaclite;
+
+static xemaclite emaclite;
+
+static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
+
+/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
+#ifdef CFG_ENV_IS_NOWHERE
+static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+#else
+static u8 emacaddr[ENET_ADDR_LENGTH];
+#endif
+
+void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
+{
+	unsigned int i;
+	u32 alignbuffer;
+	u32 *to32ptr;
+	u32 *from32ptr;
+	u8 *to8ptr;
+	u8 *from8ptr;
+
+	from32ptr = (u32 *) srcptr;
+
+	/* Word aligned buffer, no correction needed. */
+	to32ptr = (u32 *) destptr;
+	while (bytecount > 3) {
+		*to32ptr++ = *from32ptr++;
+		bytecount -= 4;
+	}
+	to8ptr = (u8 *) to32ptr;
+
+	alignbuffer = *from32ptr++;
+	from8ptr = (u8 *) & alignbuffer;
+
+	for (i = 0; i < bytecount; i++) {
+		*to8ptr++ = *from8ptr++;
+	}
+}
+
+void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
+{
+	unsigned i;
+	u32 alignbuffer;
+	u32 *to32ptr = (u32 *) destptr;
+	u32 *from32ptr;
+	u8 *to8ptr;
+	u8 *from8ptr;
+
+	from32ptr = (u32 *) srcptr;
+	while (bytecount > 3) {
+
+		*to32ptr++ = *from32ptr++;
+		bytecount -= 4;
+	}
+
+	alignbuffer = 0;
+	to8ptr = (u8 *) & alignbuffer;
+	from8ptr = (u8 *) from32ptr;
+
+	for (i = 0; i < bytecount; i++) {
+		*to8ptr++ = *from8ptr++;
+	}
+
+	*to32ptr++ = alignbuffer;
+}
+
+void eth_halt (void)
+{
+	debug ("eth_halt\n");
+}
+
+int eth_init (bd_t * bis)
+{
+	debug ("EmacLite Initialization Started\n");
+	memset (&emaclite, 0, sizeof (xemaclite));
+	emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
+
+	if (!getenv("ethaddr")) {
+		memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
+	}
+
+/*
+ * TX - TX_PING & TX_PONG initialization
+ */
+	/* Restart PING TX */
+	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
+	/* Copy MAC address */
+	xemaclite_alignedwrite (bis->bi_enetaddr,
+		emaclite.baseaddress, ENET_ADDR_LENGTH);
+	/* Set the length */
+	out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+	/* Update the MAC address in the EMAC Lite */
+	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
+	/* Wait for EMAC Lite to finish with the MAC address update */
+	while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) &
+		XEL_TSR_PROG_MAC_ADDR) != 0) ;
+
+#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	/* The same operation with PONG TX */
+	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
+	xemaclite_alignedwrite (bis->bi_enetaddr, emaclite.baseaddress +
+		XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
+	out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
+	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
+		XEL_TSR_PROG_MAC_ADDR);
+	while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
+		XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
+#endif
+
+/*
+ * RX - RX_PING & RX_PONG initialization
+ */
+	/* Write out the value to flush the RX buffer */
+	out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
+#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+	out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
+		XEL_RSR_RECV_IE_MASK);
+#endif
+
+	debug ("EmacLite Initialization complete\n");
+	return 0;
+}
+
+int xemaclite_txbufferavailable (xemaclite * instanceptr)
+{
+	u32 reg;
+	u32 txpingbusy;
+	u32 txpongbusy;
+	/*
+	 * Read the other buffer register
+	 * and determine if the other buffer is available
+	 */
+	reg = in_be32 (instanceptr->baseaddress +
+			instanceptr->nexttxbuffertouse + 0);
+	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
+			XEL_TSR_XMIT_BUSY_MASK);
+
+	reg = in_be32 (instanceptr->baseaddress +
+			(instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
+	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
+			XEL_TSR_XMIT_BUSY_MASK);
+
+	return (!(txpingbusy && txpongbusy));
+}
+
+int eth_send (volatile void *ptr, int len) {
+
+	unsigned int reg;
+	unsigned int baseaddress;
+
+	unsigned maxtry = 1000;
+
+	if (len > ENET_MAX_MTU)
+		len = ENET_MAX_MTU;
+
+	while (!xemaclite_txbufferavailable (&emaclite) && maxtry) {
+		udelay (10);
+		maxtry--;
+	}
+
+	if (!maxtry) {
+		printf ("Error: Timeout waiting for ethernet TX buffer\n");
+		/* Restart PING TX */
+		out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
+#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+		out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
+		XEL_BUFFER_OFFSET, 0);
+#endif
+		return 0;
+	}
+
+	/* Determine the expected TX buffer address */
+	baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse);
+
+	/* Determine if the expected buffer address is empty */
+	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
+	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
+		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
+			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+
+#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+		emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
+#endif
+		debug ("Send packet from 0x%x\n", baseaddress);
+		/* Write the frame to the buffer */
+		xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
+		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
+			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
+		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
+		reg |= XEL_TSR_XMIT_BUSY_MASK;
+		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
+			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
+		}
+		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
+		return 1;
+	}
+#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	/* Switch to second buffer */
+	baseaddress ^= XEL_BUFFER_OFFSET;
+	/* Determine if the expected buffer address is empty */
+	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
+	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
+		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
+			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
+		debug ("Send packet from 0x%x\n", baseaddress);
+		/* Write the frame to the buffer */
+		xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
+		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
+			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
+		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
+		reg |= XEL_TSR_XMIT_BUSY_MASK;
+		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
+			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
+		}
+		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
+		return 1;
+	}
+#endif
+	puts ("Error while sending frame\n");
+	return 0;
+}
+
+int eth_rx (void)
+{
+	unsigned int length;
+	unsigned int reg;
+	unsigned int baseaddress;
+
+	baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
+	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
+	debug ("Testing data at address 0x%x\n", baseaddress);
+	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
+#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+		emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
+#endif
+	} else {
+#ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+		debug ("No data was available - address 0x%x\n", baseaddress);
+		return 0;
+#else
+		baseaddress ^= XEL_BUFFER_OFFSET;
+		reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
+		if ((reg & XEL_RSR_RECV_DONE_MASK) !=
+					XEL_RSR_RECV_DONE_MASK) {
+			debug ("No data was available - address 0x%x\n",
+					baseaddress);
+			return 0;
+		}
+#endif
+	}
+	/* Get the length of the frame that arrived */
+	switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
+			0xFFFF0000 ) >> 16) {
+		case 0x806:
+			length = 42 + 20; /* FIXME size of ARP */
+			debug ("ARP Packet\n");
+			break;
+		case 0x800:
+			length = 14 + 14 +
+			(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
+			0xFFFF0000) >> 16); /* FIXME size of IP packet */
+			debug ("IP Packet\n");
+			break;
+		default:
+			debug ("Other Packet\n");
+			length = ENET_MAX_MTU;
+			break;
+	}
+
+	xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
+			etherrxbuff, length);
+
+	/* Acknowledge the frame */
+	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
+	reg &= ~XEL_RSR_RECV_DONE_MASK;
+	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
+
+	debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
+	NetReceive ((uchar *) etherrxbuff, length);
+	return 1;
+
+}

new file mode 100644
index 0000000..c7f1a2a
@@ -0,0 +1,462 @@
+/******************************************************************************
+ *
+ * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+ * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+ * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+ * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+ * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+ * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+ * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+ * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+ * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+ * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+ * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+ * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE.
+ *
+ * (C) Copyright 2007-2008 Michal Simek
+ * Michal SIMEK <[email protected]>
+ *
+ * (c) Copyright 2003 Xilinx Inc.
+ * All rights reserved.
+ *
+ ******************************************************************************/
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <asm/io.h>
+
+#include <asm/asm.h>
+
+#undef DEBUG
+
+typedef struct {
+	u32 regbaseaddress;	/* Base address of registers */
+	u32 databaseaddress;	/* Base address of data for FIFOs */
+} xpacketfifov100b;
+
+typedef struct {
+	u32 baseaddress;	/* Base address (of IPIF) */
+	u32 isstarted;		/* Device is currently started 0-no, 1-yes */
+	xpacketfifov100b recvfifo;	/* FIFO used to receive frames */
+	xpacketfifov100b sendfifo;	/* FIFO used to send frames */
+} xemac;
+
+#define XIIF_V123B_IISR_OFFSET	32UL /* IP interrupt status register */
+#define XIIF_V123B_RESET_MASK		0xAUL
+#define XIIF_V123B_RESETR_OFFSET	64UL /* reset register */
+
+/* This constant is used with the Reset Register */
+#define XPF_RESET_FIFO_MASK		0x0000000A
+#define XPF_COUNT_STATUS_REG_OFFSET	4UL
+
+/* These constants are used with the Occupancy/Vacancy Count Register. This
+ * register also contains FIFO status */
+#define XPF_COUNT_MASK			0x0000FFFF
+#define XPF_DEADLOCK_MASK		0x20000000
+
+/* Offset of the MAC registers from the IPIF base address */
+#define XEM_REG_OFFSET		0x1100UL
+
+/*
+ * Register offsets for the Ethernet MAC. Each register is 32 bits.
+ */
+#define XEM_ECR_OFFSET	(XEM_REG_OFFSET + 0x4)	/* MAC Control */
+#define XEM_SAH_OFFSET	(XEM_REG_OFFSET + 0xC)	/* Station addr, high */
+#define XEM_SAL_OFFSET	(XEM_REG_OFFSET + 0x10)	/* Station addr, low */
+#define XEM_RPLR_OFFSET	(XEM_REG_OFFSET + 0x1C)	/* Rx packet length */
+#define XEM_TPLR_OFFSET	(XEM_REG_OFFSET + 0x20)	/* Tx packet length */
+#define XEM_TSR_OFFSET	(XEM_REG_OFFSET + 0x24)	/* Tx status */
+
+#define XEM_PFIFO_OFFSET	0x2000UL
+/* Tx registers */
+#define XEM_PFIFO_TXREG_OFFSET	(XEM_PFIFO_OFFSET + 0x0)
+/* Rx registers */
+#define XEM_PFIFO_RXREG_OFFSET	(XEM_PFIFO_OFFSET + 0x10)
+/* Tx keyhole */
+#define XEM_PFIFO_TXDATA_OFFSET	(XEM_PFIFO_OFFSET + 0x100)
+/* Rx keyhole */
+#define XEM_PFIFO_RXDATA_OFFSET	(XEM_PFIFO_OFFSET + 0x200)
+
+/*
+ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
+ * part of the IPIF IP Interrupt registers
+ */
+/* A mask for all transmit interrupts, used in polled mode */
+#define XEM_EIR_XMIT_ALL_MASK	(XEM_EIR_XMIT_DONE_MASK |\
+				XEM_EIR_XMIT_ERROR_MASK | \
+				XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
+				XEM_EIR_XMIT_LFIFO_FULL_MASK)
+
+/* Xmit complete */
+#define XEM_EIR_XMIT_DONE_MASK		0x00000001UL
+/* Recv complete */
+#define XEM_EIR_RECV_DONE_MASK		0x00000002UL
+/* Xmit error */
+#define XEM_EIR_XMIT_ERROR_MASK		0x00000004UL
+/* Recv error */
+#define XEM_EIR_RECV_ERROR_MASK		0x00000008UL
+/* Xmit status fifo empty */
+#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK	0x00000010UL
+/* Recv length fifo empty */
+#define XEM_EIR_RECV_LFIFO_EMPTY_MASK	0x00000020UL
+/* Xmit length fifo full */
+#define XEM_EIR_XMIT_LFIFO_FULL_MASK	0x00000040UL
+/* Recv length fifo overrun */
+#define XEM_EIR_RECV_LFIFO_OVER_MASK	0x00000080UL
+/* Recv length fifo underrun */
+#define XEM_EIR_RECV_LFIFO_UNDER_MASK	0x00000100UL
+/* Xmit status fifo overrun */
+#define XEM_EIR_XMIT_SFIFO_OVER_MASK	0x00000200UL
+/* Transmit status fifo underrun */
+#define XEM_EIR_XMIT_SFIFO_UNDER_MASK	0x00000400UL
+/* Transmit length fifo overrun */
+#define XEM_EIR_XMIT_LFIFO_OVER_MASK	0x00000800UL
+/* Transmit length fifo underrun */
+#define XEM_EIR_XMIT_LFIFO_UNDER_MASK	0x00001000UL
+/* Transmit pause pkt received */
+#define XEM_EIR_XMIT_PAUSE_MASK		0x00002000UL
+
+/*
+ * EMAC Control Register (ECR)
+ */
+/* Full duplex mode */
+#define XEM_ECR_FULL_DUPLEX_MASK	0x80000000UL
+/* Reset transmitter */
+#define XEM_ECR_XMIT_RESET_MASK		0x40000000UL
+/* Enable transmitter */
+#define XEM_ECR_XMIT_ENABLE_MASK	0x20000000UL
+/* Reset receiver */
+#define XEM_ECR_RECV_RESET_MASK		0x10000000UL
+/* Enable receiver */
+#define XEM_ECR_RECV_ENABLE_MASK	0x08000000UL
+/* Enable PHY */
+#define XEM_ECR_PHY_ENABLE_MASK		0x04000000UL
+/* Enable xmit pad insert */
+#define XEM_ECR_XMIT_PAD_ENABLE_MASK	0x02000000UL
+/* Enable xmit FCS insert */
+#define XEM_ECR_XMIT_FCS_ENABLE_MASK	0x01000000UL
+/* Enable unicast addr */
+#define XEM_ECR_UNICAST_ENABLE_MASK	0x00020000UL
+/* Enable broadcast addr */
+#define XEM_ECR_BROAD_ENABLE_MASK	0x00008000UL
+
+/*
+ * Transmit Status Register (TSR)
+ */
+/* Transmit excess deferral */
+#define XEM_TSR_EXCESS_DEFERRAL_MASK	0x80000000UL
+/* Transmit late collision */
+#define XEM_TSR_LATE_COLLISION_MASK	0x01000000UL
+
+#define ENET_MAX_MTU		PKTSIZE
+#define ENET_ADDR_LENGTH	6
+
+static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
+
+static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+
+static xemac emac;
+
+void eth_halt(void)
+{
+	debug ("eth_halt\n");
+}
+
+int eth_init(bd_t * bis)
+{
+	u32 helpreg;
+	debug ("EMAC Initialization Started\n\r");
+
+	if (emac.isstarted) {
+		puts("Emac is started\n");
+		return 0;
+	}
+
+	memset (&emac, 0, sizeof (xemac));
+
+	emac.baseaddress = XILINX_EMAC_BASEADDR;
+
+	/* Setting up FIFOs */
+	emac.recvfifo.regbaseaddress = emac.baseaddress +
+					XEM_PFIFO_RXREG_OFFSET;
+	emac.recvfifo.databaseaddress = emac.baseaddress +
+					XEM_PFIFO_RXDATA_OFFSET;
+	out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
+
+	emac.sendfifo.regbaseaddress = emac.baseaddress +
+					XEM_PFIFO_TXREG_OFFSET;
+	emac.sendfifo.databaseaddress = emac.baseaddress +
+					XEM_PFIFO_TXDATA_OFFSET;
+	out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
+
+	/* Reset the entire IPIF */
+	out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
+					XIIF_V123B_RESET_MASK);
+
+	/* Stopping EMAC for setting up MAC */
+	helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
+	helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+	out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
+
+	if (!getenv("ethaddr")) {
+		memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
+	}
+
+	/* Set the device station address high and low registers */
+	helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
+	out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
+	helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
+			(bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
+	out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
+
+	helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
+		XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
+		XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
+	out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
+
+	emac.isstarted = 1;
+
+	/* Enable the transmitter, and receiver */
+	helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
+	helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
+	helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+	out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
+
+	printf("EMAC Initialization complete\n\r");
+	return 0;
+}
+
+int eth_send(volatile void *ptr, int len)
+{
+	u32 intrstatus;
+	u32 xmitstatus;
+	u32 fifocount;
+	u32 wordcount;
+	u32 extrabytecount;
+	u32 *wordbuffer = (u32 *) ptr;
+
+	if (len > ENET_MAX_MTU)
+		len = ENET_MAX_MTU;
+
+	/*
+	 * Check for overruns and underruns for the transmit status and length
+	 * FIFOs and make sure the send packet FIFO is not deadlocked.
+	 * Any of these conditions is bad enough that we do not want to
+	 * continue. The upper layer software should reset the device to resolve
+	 * the error.
+	 */
+	intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+	if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+			XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		debug ("Transmitting overrun error\n");
+		return 0;
+	} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+			XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		debug ("Transmitting underrun error\n");
+		return 0;
+	} else if (in_be32 (emac.sendfifo.regbaseaddress +
+			XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
+		debug ("Transmitting fifo error\n");
+		return 0;
+	}
+
+	/*
+	 * Before writing to the data FIFO, make sure the length FIFO is not
+	 * full. The data FIFO might not be full yet even though the length FIFO
+	 * is. This avoids an overrun condition on the length FIFO and keeps the
+	 * FIFOs in sync.
+	 *
+	 * Clear the latched LFIFO_FULL bit so next time around the most
+	 * current status is represented
+	 */
+	if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
+		out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+			intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
+		debug ("Fifo is full\n");
+		return 0;
+	}
+
+	/* get the count of how many words may be inserted into the FIFO */
+	fifocount = in_be32 (emac.sendfifo.regbaseaddress +
+				XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+	wordcount = len >> 2;
+	extrabytecount = len & 0x3;
+
+	if (fifocount < wordcount) {
+		debug ("Sending packet is larger then size of FIFO\n");
+		return 0;
+	}
+
+	for (fifocount = 0; fifocount < wordcount; fifocount++) {
+		out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);
+	}
+	if (extrabytecount > 0) {
+		u32 lastword = 0;
+		u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
+
+		if (extrabytecount == 1) {
+			lastword = extrabytesbuffer[0] << 24;
+		} else if (extrabytecount == 2) {
+			lastword = extrabytesbuffer[0] << 24 |
+				extrabytesbuffer[1] << 16;
+		} else if (extrabytecount == 3) {
+			lastword = extrabytesbuffer[0] << 24 |
+				extrabytesbuffer[1] << 16 |
+				extrabytesbuffer[2] << 8;
+		}
+		out_be32 (emac.sendfifo.databaseaddress, lastword);
+	}
+
+	/* Loop on the MAC's status to wait for any pause to complete */
+	intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+	while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
+		intrstatus = in_be32 ((emac.baseaddress) +
+					XIIF_V123B_IISR_OFFSET);
+		/* Clear the pause status from the transmit status register */
+		out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+				intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
+	}
+
+	/*
+	 * Set the MAC's transmit packet length register to tell it to transmit
+	 */
+	out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
+
+	/*
+	 * Loop on the MAC's status to wait for the transmit to complete.
+	 * The transmit status is in the FIFO when the XMIT_DONE bit is set.
+	 */
+	do {
+		intrstatus = in_be32 ((emac.baseaddress) +
+						XIIF_V123B_IISR_OFFSET);
+	}
+	while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
+
+	xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
+
+	if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+					XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		debug ("Transmitting overrun error\n");
+		return 0;
+	} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+					XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		debug ("Transmitting underrun error\n");
+		return 0;
+	}
+
+	/* Clear the interrupt status register of transmit statuses */
+	out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+				intrstatus & XEM_EIR_XMIT_ALL_MASK);
+
+	/*
+	 * Collision errors are stored in the transmit status register
+	 * instead of the interrupt status register
+	 */
+	if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
+				(xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
+		debug ("Transmitting collision error\n");
+		return 0;
+	}
+	return 1;
+}
+
+int eth_rx(void)
+{
+	u32 pktlength;
+	u32 intrstatus;
+	u32 fifocount;
+	u32 wordcount;
+	u32 extrabytecount;
+	u32 lastword;
+	u8 *extrabytesbuffer;
+
+	if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)
+			& XPF_DEADLOCK_MASK) {
+		out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
+		debug ("Receiving FIFO deadlock\n");
+		return 0;
+	}
+
+	/*
+	 * Get the interrupt status to know what happened (whether an error
+	 * occurred and/or whether frames have been received successfully).
+	 * When clearing the intr status register, clear only statuses that
+	 * pertain to receive.
+	 */
+	intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+	/*
+	 * Before reading from the length FIFO, make sure the length FIFO is not
+	 * empty. We could cause an underrun error if we try to read from an
+	 * empty FIFO.
+	 */
+	if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
+		/* debug ("Receiving FIFO is empty\n"); */
+		return 0;
+	}
+
+	/*
+	 * Determine, from the MAC, the length of the next packet available
+	 * in the data FIFO (there should be a non-zero length here)
+	 */
+	pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
+	if (!pktlength) {
+		return 0;
+	}
+
+	/*
+	 * Write the RECV_DONE bit in the status register to clear it. This bit
+	 * indicates the RPLR is non-empty, and we know it's set@this point.
+	 * We clear it so that subsequent entry into this routine will reflect
+	 * the current status. This is done because the non-empty bit is latched
+	 * in the IPIF, which means it may indicate a non-empty condition even
+	 * though there is something in the FIFO.
+	 */
+	out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+						XEM_EIR_RECV_DONE_MASK);
+
+	fifocount = in_be32 (emac.recvfifo.regbaseaddress +
+				XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+
+	if ((fifocount * 4) < pktlength) {
+		debug ("Receiving FIFO is smaller than packet size.\n");
+		return 0;
+	}
+
+	wordcount = pktlength >> 2;
+	extrabytecount = pktlength & 0x3;
+
+	for (fifocount = 0; fifocount < wordcount; fifocount++) {
+		etherrxbuff[fifocount] =
+				in_be32 (emac.recvfifo.databaseaddress);
+	}
+
+	/*
+	 * if there are extra bytes to handle, read the last word from the FIFO
+	 * and insert the extra bytes into the buffer
+	 */
+	if (extrabytecount > 0) {
+		extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
+
+		lastword = in_be32 (emac.recvfifo.databaseaddress);
+
+		/*
+		 * one extra byte in the last word, put the byte into the next
+		 * location of the buffer, bytes in a word of the FIFO are
+		 * ordered from most significant byte to least
+		 */
+		if (extrabytecount == 1) {
+			extrabytesbuffer[0] = (u8) (lastword >> 24);
+		} else if (extrabytecount == 2) {
+			extrabytesbuffer[0] = (u8) (lastword >> 24);
+			extrabytesbuffer[1] = (u8) (lastword >> 16);
+		} else if (extrabytecount == 3) {
+			extrabytesbuffer[0] = (u8) (lastword >> 24);
+			extrabytesbuffer[1] = (u8) (lastword >> 16);
+			extrabytesbuffer[2] = (u8) (lastword >> 8);
+		}
+	}
+	NetReceive((uchar *)etherrxbuff, pktlength);
+	return 1;
+}

index becafc8..d805061 100644
@@ -41,8 +41,8 @@
 #define XILINX_TIMER_IRQ	0
 
 /* Uart pheriphery is RS232_Uart */
-#define XILINX_UART_BASEADDR	0x40600000
-#define XILINX_UART_BAUDRATE	115200
+#define XILINX_UARTLITE_BASEADDR	0x40600000
+#define XILINX_UARTLITE_BAUDRATE	115200
 
 /* IIC pheriphery is IIC_EEPROM */
 #define XILINX_IIC_0_BASEADDR	0x40800000

index 19b81fd..9e5ebda 100644
@@ -37,8 +37,8 @@
 #define XILINX_TIMER_IRQ	1
 
 /* Uart pheriphery is RS232_Uart_1 */
-#define XILINX_UART_BASEADDR	0x40600000
-#define XILINX_UART_BAUDRATE	115200
+#define XILINX_UARTLITE_BASEADDR	0x40600000
+#define XILINX_UARTLITE_BAUDRATE	115200
 
 /* GPIO is LEDs_4Bit*/
 #define XILINX_GPIO_BASEADDR	0x40000000

index 6db1c1a..1a2cb0a 100644
@@ -32,10 +32,23 @@
 #define	CONFIG_ML401		1	/* ML401 Board */
 
 /* uart */
+#ifdef XILINX_UARTLITE_BASEADDR
 #define	CONFIG_XILINX_UARTLITE
-#define	CONFIG_SERIAL_BASE	XILINX_UART_BASEADDR
-#define	CONFIG_BAUDRATE		XILINX_UART_BAUDRATE
+#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
+#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+#else
+#ifdef XILINX_UART16550_BASEADDR
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	4
+#define CONFIG_CONS_INDEX	1
+#define CFG_NS16550_COM1	XILINX_UART16550_BASEADDR
+#define CFG_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
+#define	CONFIG_BAUDRATE		115200
+#define	CFG_BAUDRATE_TABLE	{ 9600, 115200 }
+#endif
+#endif
 
 /* setting reset address */
 /*#define	CFG_RESET_ADDRESS	TEXT_BASE*/

index eef4f72..f86b3b9 100644
@@ -31,10 +31,23 @@
 #define	CONFIG_XUPV2P		1
 
 /* uart */
+#ifdef XILINX_UARTLITE_BASEADDR
 #define	CONFIG_XILINX_UARTLITE
-#define	CONFIG_SERIAL_BASE	XILINX_UART_BASEADDR
-#define	CONFIG_BAUDRATE		XILINX_UART_BAUDRATE
+#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
+#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+#else
+#ifdef XILINX_UART16550_BASEADDR
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	4
+#define CONFIG_CONS_INDEX	1
+#define CFG_NS16550_COM1	XILINX_UART16550_BASEADDR
+#define CFG_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
+#define	CONFIG_BAUDRATE		115200
+#define	CFG_BAUDRATE_TABLE	{ 9600, 115200 }
+#endif
+#endif
 
 /*
  * setting reset address

index 1a2cb0a..b167cb2 100644
@@ -64,8 +64,10 @@
 #undef ET_DEBUG
 
 /* gpio */
+#ifdef XILINX_GPIO_BASEADDR
 #define	CFG_GPIO_0		1
 #define	CFG_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
+#endif
 
 /* interrupt controller */
 #define	CFG_INTC_0		1

index b167cb2..360e2e1 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 Michal Simek
+ * (C) Copyright 2007-2008 Michal Simek
  *
  * Michal SIMEK <[email protected]>
  *

@@ -83,8 +83,8 @@
 #define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
 
 /* FSL */
-#define	CFG_FSL_2
-#define	FSL_INTR_2	1
+/* #define	CFG_FSL_2 */
+/* #define	FSL_INTR_2	1 */
 
 /*
  * memory layout - Example

@@ -155,9 +155,9 @@
 
 	#else	/* !RAMENV */
 		#define	CFG_ENV_IS_IN_FLASH	1
-		#define	CFG_ENV_ADDR		0x40000
 		#define	CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-		#define	CFG_ENV_SIZE		0x2000
+		#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
+		#define	CFG_ENV_SIZE		0x40000
 	#endif /* !RAMBOOT */
 #else /* !FLASH */
 	/* ENV in RAM */

@@ -256,4 +256,7 @@
 					"256k(u-boot),256k(env),3m(kernel),"\
 					"1m(romfs),1m(cramfs),-(jffs2)\0"
 
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_OF_LIBFDT	1
+
 #endif	/* __CONFIG_H */

index f86b3b9..30fb303 100644
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 Michal Simek
+ * (C) Copyright 2007-2008 Michal Simek
  *
  * Michal SIMEK <[email protected]>
  *

@@ -156,6 +156,7 @@
 #include <config_cmd_default.h>
 
 #undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_JFFS2
 #undef CONFIG_CMD_IMLS
 
 #define CONFIG_CMD_ASKENV

@@ -203,4 +204,7 @@
 #define	CONFIG_DOS_PARTITION
 #endif
 
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_OF_LIBFDT	1 /* flat device tree */
+
 #endif	/* __CONFIG_H */