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PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

PATCH New Grant Erickson 2 participants 5 messages May 16, 2008 – May 18, 2008

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Grant Erickson

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PATCH 1/1 PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

This patch lays the ground work for moving out-of-assembly and unifying the SDRAM initialization code for PowerPC 405EX[r]-based boards.

include/ppc405.h:
Wrapped casts in EBC mnemonics with a macro such that the mnemonics can be used from assembly as well as from C.

cpu/ppc4xx/start.S:
Reworked code to handle the primordial stack and data area initialization when CFG_INIT_DCACHE_CS is asserted.

The most important change was the addition of a 'dcba' loop (per-AMCC) to preallocate data cache blocks to be used for such a purpose. In addition, other changes include replacing magic numbers with the approriate mnemonics to improve code readability and self-documentation.

Tested On:
AMCC "Haleakala" with:

    CFG_SDRAM_BASE=0x00000000
    CFG_INIT_DCACHE_CS=4
    CFG_INIT_RAM_ADDR=(CFG_SDRAM_BASE + (1 << 30))
    CFG_INIT_RAM_END=(4 << 10)
Signed-off-by Grant Erickson <[email protected]>
---
 include/ppc405.h   |   45 +++++++++++++++++++++++++++++++++++----------
 cpu/ppc4xx/start.S |  124 +++++++++++++++++++++++++++++++++++++++-------------
 2 files changed, 128 insertions(+), 41 deletions(-)
include/ppc405.h +35 -10
index 009aa68..d02eb71 100644
@@ -25,6 +25,12 @@
 #define	PPC_REG_BITS		32
 #define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
 
+#ifndef __ASSEMBLY__
+#define	static_cast(type, val)	(type)(val)
+#else
+#define	static_cast(type, val)	(val)
+#endif
+
 #ifndef CONFIG_IOP480
 #define CFG_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs	*/
 #else

@@ -371,7 +377,8 @@
 
 /* Bank Configuration Register */
 #define	EBC_BXCR_BAS_MASK	PPC_REG_VAL(11, 0xFFF)
-#define EBC_BXCR_BAS_ENCODE(n)	((((unsigned long)(n))&EBC_BXCR_BAS_MASK)<<0)
+#define EBC_BXCR_BAS_ENCODE(n)	(((static_cast(unsigned long, n)) & \
+				  EBC_BXCR_BAS_MASK) << 0)
 #define EBC_BXCR_BS_MASK	PPC_REG_VAL(14, 0x7)
 #define EBC_BXCR_BS_1MB		PPC_REG_VAL(14, 0x0)
 #define EBC_BXCR_BS_2MB		PPC_REG_VAL(14, 0x1)

@@ -394,9 +401,15 @@
 /* Bank Access Parameter Register */
 #define EBC_BXAP_BME_ENABLED	PPC_REG_VAL(0, 0x1)
 #define EBC_BXAP_BME_DISABLED	PPC_REG_VAL(0, 0x0)
-#define EBC_BXAP_TWT_ENCODE(n)	PPC_REG_VAL(8, ((unsigned long)(n)) & 0xFF)
-#define	EBC_BXAP_FWT_ENCODE(n)	PPC_REG_VAL(5, ((unsigned long)(n)) & 0x1F)
-#define	EBC_BXAP_BWT_ENCODE(n)	PPC_REG_VAL(8, ((unsigned long)(n)) & 0x7)
+#define EBC_BXAP_TWT_ENCODE(n)	PPC_REG_VAL(8, \
+					    (static_cast(unsigned long, n)) \
+					    & 0xFF)
+#define	EBC_BXAP_FWT_ENCODE(n)	PPC_REG_VAL(5, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x1F)
+#define	EBC_BXAP_BWT_ENCODE(n)	PPC_REG_VAL(8, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x7)
 #define EBC_BXAP_BCE_DISABLE	PPC_REG_VAL(9, 0x0)
 #define EBC_BXAP_BCE_ENABLE	PPC_REG_VAL(9, 0x1)
 #define EBC_BXAP_BCT_MASK	PPC_REG_VAL(11, 0x3)

@@ -404,11 +417,21 @@
 #define EBC_BXAP_BCT_4TRANS	PPC_REG_VAL(11, 0x1)
 #define EBC_BXAP_BCT_8TRANS	PPC_REG_VAL(11, 0x2)
 #define EBC_BXAP_BCT_16TRANS	PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_CSN_ENCODE(n)	PPC_REG_VAL(13, ((unsigned long)(n)) & 0x3)
-#define EBC_BXAP_OEN_ENCODE(n)	PPC_REG_VAL(15, ((unsigned long)(n)) & 0x3)
-#define EBC_BXAP_WBN_ENCODE(n)	PPC_REG_VAL(17, ((unsigned long)(n)) & 0x3)
-#define EBC_BXAP_WBF_ENCODE(n)	PPC_REG_VAL(19, ((unsigned long)(n)) & 0x3)
-#define EBC_BXAP_TH_ENCODE(n)	PPC_REG_VAL(22, ((unsigned long)(n)) & 0x7)
+#define EBC_BXAP_CSN_ENCODE(n)	PPC_REG_VAL(13, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_OEN_ENCODE(n)	PPC_REG_VAL(15, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_WBN_ENCODE(n)	PPC_REG_VAL(17, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_WBF_ENCODE(n)	PPC_REG_VAL(19, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_TH_ENCODE(n)	PPC_REG_VAL(22, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x7)
 #define EBC_BXAP_RE_ENABLED	PPC_REG_VAL(23, 0x1)
 #define EBC_BXAP_RE_DISABLED	PPC_REG_VAL(23, 0x0)
 #define EBC_BXAP_SOR_DELAYED	PPC_REG_VAL(24, 0x0)

@@ -453,7 +476,9 @@
 #define EBC_CFG_PME_DISABLE	PPC_REG_VAL(14, 0x0)
 #define EBC_CFG_PME_ENABLE	PPC_REG_VAL(14, 0x1)
 #define EBC_CFG_PMT_MASK	PPC_REG_VAL(19, 0x1F)
-#define EBC_CFG_PMT_ENCODE(n)	PPC_REG_VAL(19, ((unsigned long)(n)) & 0x1F)
+#define EBC_CFG_PMT_ENCODE(n)	PPC_REG_VAL(19, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x1F)
 #define EBC_CFG_PR_MASK		PPC_REG_VAL(21, 0x3)
 #define EBC_CFG_PR_16		PPC_REG_VAL(21, 0x0)
 #define EBC_CFG_PR_32		PPC_REG_VAL(21, 0x1)
cpu/ppc4xx/start.S +93 -31

155 lines not on this page · raw message

Signature · 1 line
1.5.4.3
#1 lore raw

PATCH 1/1 PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

Quoted 1 line · In message <[email protected]> you…

...

Quoted 2 lines

cpu/ppc4xx/start.S:
Reworked code to handle the primordial stack and data area initialization when CFG_INIT_DCACHE_CS is asserted.

...

cpu/ppc4xx/start.S _start: · line 955

Quoted 6 lines
cpu/ppc4xx/start.S +3 -3
-	 * Boards like the Kilauea (405EX) don't have OCM and can't use
-	 * DCache for init-ram. So setup stack here directly after the
-	 * SDRAM is initialized.
+	 * For boards that don't have OCM and can't use the data cache
+	 * for their primordial stack, setup stack here directly after the
+	 * SDRAM is initialized in ext_bus_cntlr_init.

Was there ever a useful explanation given why these boards should not be able to use DC as initial RAM?

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
[Braddock:] Mr. Churchill, you are drunk.
[Churchill:] And you madam, are ugly.  But I shall be sober tomorrow.
author
#2 lore raw

PATCH 1/1 PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

Quoted 14 lines · Wolfgang Denk

In message <[email protected]> you wrote:
...

Quoted 3 lines

cpu/ppc4xx/start.S:
Reworked code to handle the primordial stack and data area initialization
when CFG_INIT_DCACHE_CS is asserted.

...

cpu/ppc4xx/start.S _start: · line 955

Quoted 6 lines
cpu/ppc4xx/start.S +3 -3
-  * Boards like the Kilauea (405EX) don't have OCM and can't use
-  * DCache for init-ram. So setup stack here directly after the
-  * SDRAM is initialized.
+  * For boards that don't have OCM and can't use the data cache
+  * for their primordial stack, setup stack here directly after the
+  * SDRAM is initialized in ext_bus_cntlr_init.
Quoted 2 lines

Was there ever a useful explanation given why these boards should not be able to use DC as initial RAM?

Kilauea, Makalu and Haleakala (405EX- and 405EXr-based) can now use the data cache for the initial stack and data area with this 'dcba' change patch.

However, no clear reason has been provided as yet from the vendor as to why the 'dcba' addition was not historically required for the 405GP but is required now for the 405EX[r]. Regardless, the 'dcba' should work and, going forward, will be "more correct" on the 405GP as well.

Regards,

Grant
Principal
Nuovation System Designs, LLC

998 Alpine Terrace Suite 3
Sunnyvale, CA 94086-2469
US

T +1-408-749-0495
F +1-205-449-0495
M +1-408-489-5710

gerickson at nuovations.com
http://www.nuovations.com/

#3 lore raw

PATCH 1/1 PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

Quoted 8 lines · In message <C455E5F6.F3FB%[email protected]> you wrote:
Quoted 7 lines

cpu/ppc4xx/start.S _start: · line 955

Quoted 4 lines
cpu/ppc4xx/start.S +3 -0
+  * For boards that don't have OCM and can't use the data cache
+  * for their primordial stack, setup stack here directly after the
+  * SDRAM is initialized in ext_bus_cntlr_init.

Was there ever a useful explanation given why these boards should not be able to use DC as initial RAM?

Quoted 7 lines

Kilauea, Makalu and Haleakala (405EX- and 405EXr-based) can now use the data cache for the initial stack and data area with this 'dcba' change patch.

However, no clear reason has been provided as yet from the vendor as to why the 'dcba' addition was not historically required for the 405GP but is required now for the 405EX[r]. Regardless, the 'dcba' should work and, going forward, will be "more correct" on the 405GP as well.

So the comment "can't use the data cache for their primordial stack" is wrong and should be fixed?

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The IQ of the group is the lowest IQ of a member of the group divided
by the number of people in the group.
author
#4 lore raw

PATCH 1/1 PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

Quoted 11 lines · Wolfgang Denk
Quoted 10 lines · In message <C455E5F6.F3FB%[email protected]> you wrote:
Quoted 6 lines

cpu/ppc4xx/start.S _start: · line 955

Quoted 3 lines
cpu/ppc4xx/start.S +3 -0
+  * For boards that don't have OCM and can't use the data cache
+  * for their primordial stack, setup stack here directly after the
+  * SDRAM is initialized in ext_bus_cntlr_init.

Was there ever a useful explanation given why these boards should not be able to use DC as initial RAM?

Kilauea, Makalu and Haleakala (405EX- and 405EXr-based) can now use the data cache for the initial stack and data area with this 'dcba' change patch.

Quoted 7 lines
Quoted 4 lines

However, no clear reason has been provided as yet from the vendor as to why the 'dcba' addition was not historically required for the 405GP but is required now for the 405EX[r]. Regardless, the 'dcba' should work and, going forward, will be "more correct" on the 405GP as well.

So the comment "can't use the data cache for their primordial stack" is wrong and should be fixed?

While it is pessimistic, it may not be wrong as I don't have an exhaustive suite of chips and boards at my disposal to test.

As the code stands, should all my patches submitted for this issue get integrated, users will still have the less-than-optimal option of setting up SDRAM in ext_bus_cntlr_init should it be necessary.

Regards,

Grant
Principal
Nuovation System Designs, LLC

998 Alpine Terrace Suite 3
Sunnyvale, CA 94086-2469
US

T +1-408-749-0495
F +1-205-449-0495
M +1-408-489-5710

gerickson at nuovations.com
http://www.nuovations.com/