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PPC4xx: Makalu Uses Data Cache for Initial Stack and Leverages Shared SDRAM Code

PATCH New Grant Erickson 2 participants 2 messages May 17, 2008 – May 19, 2008

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PATCH 1/1 PPC4xx: Makalu Uses Data Cache for Initial Stack and Leverages Shared SDRAM Code

board/amcc/makalu/init.S:
board/amcc/makalu/memory.c:
include/configs/makalu.h:

Makalu now uses the data cache for its primordial stack and data area and leverages the common, shared parameter-based SDRAM initialization code.

include/ppc405.h:

Redefined SDRAM configuration size mnemonics on PPC_REG_VAL macro and added self-documenting mnemonics to remove any ambiuity about the units associated with the mnemonic.

---
 include/ppc405.h           |   52 ++++++++++++++++++++++++++++++++++----------
 board/amcc/makalu/init.S   |  127 ++------------------------------------------
 board/amcc/makalu/memory.c |  122 ++----------------------------------------
 include/configs/makalu.h   |  117 ++++++++++++++++++++++++++++++++++++++--
 4 files changed, 158 insertions(+), 260 deletions(-)
include/ppc405.h +38 -14
index d02eb71..f8eeeae 100644
@@ -1339,21 +1339,45 @@
 #define SDRAM_ECCCR     0x98    /* ECC error status                   */
 #define SDRAM_RID       0xF8    /* revision ID                        */
 
-/*-----------------------------------------------------------------------------+
+/*----------------------------------------------------------------------------+
 |  Memory Bank 0-7 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDSZ_4         0x00000000      /*   4M                    */
-#define SDRAM_RXBAS_SDSZ_8         0x00001000      /*   8M                    */
-#define SDRAM_RXBAS_SDSZ_16        0x00002000      /*  16M                    */
-#define SDRAM_RXBAS_SDSZ_32        0x00003000      /*  32M                    */
-#define SDRAM_RXBAS_SDSZ_64        0x00004000      /*  64M                    */
-#define SDRAM_RXBAS_SDSZ_128       0x00005000      /* 128M                    */
-#define SDRAM_RXBAS_SDSZ_256       0x00006000      /* 256M                    */
-#define SDRAM_RXBAS_SDSZ_512       0x00007000      /* 512M                    */
-#define SDRAM_RXBAS_SDSZ_1024      0x00008000      /* 1024M                   */
-#define SDRAM_RXBAS_SDSZ_2048      0x00009000      /* 2048M                   */
-#define SDRAM_RXBAS_SDSZ_4096      0x0000a000      /* 4096M                   */
-#define SDRAM_RXBAS_SDSZ_8192      0x0000b000      /* 8192M                   */
++----------------------------------------------------------------------------*/
+#define SDRAM_RXBAS_SDSZ_MASK		PPC_REG_VAL(19, 0xF)
+#define SDRAM_RXBAS_SDSZ_4MB	   	PPC_REG_VAL(19, 0x0)
+#define SDRAM_RXBAS_SDSZ_8MB	   	PPC_REG_VAL(19, 0x1)
+#define SDRAM_RXBAS_SDSZ_16MB	   	PPC_REG_VAL(19, 0x2)
+#define SDRAM_RXBAS_SDSZ_32MB	   	PPC_REG_VAL(19, 0x3)
+#define SDRAM_RXBAS_SDSZ_64MB	   	PPC_REG_VAL(19, 0x4)
+#define SDRAM_RXBAS_SDSZ_128MB	   	PPC_REG_VAL(19, 0x5)
+#define SDRAM_RXBAS_SDSZ_256MB	   	PPC_REG_VAL(19, 0x6)
+#define SDRAM_RXBAS_SDSZ_512MB	   	PPC_REG_VAL(19, 0x7)
+#define SDRAM_RXBAS_SDSZ_1024MB	   	PPC_REG_VAL(19, 0x8)
+#define SDRAM_RXBAS_SDSZ_2048MB	   	PPC_REG_VAL(19, 0x9)
+#define SDRAM_RXBAS_SDSZ_4096MB		PPC_REG_VAL(19, 0xA)
+#define SDRAM_RXBAS_SDSZ_8192MB		PPC_REG_VAL(19, 0xB)
+#define SDRAM_RXBAS_SDSZ_8      	SDRAM_RXBAS_SDSZ_8MB
+#define SDRAM_RXBAS_SDSZ_16     	SDRAM_RXBAS_SDSZ_16MB
+#define SDRAM_RXBAS_SDSZ_32     	SDRAM_RXBAS_SDSZ_32MB
+#define SDRAM_RXBAS_SDSZ_64     	SDRAM_RXBAS_SDSZ_64MB
+#define SDRAM_RXBAS_SDSZ_128    	SDRAM_RXBAS_SDSZ_128MB
+#define SDRAM_RXBAS_SDSZ_256    	SDRAM_RXBAS_SDSZ_256MB
+#define SDRAM_RXBAS_SDSZ_512    	SDRAM_RXBAS_SDSZ_512MB
+#define SDRAM_RXBAS_SDSZ_1024		SDRAM_RXBAS_SDSZ_1024MB
+#define SDRAM_RXBAS_SDSZ_2048		SDRAM_RXBAS_SDSZ_2048MB
+#define SDRAM_RXBAS_SDSZ_4096		SDRAM_RXBAS_SDSZ_4096MB
+#define SDRAM_RXBAS_SDSZ_8192		SDRAM_RXBAS_SDSZ_8192MB
+#define SDRAM_RXBAS_SDAM_MODE0		PPC_REG_VAL(23, 0x0)
+#define SDRAM_RXBAS_SDAM_MODE1		PPC_REG_VAL(23, 0x1)
+#define SDRAM_RXBAS_SDAM_MODE2		PPC_REG_VAL(23, 0x2)
+#define SDRAM_RXBAS_SDAM_MODE3		PPC_REG_VAL(23, 0x3)
+#define SDRAM_RXBAS_SDAM_MODE4		PPC_REG_VAL(23, 0x4)
+#define SDRAM_RXBAS_SDAM_MODE5		PPC_REG_VAL(23, 0x5)
+#define SDRAM_RXBAS_SDAM_MODE6		PPC_REG_VAL(23, 0x6)
+#define SDRAM_RXBAS_SDAM_MODE7		PPC_REG_VAL(23, 0x7)
+#define SDRAM_RXBAS_SDAM_MODE8		PPC_REG_VAL(23, 0x8)
+#define SDRAM_RXBAS_SDAM_MODE9		PPC_REG_VAL(23, 0x9)
+#define SDRAM_RXBAS_SDBE_DISABLE	PPC_REG_VAL(31, 0x0)
+#define SDRAM_RXBAS_SDBE_ENABLE		PPC_REG_VAL(31, 0x1)
 
 /*-----------------------------------------------------------------------------+
 |  Memory Controller Status
board/amcc/makalu/init.S +4 -123

138 lines not on this page · raw message

board/amcc/makalu/memory.c +5 -117

132 lines not on this page · raw message

include/configs/makalu.h +111 -6

133 lines not on this page · raw message

Signature · 1 line
1.5.4.3
#1 lore raw

PATCH 1/1 PPC4xx: Makalu Uses Data Cache for Initial Stack and Leverages Shared SDRAM Code

Quoted 8 lines · Grant Erickson

board/amcc/makalu/init.S:
board/amcc/makalu/memory.c:
include/configs/makalu.h:

Makalu now uses the data cache for its primordial stack and data area and leverages the common, shared parameter-based SDRAM initialization code.

Quoted 5 lines

include/ppc405.h:

Redefined SDRAM configuration size mnemonics on PPC_REG_VAL macro and added self-documenting mnemonics to remove any ambiuity about the units associated with the mnemonic.

Thanks.

Will you submit a patch to move Kilauea to this common code too?

Best regards,
Stefan

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