Add asm headers
PATCH 1/2 Add asm headers
These headers are used to probe and utilize CPU informartion.
- <asm/cpu-features.h>
- <asm/cpu-info.h>
- <asm/cpu.h>
- <asm/fpu.h>
- <asm/hazards.h>
---
include/asm-mips/cpu-features.h | 218 +++++++++++++++++++++++++++++++ include/asm-mips/cpu-info.h | 70 ++++++++++ include/asm-mips/cpu.h | 265 ++++++++++++++++++++++++++++++++++++++ include/asm-mips/fpu.h | 42 ++++++ include/asm-mips/hazards.h | 270 +++++++++++++++++++++++++++++++++++++++ include/asm-mips/mipsregs.h | 1 6 files changed, 866 insertions(+), 0 deletions(-) create mode 100644 include/asm-mips/cpu-features.h create mode 100644 include/asm-mips/cpu-info.h create mode 100644 include/asm-mips/cpu.h create mode 100644 include/asm-mips/fpu.h create mode 100644 include/asm-mips/hazards.h
include/asm-mips/cpu-features.h new file +218 -0
@@ -0,0 +1,218 @@ +/* +* This file is subject to the terms and conditions of the GNU General Public +* License. See the file "COPYING" in the main directory of this archive +* for more details. +* +* Copyright (C) 2003, 2004 Ralf Baechle +* Copyright (C) 2004 Maciej W. Rozycki +*/ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include <asm/cpu.h> +#include <asm/cpu-info.h> + +#ifndef current_cpu_type +#define current_cpu_type () current_cpu_data.cputype +#endif + +/* +* SMP assumption: Options of CPU 0 are a superset of all processors. +* This is true for all known MIPS systems. +*/ +#ifndef cpu_has_tlb +#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) +#endif +#ifndef cpu_has_4kex +#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) +#endif +#ifndef cpu_has_3k_cache +#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) +#endif +#define cpu_has_6k_cache 0 +#define cpu_has_8k_cache 0 +#ifndef cpu_has_4k_cache +#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) +#endif +#ifndef cpu_has_tx39_cache +#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) +#endif +#ifndef cpu_has_fpu +#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) +#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) +#else +#define raw_cpu_has_fpu cpu_has_fpu +#endif +#ifndef cpu_has_32fpr +#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) +#endif +#ifndef cpu_has_counter +#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) +#endif +#ifndef cpu_has_watch +#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) +#endif +#ifndef cpu_has_divec +#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) +#endif +#ifndef cpu_has_vce +#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) +#endif +#ifndef cpu_has_cache_cdex_p +#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) +#endif +#ifndef cpu_has_cache_cdex_s +#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) +#endif +#ifndef cpu_has_prefetch +#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) +#endif +#ifndef cpu_has_mcheck +#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) +#endif +#ifndef cpu_has_ejtag +#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) +#endif +#ifndef cpu_has_llsc +#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) +#endif +#ifndef cpu_has_mips16 +#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) +#endif +#ifndef cpu_has_mdmx +#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) +#endif +#ifndef cpu_has_mips3d +#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) +#endif +#ifndef cpu_has_smartmips +#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) +#endif +#ifndef cpu_has_vtag_icache +#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) +#endif +#ifndef cpu_has_dc_aliases +#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) +#endif +#ifndef cpu_has_ic_fills_f_dc +#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) +#endif +#ifndef cpu_has_pindexed_dcache +#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) +#endif + +/* +* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors +* such as the R10000 have I-Caches that snoop local stores; the embedded ones +* don't. For maintaining I-cache coherency this means we need to flush the +* D-cache all the way back to whever the I-cache does refills from, so the +* I-cache has a chance to see the new data at all. Then we have to flush the +* I-cache also. +* Note we may have been rescheduled and may no longer be running on the CPU +* that did the store so we can't optimize this into only doing the flush on +* the local CPU. +*/ +#ifndef cpu_icache_snoops_remote_store +#ifdef CONFIG_SMP +#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) +#else +#define cpu_icache_snoops_remote_store 1 +#endif +#endif + +# ifndef cpu_has_mips32r1 +# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) +# endif +# ifndef cpu_has_mips32r2 +# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) +# endif +# ifndef cpu_has_mips64r1 +# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) +# endif +# ifndef cpu_has_mips64r2 +# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) +# endif + +/* +* Shortcuts ... +*/ +#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) +#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) +#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) +#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) + +#ifndef cpu_has_dsp +#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) +#endif + +#ifndef cpu_has_mipsmt +#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) +#endif + +#ifndef cpu_has_userlocal +#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) +#endif + +#ifdef CONFIG_32BIT +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 0 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 0 +# endif +#endif + +#ifdef CONFIG_64BIT +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex 0 +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits 1 +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg 1 +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 1 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 1 +# endif +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_VI ) && !defined(cpu_has_vint) +# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) +#elif !defined(cpu_has_vint) +# define cpu_has_vint 0 +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_EI ) && !defined(cpu_has_veic) +# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) +#elif !defined(cpu_has_veic) +# define cpu_has_veic 0 +#endif + +#ifndef cpu_has_inclusive_pcaches +#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) +#endif + +#ifndef cpu_dcache_line_size +#define cpu_dcache_line_size () cpu_data[0].dcache.linesz +#endif +#ifndef cpu_icache_line_size +#define cpu_icache_line_size () cpu_data[0].icache.linesz +#endif +#ifndef cpu_scache_line_size +#define cpu_scache_line_size () cpu_data[0].scache.linesz +#endif + +#endif /* __ASM_CPU_FEATURES_H */
include/asm-mips/cpu-info.h new file +70 -0
70 lines not on this page · raw message
include/asm-mips/cpu.h new file +265 -0
265 lines not on this page · raw message
include/asm-mips/fpu.h new file +42 -0
42 lines not on this page · raw message
include/asm-mips/hazards.h new file +270 -0
270 lines not on this page · raw message
include/asm-mips/mipsregs.h +1 -0
@@ -16,6 +16,7 @@#if 0 #include <linux/linkage.h> #endif +#include <asm/hazards.h> /* * The following macros are especially useful for __asm__
PATCH 2/2 Add cpu_probe and cpu_report
Probe CPU information (core type, ISA level, core features and TLB size). These info will be utilized all over the further processing.
[it seems this doesn't work on qemu-mips. Need more work...]
Probed info will be appeared like below:
--------
U-Boot 1.3.3-rc3-00018-g4cb1ca8 (May 6 2008 - 11:05:51)
DRAM: 256 MB
Flash: 64 MB
CPU revision is: 00005520 (R5500)
FPU revision is: 00035520
Using default environment
In: serial Out: serial Err: serial Net: No ethernet found.
#
--------
U-Boot 1.3.3-rc3-00018-g4cb1ca8 (May 6 2008 - 11:09:28)
DRAM: 256 MB
Flash: 64 MB
CPU revision is: 00019064 (MIPS 4KEc)
Using default environment
In: serial Out: serial Err: serial Net: No ethernet found.
#
----------------
---
cpu/mips/Makefile | 2 cpu/mips/cpu-probe.c | 754 ++++++++++++++++++++++++++++++++++++++++++++++++++ cpu/mips/cpu.c | 3 lib_mips/board.c | 5 4 files changed, 763 insertions(+), 1 deletions(-) create mode 100644 cpu/mips/cpu-probe.c
cpu/mips/Makefile +1 -1
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ - cpu.o interrupts.o incaip_clock.o + cpu.o cpu-probe.o interrupts.o incaip_clock.o SOBJS = incaip_wdt.o cache.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
cpu/mips/cpu-probe.c new file +754 -0
754 lines not on this page · raw message
cpu/mips/cpu.c +3 -0
@@ -23,10 +23,13 @@#include <common.h> #include <command.h> +#include <asm/cpu-info.h> #include <asm/mipsregs.h> #include <asm/cacheops.h> #include <asm/reboot.h> +struct cpuinfo_mips cpu_data[1 ];/* NR_CPUS */ +#define cache_op (op,addr) \ __asm__ __volatile__( \ " .set push \n" \
lib_mips/board.c +5 -0
@@ -31,6 +31,8 @@#include <nand.h> #include <spi.h> +#include <asm/cpu-info.h> +DECLARE_GLOBAL_DATA_PTR ; #if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
@@ -373,6 +375,9 @@ void board_init_r (gd_t *id, ulong dest_addr) bd->bi_flashoffset =0 ;#endif +cpu_probe (); +cpu_report (); +/* initialize malloc() area */ mem_malloc_init ();malloc_bin_reloc ();
PATCH 2/2 Add cpu_probe and cpu_report
Quoted 2 lines · In message <[email protected]> you wrote:
Probe CPU information (core type, ISA level, core features and TLB size). These info will be utilized all over the further processing.
...
Quoted 1 line
cpu/mips/cpu-probe.c | 754 ++++++++++++++++++++++++++++++++++++++++++++++++++
Ummm... we're adding more than 750 lines of code - for which benefit exactly?
How much memory footprint does this code add?
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "The two most common things in the universe are hydrogen and stupi- dity."
PATCH 2/2 Add cpu_probe and cpu_report
Quoted 8 lines · Wolfgang Denk
Quoted 2 lines · In message <[email protected]> you wrote:
Probe CPU information (core type, ISA level, core features and TLB size). These info will be utilized all over the further processing.
...
Quoted 1 line
cpu/mips/cpu-probe.c | 754 ++++++++++++++++++++++++++++++++++++++++++++++++++Ummm... we're adding more than 750 lines of code - for which benefit exactly?
This patch is still in development, and just probes info at the moment. We will utilize it around TLB initialization, cache unrolling, .etc. But that's not yet prepared, should have postphone submission for the review.
Please ignore this patch. I'll drop this patch from my queue.
Sorry for noise,
Shinya
Quoted 6 lines
How much memory footprint does this code add?
Best regards,
Wolfgang Denk
PATCH 2/2 Add cpu_probe and cpu_report
Quoted 9 lines · In message <[email protected]> you wrote:
Quoted 3 lines
Ummm... we're adding more than 750 lines of code - for which benefit exactly?
This patch is still in development, and just probes info at the moment. We will utilize it around TLB initialization, cache unrolling, .etc. But that's not yet prepared, should have postphone submission for the review.
Please ignore this patch. I'll drop this patch from my queue.
...
Quoted 1 line
Quoted 1 line
How much memory footprint does this code add?
OK, but please be prepared that I will repeat these two questions, then :-)
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de I've already got a female to worry about. Her name is the Enterprise. -- Kirk, "The Corbomite Maneuver", stardate 1514.0
PATCH 1/2 Add asm headers
In reply to Shinya KuribayashiQuoted 7 lines · In message <[email protected]> you wrote:
These headers are used to probe and utilize CPU informartion.
- <
asm/cpu-features.h>
- <asm/cpu-info.h>
- <asm/cpu.h>
- <asm/fpu.h>
- <asm/hazards.h>
...
include/asm-mips/cpu.h line 7
Quoted 13 lines
include/asm-mips/cpu.h new file +7
-0@@ -0,0 +1,265 @@ +/* +* cpu.h: Values of the PRId register used to match up +* various MIPS cpu types. +* +* Copyright (C) 1996 David S. Miller (dm at engr.sgi.com) +* Copyright (C) 2004 Maciej W. Rozycki +*/
Which license is this file released under?
Best regards,
Wolfgang Denk
Signature · 6 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de A star captain's most solemn oath is that he will give his life, even his entire crew, rather than violate the Prime Directive. -- Kirk, "The Omega Glory", stardate unknown
PATCH 1/2 Add asm headers
Quoted 9 lines · Wolfgang Denk
Quoted 7 lines · In message <[email protected]> you wrote:
These headers are used to probe and utilize CPU informartion.
- <
asm/cpu-features.h>
- <asm/cpu-info.h>
- <asm/cpu.h>
- <asm/fpu.h>
- <asm/hazards.h>...
Quoted 15 lines
include/asm-mips/cpu.h line 7
Quoted 13 lines
include/asm-mips/cpu.h new file +7
-0@@ -0,0 +1,265 @@ +/* +* cpu.h: Values of the PRId register used to match up +* various MIPS cpu types. +* +* Copyright (C) 1996 David S. Miller (dm at engr.sgi.com) +* Copyright (C) 2004 Maciej W. Rozycki +*/ Which license is this file released under?
GPLv2 only, no doubt. I'll check it.
Thanks for pointing this out.
Shinya