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DM9000: Several fixes/cleanups for the DM9000A controller

PATCH New Remy Bohmer 4 participants 19 messages Jun 3, 2008 – Jun 4, 2008

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Remy Bohmer

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#0 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

The following 6 patches contain several fixes and cleanups for the DM9000A network controller. It turned out that the U-boot DM9000 driver was not working with this particular version of the DM9000 series.

At low speeds (10MBit) it was sometimes capable of getting a peer-2-peer connection, but 100MBit did not work at all, also connecting the board to a corporate network did not work at any speed.

Looking deeper at the code it turned out that many things where done different than recommended in the Application Notes and Programming Guides for these controllers. Doing the things as recommended solved the problems with the DM9000A.

The complete series has been tested with the Atmel AT91SAM9261-EK, and a custom board, with the DM9000[A|E|EP] controllers.

Signed-off-by Remy Bohmer <[email protected]>
#7 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

In reply to Remy Bohmer

Wolfgang,

Is the merge window open for the rest of today, or is it closed? If open, I'll look at this patch set later today and act on it. Otherwise this goes into the 'for later' bin.

regards,
Ben

Quoted 18 lines · Remy Bohmer

The following 6 patches contain several fixes and cleanups for the DM9000A network controller. It turned out that the U-boot DM9000 driver was not working with this particular version of the DM9000 series.

At low speeds (10MBit) it was sometimes capable of getting a peer-2-peer connection, but 100MBit did not work at all, also connecting the board to a corporate network did not work at any speed.

Looking deeper at the code it turned out that many things where done different than recommended in the Application Notes and Programming Guides for these controllers. Doing the things as recommended solved the problems with the DM9000A.

The complete series has been tested with the Atmel AT91SAM9261-EK, and a custom board, with the DM9000[A|E|EP] controllers.

Signed-off-by Remy Bohmer <[email protected]>
#8 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Quoted 6 lines · Ben Warren

Wolfgang,

Is the merge window open for the rest of today, or is it closed? If open, I'll look at this patch set later today and act on it. Otherwise this goes into the 'for later' bin.

Hi,

this patch does not work on the trizeps board. I get the following error:

$ tftp 0xa0010000 u-boot.bin
dm9000 i/o: 0x8000000, id: 0x90000a46

DM9000: running in 32 bit mode

MAC: 00:50:c2:3b:8f:0a

operating at 100M full duplex mode

TFTP from server 192.168.2.14; our IP address is 192.168.2.77

Filename 'u-boot.bin'.
Load address: 0xa0010000

Loading: DM9000 error: status check fail: 0x6d

I have only applied the patches and tried a quick check...The bus width is correctly recognized but there is no data transfer.

However, the ethernet controller works with the current driver:

$ tftp  0xa0010000 u-boot.bin
dm9000 i/o: 0x8000000, id: 0x90000a46

MAC: 00:50:c2:3b:8f:0a

operating at 100M full duplex mode

TFTP from server 192.168.2.14; our IP address is 192.168.2.77

Filename 'u-boot.bin'.
Load address: 0xa0010000

Loading: ###########

done

Bytes transferred = 160180 (271b4 hex)

Regards,
Stefano

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================
author
#9 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Hello Stefano,

Quoted 2 lines

this patch does not work on the trizeps board. I get the following error:
Loading: DM9000 error: status check fail: 0x6d

I think I know where this one comes from.
The code reporting this error is actually not changed, but the pace in which it is called is much faster with the new code (when a 2nd packet is in the fifo) compared to the old U-boot driver code.
I can imagine you run into a race in the network driver that you never did see before, or very infrequent.

I left this piece of code untouched because the Application Notes did not speak the same language on this register. One App.note explicitly mentioned only to check bit 0:1 of this register, while others did speak about it with that many words. Notice that they all did not disagree about this.
Besides, the old code, and the Linux kernel, checked the whole byte.

So, stupid me, left it untouched against better knowledge...

In a few minutes I will post a patch which I hope it will solve this. Can you please try it on your board?
If so, it can be added to the patch series earlier today.

Kind Regards,

Remy

#10 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Quoted 2 lines · Remy Bohmer

In a few minutes I will post a patch which I hope it will solve this. Can you please try it on your board?

I have tried, the old error is gone, but the board hangs probably after getting the first packets:

$ tftp 0xa0010000 u-boot.bin
dm9000 i/o: 0x8000000, id: 0x90000a46

DM9000: running in 32 bit mode

MAC: 00:50:c2:3b:8f:0a

operating at 100M full duplex mode

TFTP from server 192.168.2.14; our IP address is 192.168.2.77

Filename 'u-boot.bin'.
Load address: 0xa0010000

Loading:*

Enabling the debug I get this output (so the first packet was received):

$  tftp 0xa0010000 u-boot.bin
eth_halt

phy_write(reg:0x0, value:0x8000)

eth_init()

resetting DM9000

resetting the DM9000, 1st reset

resetting the DM9000, 2nd reset

dm9000 i/o: 0x8000000, id: 0x90000a46

DM9000: running in 32 bit mode

phy_read(0x3): 0x0

MAC: 00:50:c2:3b:8f:0a

00:50:c2:3b:8f:0a:

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

[snip]

phy_read(0x1): 0x780d

phy_read(0x1): 0x780d

phy_read(0x1): 0x780d

phy_read(0x1): 0x780d

[snip]

phy_read(0x1): 0x780d

phy_read(0x1): 0x782d

phy_read(0x11): 0x8018

operating at 100M full duplex mode

TFTP from server 192.168.2.14; our IP address is 192.168.2.77

Filename 'u-boot.bin'.
Load address: 0xa0010000

Loading: eth_send: length: 42

eth_send: 00: ff ff ff ff ff ff 00 50

eth_send: 08: c2 3b 8f 0a 08 06 00 01

eth_send: 10: 08 00 06 04 00 01 00 50

eth_send: 18: c2 3b 8f 0a c0 a8 02 4d

eth_send: 20: 00 00 00 00 00 00 c0 a8

eth_send: 28: 02 0e

transmit done

receiving packet

rx status: 0x0001 rx len: 64

eth_rx: length: 64

eth_rx: 00: 01 00 40 00 00 50 c2 3b

eth_rx: 08: 8f 0a 00 0b 2b 12 e3 3c

eth_rx: 10: 08 06 00 01 08 00 06 04

eth_rx: 18: 00 02 00 0b 2b 12 e3 3c

eth_rx: 20: c0 a8 02 0e 00 50 c2 3b

eth_rx: 28: 8f 0a c0 a8 02 4d 00 00

eth_rx: 30: 00 00 00 00 00 00 00 00

eth_rx: 38: 00 00 00 00 00 00 00 00

passing packet to upper layer

receiving packet

rx status: 0x806d rx len: 24529

              ^^^          ^^^^^--> wrong

Stefano

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================
author
#11 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Hello Stefano,

Thanks for testing these patches on the trizeps board. This is very useful debug info.
I did not expect these problems, but I will continue debugging them.

I assume the problem is caused by patch 05, about fixing the receive path for DM9000A. Is this correct?
Just to be sure: Does your board contain a DM9000E controller?

It is probably again those little differences between the flavours of these chips that is killing the driver.
The same reason why the DM9000A did not work, caused the problem why your chip does not work now...

I will look into it some deeper and come back to you if I have more info.

Kind Regards,

Remy

2008/6/4 Stefano Babic <[email protected]>:

Quoted 148 lines
Quoted 2 lines · Remy Bohmer

In a few minutes I will post a patch which I hope it will solve this. Can you please try it on your board?

I have tried, the old error is gone, but the board hangs probably after getting the first packets:

$ tftp 0xa0010000 u-boot.bin
dm9000 i/o: 0x8000000, id: 0x90000a46

DM9000: running in 32 bit mode

MAC: 00:50:c2:3b:8f:0a

operating at 100M full duplex mode

TFTP from server 192.168.2.14; our IP address is 192.168.2.77

Filename 'u-boot.bin'.
Load address: 0xa0010000

Loading:*

Enabling the debug I get this output (so the first packet was received):

$  tftp 0xa0010000 u-boot.bin
eth_halt

phy_write(reg:0x0, value:0x8000)

eth_init()

resetting DM9000

resetting the DM9000, 1st reset

resetting the DM9000, 2nd reset

dm9000 i/o: 0x8000000, id: 0x90000a46

DM9000: running in 32 bit mode

phy_read(0x3): 0x0

MAC: 00:50:c2:3b:8f:0a

00:50:c2:3b:8f:0a:

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

phy_read(0x1): 0x7809

[snip]

phy_read(0x1): 0x780d

phy_read(0x1): 0x780d

phy_read(0x1): 0x780d

phy_read(0x1): 0x780d

[snip]

phy_read(0x1): 0x780d

phy_read(0x1): 0x782d

phy_read(0x11): 0x8018

operating at 100M full duplex mode

TFTP from server 192.168.2.14; our IP address is 192.168.2.77

Filename 'u-boot.bin'.
Load address: 0xa0010000

Loading: eth_send: length: 42

eth_send: 00: ff ff ff ff ff ff 00 50

eth_send: 08: c2 3b 8f 0a 08 06 00 01

eth_send: 10: 08 00 06 04 00 01 00 50

eth_send: 18: c2 3b 8f 0a c0 a8 02 4d

eth_send: 20: 00 00 00 00 00 00 c0 a8

eth_send: 28: 02 0e

transmit done

receiving packet

rx status: 0x0001 rx len: 64

eth_rx: length: 64

eth_rx: 00: 01 00 40 00 00 50 c2 3b

eth_rx: 08: 8f 0a 00 0b 2b 12 e3 3c

eth_rx: 10: 08 06 00 01 08 00 06 04

eth_rx: 18: 00 02 00 0b 2b 12 e3 3c

eth_rx: 20: c0 a8 02 0e 00 50 c2 3b

eth_rx: 28: 8f 0a c0 a8 02 4d 00 00

eth_rx: 30: 00 00 00 00 00 00 00 00

eth_rx: 38: 00 00 00 00 00 00 00 00

passing packet to upper layer

receiving packet

rx status: 0x806d rx len: 24529

             ^^^          ^^^^^--> wrong

Stefano

--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

author
#12 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Hello Stefano,

Quoted 2 lines
Quoted 2 lines

I have tried, the old error is gone, but the board hangs probably after getting the first packets:

I believe I found the problem.
During a last minute cleanup I broke something that only breaks it in 32 bit mode.

So, it is probably not patch number 5, but patch number 1 that broke it...

I will post a mail in a few minutes solving this...
Please apply this new past on top of the 6-patches series I posted yesterday.

Kind Regards,

Remy

#13 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Quoted 2 lines · Remy Bohmer

I will post a mail in a few minutes solving this...
Please apply this new past on top of the 6-patches series I posted yesterday.

Great ! It works, I tested now with bigger files and it sounds good !

I have seen that the complete patch (all patch 0-xx) is not so big and smaller as the limit of the mailing list (17k < 40k). What about to send only the complete patch ? It is easier to read for the review.

There are some issues with the coding style, too (trailing blanks, for example).

Kind regards,
Stefano

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: [email protected]
=====================================================================
author
#14 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Hello Stefano,

Quoted 1 line

Great ! It works, I tested now with bigger files and it sounds good !

Good news!

Quoted 3 lines

I have seen that the complete patch (all patch 0-xx) is not so big and smaller as the limit of the mailing list (17k < 40k). What about to send only the complete patch ? It is easier to read for the review.

I made it seperate patches because all changes are seperate from each other. One does not have to install the complete series. Every step should result in a bootable and working driver.
Some other rule says: Keep patches as small as possible...

I looked at the complete change at first, but that makes it unreadable, and I believe, harder to review.
Many changes are trivial, only some are more intrusive...

Quoted 2 lines

There are some issues with the coding style, too (trailing blanks, for example).

hmm, I have configured quilt such that it normally removes those whitespaces... I have to find out what went wrong here.

Wolfgang, Is the merge window for these patches still open?
If so, I will clean up the patches, and distribute it again in about an hour.

Kind Regards,

Remy

2008/6/4 Stefano Babic <[email protected]>:

Quoted 23 lines
Quoted 2 lines · Remy Bohmer

I will post a mail in a few minutes solving this...
Please apply this new past on top of the 6-patches series I posted yesterday.

I have seen that the complete patch (all patch 0-xx) is not so big and smaller as the limit of the mailing list (17k < 40k). What about to send only the complete patch ? It is easier to read for the review.

There are some issues with the coding style, too (trailing blanks, for example).

Kind regards,
Stefano

--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

#15 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Quoted 24 lines · Remy Bohmer

Hello Stefano,

Quoted 2 lines

Great ! It works, I tested now with bigger files and it sounds good !

Good news!

Quoted 4 lines

I have seen that the complete patch (all patch 0-xx) is not so big and smaller as the limit of the mailing list (17k < 40k). What about to send only the complete patch ? It is easier to read for the review.

I made it seperate patches because all changes are seperate from each other. One does not have to install the complete series. Every step should result in a bootable and working driver.
Some other rule says: Keep patches as small as possible...

I looked at the complete change at first, but that makes it unreadable, and I believe, harder to review.
Many changes are trivial, only some are more intrusive...

Quoted 8 lines
Quoted 3 lines

There are some issues with the coding style, too (trailing blanks, for example).

hmm, I have configured quilt such that it normally removes those whitespaces... I have to find out what went wrong here.

I only encountered one whitespace issue, in patch 5 and was able to fix it. I use the --whitespace=strip option in git-am, so trailing whitespace isn't a problem.

Quoted 4 lines

Wolfgang, Is the merge window for these patches still open?
If so, I will clean up the patches, and distribute it again in about an hour.

I've applied your patches to the net repo, and since you submitted them by the deadline it should go in this release.

author
#16 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Hello Ben,

Quoted 3 lines

I only encountered one whitespace issue, in patch 5 and was able to fix it. I use the --whitespace=strip option in git-am, so trailing whitespace isn't a problem.

Thanks!

Quoted 2 lines

I've applied your patches to the net repo, and since you submitted them by the deadline it should go in this release.

Thanks again :-)

Remy

#17 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

In reply to Ben Warren

Dear Ben,

Quoted 4 lines · in message <[email protected]> you wrote:

Is the merge window open for the rest of today, or is it closed? If open, I'll look at this patch set later today and act on it. Otherwise this goes into the 'for later' bin.

I did a terrible job of (not) merging patches during the last few weeks, so I think we should keep the merge window open for another week, i. e. until June 10.

Best regards,

Wolfgang Denk

Signature · 4 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Hindsight is an exact science.
#18 lore raw

cover DM9000: Several fixes/cleanups for the DM9000A controller

Quoted 4 lines · Wolfgang Denk

Dear Ben,

Quoted 1 line · in message <[email protected]> you wrote:
Quoted 8 lines
Quoted 3 lines

Is the merge window open for the rest of today, or is it closed? If open, I'll look at this patch set later today and act on it. Otherwise this goes into the 'for later' bin.

I did a terrible job of (not) merging patches during the last few weeks, so I think we should keep the merge window open for another week, i. e. until June 10.

Great news! Thanks. I'm sure I'm not the only one that thinks this merge window was very short.

regards,
Ben