PPC4xx: Enable Primordial Stack for 40x and Unify ECC Handling

PATCH New Grant Erickson 2 participants 2 messages May 22, 2008 – Jun 3, 2008

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Grant Erickson

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2008-05-22 21:44 UTC #0 lore raw

PATCH v3 1/2 PPC4xx: Enable Primordial Stack for 40x and Unify ECC Handling

This patch (Part 1 of 2):

* Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value.

- Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it.

Signed-off-by Grant Erickson <[email protected]>

---
 cpu/ppc4xx/44x_spd_ddr.c    |   49 +-------
 cpu/ppc4xx/44x_spd_ddr2.c   |  120 ++++++++++++++++-
 cpu/ppc4xx/Makefile         |    1 +
 cpu/ppc4xx/cpu_init.c       |   85 ------------
 cpu/ppc4xx/ecc.c            |  121 +++++++++++++++++
 cpu/ppc4xx/ecc.h            |   42 ++++++
 cpu/ppc4xx/sdram.c          |   44 +------
 cpu/ppc4xx/start.S          |  314 ++++++++++++++++++++++++++++++++-----------
 cpu/ppc4xx/traps.c          |    9 +-
 include/asm-ppc/processor.h |    6 +-
 include/ppc405.h            |  191 +++++++++++++++++++++++++--
 include/ppc4xx.h            |   15 ++
 12 files changed

cpu/ppc4xx/44x_spd_ddr.c +3 ~~-46~~

index b9cf5cb..b7eeaf2 100644
@@ -53,6 +53,8 @@
 #include <ppc4xx.h>
 #include <asm/mmu.h>
 
+#include "ecc.h"
+
 #if defined(CONFIG_SPD_EEPROM) &&					\
 	(defined(CONFIG_440GP) || defined(CONFIG_440GX) ||		\
 	 defined(CONFIG_440EP) || defined(CONFIG_440GR))

@@ -296,10 +298,6 @@ static void program_tr0(unsigned long *dimm_populated,
 			unsigned long num_dimm_banks);
 static void program_tr1(void);
 
-#ifdef CONFIG_DDR_ECC
-static void program_ecc(unsigned long num_bytes);
-#endif
-
 static unsigned long program_bxcr(unsigned long *dimm_populated,
 				  unsigned char *iic0_dimm_addr,
 				  unsigned long num_dimm_banks);

@@ -418,7 +416,7 @@ long int spd_sdram(void) {
 	/*
 	 * If ecc is enabled, initialize the parity bits.
 	 */
-	program_ecc(total_size);
+	ecc_init(CFG_SDRAM_BASE, total_size);
 #endif
 
 	return total_size;

@@ -1402,45 +1400,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 
 	return(bank_base_addr);
 }
-
-#ifdef CONFIG_DDR_ECC
-static void program_ecc(unsigned long num_bytes)
-{
-	unsigned long bank_base_addr;
-	unsigned long current_address;
-	unsigned long end_address;
-	unsigned long address_increment;
-	unsigned long cfg0;
-
-	/*
-	 * get Memory Controller Options 0 data
-	 */
-	mfsdram(mem_cfg0, cfg0);
-
-	/*
-	 * reset the bank_base address
-	 */
-	bank_base_addr = CFG_SDRAM_BASE;
-
-	if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
-		mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
-
-		if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
-			address_increment = 4;
-		else
-			address_increment = 8;
-
-		current_address = (unsigned long)(bank_base_addr);
-		end_address = (unsigned long)(bank_base_addr) + num_bytes;
-
-		while (current_address < end_address) {
-			*((unsigned long*)current_address) = 0x00000000;
-			current_address += address_increment;
-		}
-
-		mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
-			SDRAM_CFG0_MCHK_CHK);
-	}
-}
-#endif /* CONFIG_DDR_ECC */
 #endif /* CONFIG_SPD_EEPROM */

cpu/ppc4xx/44x_spd_ddr2.c +116 -4

140 lines not on this page · raw message

cpu/ppc4xx/Makefile +1 -0

index 178c5c6..800bb41 100644
@@ -45,6 +45,7 @@ COBJS	+= cpu.o
 COBJS	+= cpu_init.o
 COBJS	+= denali_data_eye.o
 COBJS	+= denali_spd_ddr2.o
+COBJS	+= ecc.o
 COBJS	+= fdt.o
 COBJS	+= gpio.o
 COBJS	+= i2c.o

cpu/ppc4xx/cpu_init.c +0 ~~-85~~

97 lines not on this page · raw message

cpu/ppc4xx/ecc.c new file +121 -0

121 lines not on this page · raw message

cpu/ppc4xx/ecc.h new file +42 -0

42 lines not on this page · raw message

cpu/ppc4xx/sdram.c +1 ~~-43~~

56 lines not on this page · raw message

cpu/ppc4xx/start.S +235 ~~-79~~

433 lines not on this page · raw message

cpu/ppc4xx/traps.c +7 -2

index 38b6f89..8b7e32a 100644
@@ -170,7 +170,7 @@ MachineCheckException(struct pt_regs *regs)
 
 	val = get_esr();
 
-#if !defined(CONFIG_440)
+#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
 	if (val& ESR_IMCP) {
 		printf("Instruction");
 		mtspr(ESR, val & ~ESR_IMCP);

@@ -179,7 +179,7 @@ MachineCheckException(struct pt_regs *regs)
 	}
 	printf(" machine check.\n");
 
-#elif defined(CONFIG_440)
+#elif defined(CONFIG_440) || defined(CONFIG_405EX)
 	if (val& ESR_IMCP){
 		printf("Instruction Synchronous Machine Check exception\n");
 		mtspr(SPRN_ESR, val & ~ESR_IMCP);

@@ -187,10 +187,15 @@ MachineCheckException(struct pt_regs *regs)
 		val = mfspr(MCSR);
 		if (val & MCSR_IB)
 			printf("Instruction Read PLB Error\n");
+#if defined(CONFIG_440)
 		if (val & MCSR_DRB)
 			printf("Data Read PLB Error\n");
 		if (val & MCSR_DWB)
 			printf("Data Write PLB Error\n");
+#else
+		if (val & MCSR_DB)
+			printf("Data PLB Error\n");
+#endif
 		if (val & MCSR_TLBP)
 			printf("TLB Parity Error\n");
 		if (val & MCSR_ICP){

include/asm-ppc/processor.h +4 -2

index 8bdfb9d..cfd8440 100644
@@ -460,17 +460,19 @@
 #define SPRN_PID2	0x27a	/* Process ID Register 2 */
 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
 #define SPRN_MCAR	0x23d	/* Machine Check Address register */
-#ifdef CONFIG_440
 #define MCSR_MCS	0x80000000	/* Machine Check Summary */
 #define MCSR_IB		0x40000000	/* Instruction PLB Error */
+#if defined(CONFIG_440)
 #define MCSR_DRB	0x20000000	/* Data Read PLB Error */
 #define MCSR_DWB	0x10000000	/* Data Write PLB Error */
+#else
+#define MCSR_DB		0x20000000	/* Data PLB Error */
+#endif /* defined(CONFIG_440) */
 #define MCSR_TLBP	0x08000000	/* TLB Parity Error */
 #define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
 #define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
 #define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
 #define MCSR_IMPE	0x00800000	/* Imprecise Machine Check Exception */
-#endif
 #define ESR_ST		0x00800000	/* Store Operation */
 
 #if defined(CONFIG_MPC86xx)

include/ppc405.h +178 ~~-13~~

213 lines not on this page · raw message

include/ppc4xx.h +15 -0

index 76fe872..4a6eb86 100644
@@ -29,6 +29,21 @@
 #endif
 
 /*
+ * Macro for generating register field mnemonics
+ */
+#define	PPC_REG_BITS		32
+#define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
+
+/*
+ * Elide casts when assembling register mnemonics
+ */
+#ifndef __ASSEMBLY__
+#define	static_cast(type, val)	(type)(val)
+#else
+#define	static_cast(type, val)	(val)
+#endif
+
+/*
  * Common stuff for 4xx (405 and 440)
  */

Stefan Roese

2008-06-03 18:35 UTC #1 lore raw

PATCH v3 1/2 PPC4xx: Enable Primordial Stack for 40x and Unify ECC Handling

Quoted 20 lines · Grant Erickson

This patch (Part 1 of 2):
* Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
* Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code.
* Enables MCSR visibility on the 405EX(r).
* Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value.
- Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c.

Quoted 6 lines

With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it.

Applied to u-boot-ppc4xx repo. Thanks.

Best regards,
Stefan

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