PPC4xx: Enable Primordial Stack for 40x and Unify ECC Handling

index 8cd534c..bf47d6b 100644
@@ -1,8 +1,11 @@
 /*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <[email protected]>
+ *
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
- * Based on code provided from UDTech and AMCC
+ * Originally based on code provided from UDTech and AMCC
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -30,125 +33,135 @@
 #include <ppc_defs.h>
 
 #define mtsdram_as(reg, value)		\
-	addi    r4,0,reg	;	\
-	mtdcr   memcfga,r4	;	\
-	addis   r4,0,value at h	;	\
-	ori     r4,r4,value at l	;	\
-	mtdcr   memcfgd,r4	;
+	addi	r4,0,reg	;	\
+	mtdcr	memcfga,r4	;	\
+	addis	r4,0,value at h	;	\
+	ori	r4,r4,value at l	;	\
+	mtdcr	memcfgd,r4	;
+
+#if defined(CONFIG_DDR_ECC)
+	.extern ecc_init
+#endif /* defined(CONFIG_DDR_ECC) */
 
 	.globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
+#if !defined(CFG_INIT_DCACHE_CS)
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 
 	/*
-	 * DDR2 setup
+	 * DDR2 SDRAM Controller Setup
 	 */
 
-	/* Following the DDR Core Manual, here is the initialization */
-
-	/* Step 1 */
-
-	/* Step 2 */
-
-	/* Step 3 */
-
-	/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
-	mtsdram_as(SDRAM_MB0CF, 0x00006701);
-
-	/* SET SDRAM_MB1CF - Not enabled */
-	mtsdram_as(SDRAM_MB1CF, 0x00000000);
-
-	/* SET SDRAM_MB2CF  - Not enabled */
-	mtsdram_as(SDRAM_MB2CF, 0x00000000);
-
-	/* SET SDRAM_MB3CF  - Not enabled */
-	mtsdram_as(SDRAM_MB3CF, 0x00000000);
-
-	/* SDRAM_CLKTR: Adv Addr clock by 180 deg */
-	mtsdram_as(SDRAM_CLKTR, 0x80000000);
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS */
-	mtsdram_as(SDRAM_RTR, 0x06180000);
+	/* Set Memory Bank Configuration Registers */
+	mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
+	mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
+	mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
+	mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+
+	/* Set Memory Clock Timing Register */
+	mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+
+	/* Set Refresh Time Register */
+	mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR);
+
+	/* Set SDRAM Timing Registers */
+	mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
+	mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
+	mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+
+	/* Set Mode and Extended Mode Registers */
+	mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE);
+	mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+
+	/* Set Memory Controller Options 1 Register */
+	mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+
+	/* Set Manual Initialization Control Registers */
+	mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
+	mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
+	mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
+	mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
+	mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
+	mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
+	mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
+	mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
+	mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
+	mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
+	mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
+	mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
+	mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
+	mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
+	mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
+	mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+
+	/* Set On-Die Termination Registers */
+	mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT);
+	mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0);
+	mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+
+	/* Set Write Timing Register */
+	mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
 
-	/* SDRAM_SDTR1 */
-	mtsdram_as(SDRAM_SDTR1, 0x80201000);
-
-	/* SDRAM_SDTR2	*/
-	mtsdram_as(SDRAM_SDTR2, 0x32204232);
+	/*
+	 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
+	 * SDRAM0_MCOPT2[IPTR] = 1
+	 */
+	mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \
+				 SDRAM_MCOPT2_IPTR_EXECUTE);
 
-	/* SDRAM_SDTR3	*/
-	mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
+	/*
+	 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
+	 * completion of initialization.
+	 *
+	 *   do {
+	 *           mfsdram(SDRAM_MCSTAT, val);
+	 *   } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
+	 */
+	li	r4,SDRAM_MCSTAT
+	lis	r2,SDRAM_MCSTAT_MIC_COMP at h
+	ori	r2,r2,SDRAM_MCSTAT_MIC_COMP at l
+0:	mtdcr	memcfga,r4
+	mfdcr	r3,memcfgd
+	clrrwi	r3,r3,31
+	cmpw	cr7,r3,r2
+	bne+	cr7,0b
+
+	/* Set Delay Control Registers */
+	mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR);
+	mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC);
+	mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC);
+	mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC);
 
-	mtsdram_as(SDRAM_MMODE, 0x00000442);
-	mtsdram_as(SDRAM_MEMODE, 0x00000404);
+	/*
+	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
+	 *
+	 *   mcopt2 = mfsdram(SDRAM_MCOPT2);
+	 */
+	li	r4,SDRAM_MCOPT2
+	mtdcr	memcfga,r4
+	mfdcr	r3,memcfgd
 
-	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
-	mtsdram_as(SDRAM_MCOPT1, 0x04322000);
+	/*
+	 *   mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE);
+	 */
+	mtdcr	memcfga,r4
+	oris	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE at h
+	ori	r3,r3,SDRAM_MCOPT2_DCEN_ENABLE at l
+	mtdcr	memcfgd,r3
 
-	/* NOP */
-	mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR1, 0x81900400);
-	/* EMR2 twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR2, 0x81020000);
-	/* EMR3  twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR3, 0x81030000);
-	/* EMR DLL ENABLE twr = 2tck */
-	mtsdram_as(SDRAM_INITPLR4, 0x81010404);
-	/* MR w/ DLL reset
-	 * Note: 5 is CL.  May need to be changed
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 *   ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
 	 */
-	mtsdram_as(SDRAM_INITPLR5, 0x81000542);
-	/* precharge 3 DDR clock cycle */
-	mtsdram_as(SDRAM_INITPLR6, 0x81900400);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
-	/* Auto-refresh trfc = 26tck */
-	mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
-	/* Auto-refresh */
-	mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
-	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
-	mtsdram_as(SDRAM_INITPLR11, 0x81000442);
-	mtsdram_as(SDRAM_INITPLR12, 0x81010780);
-	mtsdram_as(SDRAM_INITPLR13, 0x81010400);
-	mtsdram_as(SDRAM_INITPLR14, 0x00000000);
-	mtsdram_as(SDRAM_INITPLR15, 0x00000000);
-
-	/* SET MCIF0_CODT   Die Termination On */
-	mtsdram_as(SDRAM_CODT, 0x0080f837);
-	mtsdram_as(SDRAM_MODT0, 0x01800000);
-	mtsdram_as(SDRAM_MODT1, 0x00000000);
-
-	mtsdram_as(SDRAM_WRDTR, 0x00000000);
-
-	/* SDRAM0_MCOPT2 (0X21) Start initialization */
-	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
-
-	/* Step 5 */
-	lis     r3,0x1	/* 400000 =  wait 100ms */
-	mtctr   r3
-
-pll_wait:
-	bdnz	pll_wait
-
-	/* Step 6 */
-
-	/* SDRAM_DLCR */
-	mtsdram_as(SDRAM_DLCR, 0x030000a5);
-
-	/* SDRAM_RDCC */
-	mtsdram_as(SDRAM_RDCC, 0x40000000);
-
-	/* SDRAM_RQDC */
-	mtsdram_as(SDRAM_RQDC, 0x80000038);
-
-	/* SDRAM_RFDC */
-	mtsdram_as(SDRAM_RFDC, 0x00000209);
-
-	/* Enable memory controller */
-	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+	mflr	r13
+	lis	r3,CFG_SDRAM_BASE at h
+	ori	r3,r3,CFG_SDRAM_BASE at l
+	lis	r4,(CFG_MBYTES_SDRAM << 20)@h
+	ori	r4,r4,(CFG_MBYTES_SDRAM << 20)@l
+	bl	ecc_init
+	mtlr	r13
+#endif /* defined(CONFIG_DDR_ECC) */
+#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+#endif /* !defined(CFG_INIT_DCACHE_CS) */
 
 	blr

index 39328c2..4def0d4 100644
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o cmd_pll.o memory.o
+COBJS	= $(BOARD).o cmd_pll.o
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

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