make section names compatible with -ffunction-sections -fdata-sections: ia64

PATCH In review Denys Vlasenko 1 participant 1 message Jul 1, 2008 Generic include/asm header files

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Denys Vlasenko

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2008-07-01 22:36 UTC #0 lore raw

PATCH 9/23 make section names compatible with -ffunction-sections -fdata-sections: ia64

The purpose of this patch is to make kernel buildable with "gcc -ffunction-sections -fdata-sections". This patch fixes ia64 architecture.

Signed-off-by Denys Vlasenko <[email protected]>

--
vda

arch/ia64/kernel/Makefile +1 -1

@@ -66,7 +66,7 @@
 $(obj)/gate-syms.o: $(obj)/gate.lds $(obj)/gate.o FORCE
 	$(call if_changed,gate)
 
-# gate-data.o contains the gate DSO image as data in section .data.gate.
+# gate-data.o contains the gate DSO image as data in section .gate..data
 # We must build gate.so before we can assemble it.
 # Note: kbuild does not track this dependency due to usage of .incbin
 $(obj)/gate-data.o: $(obj)/gate.so

arch/ia64/kernel/gate-data.S +1 -1

@@ -1,3 +1,3 @@
-	.section .data.gate, "aw"
+	.section .gate.data, "aw"
 
 	.incbin "arch/ia64/kernel/gate.so"

arch/ia64/kernel/gate.S +4 -4

@@ -20,18 +20,18 @@
  * to targets outside the shared object) and to avoid multi-phase kernel builds, we
  * simply create minimalistic "patch lists" in special ELF sections.
  */
-	.section ".data.patch.fsyscall_table", "a"
+	.section ".patch.fsyscall_table.data", "a"
 	.previous
 #define LOAD_FSYSCALL_TABLE(reg)			\
 [1:]	movl reg=0;					\
-	.xdata4 ".data.patch.fsyscall_table", 1b-.
+	.xdata4 ".patch.fsyscall_table.data", 1b-.
 
-	.section ".data.patch.brl_fsys_bubble_down", "a"
+	.section ".patch.brl_fsys_bubble_down.data", "a"
 	.previous
 #define BRL_COND_FSYS_BUBBLE_DOWN(pr)			\
 [1:](pr)brl.cond.sptk 0;				\
 	;;						\
-	.xdata4 ".data.patch.brl_fsys_bubble_down", 1b-.
+	.xdata4 ".patch.brl_fsys_bubble_down.data", 1b-.
 
 GLOBAL_ENTRY(__kernel_syscall_via_break)
 	.prologue

arch/ia64/kernel/gate.lds.S +5 -5

@@ -32,21 +32,21 @@
 	 */
 	. = GATE_ADDR + 0x600;
 
-	.data.patch		: {
+	.patch.data		: {
 		__start_gate_mckinley_e9_patchlist = .;
-		*(.data.patch.mckinley_e9)
+		*(.patch.mckinley_e9.data)
 		__end_gate_mckinley_e9_patchlist = .;
 
 		__start_gate_vtop_patchlist = .;
-		*(.data.patch.vtop)
+		*(.patch.vtop.data)
 		__end_gate_vtop_patchlist = .;
 
 		__start_gate_fsyscall_patchlist = .;
-		*(.data.patch.fsyscall_table)
+		*(.patch.fsyscall_table.data)
 		__end_gate_fsyscall_patchlist = .;
 
 		__start_gate_brl_fsys_bubble_down_patchlist = .;
-		*(.data.patch.brl_fsys_bubble_down)
+		*(.patch.brl_fsys_bubble_down.data)
 		__end_gate_brl_fsys_bubble_down_patchlist = .;
 	}						:readable

arch/ia64/kernel/head.S +1 -1

@@ -178,7 +178,7 @@
 halt_msg:
 	stringz "Halting kernel\n"
 
-	.section .text.head,"ax"
+	.section .head.text,"ax"
 
 	.global start_ap

arch/ia64/kernel/init_task.c +2 -2

@@ -28,7 +28,7 @@
  * Initial task structure.
  *
  * We need to make sure that this is properly aligned due to the way process stacks are
- * handled. This is done by having a special ".data.init_task" section...
+ * handled. This is done by having a special ".init_task.data" section...
  */
 #define init_thread_info	init_task_mem.s.thread_info

@@ -38,7 +38,7 @@
 		struct thread_info thread_info;
 	} s;
 	unsigned long stack[KERNEL_STACK_SIZE/sizeof (unsigned long)];
-} init_task_mem asm ("init_task") __attribute__((section(".data.init_task"))) = {{
+} init_task_mem asm ("init_task") __attribute__((section(".init_task.data"))) = {{
 	.task =		INIT_TASK(init_task_mem.s.task),
 	.thread_info =	INIT_THREAD_INFO(init_task_mem.s.task)
 }};

arch/ia64/kernel/ivt.S +1 -1

@@ -75,7 +75,7 @@
 	mov r19=n;;			/* prepare to save predicates */		\
 	br.sptk.many dispatch_to_fault_handler
 
-	.section .text.ivt,"ax"
+	.section .ivt.text,"ax"
 
 	.align 32768	// align on 32KB boundary
 	.global ia64_ivt

arch/ia64/kernel/minstate.h +2 -2

@@ -15,7 +15,7 @@
 #define ACCOUNT_SYS_ENTER
 #endif
 
-.section ".data.patch.rse", "a"
+.section ".patch.rse.data", "a"
 .previous
 
 /*

@@ -214,7 +214,7 @@
 (pUStk) extr.u r17=r18,3,6;			\
 (pUStk)	sub r16=r18,r22;			\
 [1:](pKStk)	br.cond.sptk.many 1f;		\
-	.xdata4 ".data.patch.rse",1b-.		\
+	.xdata4 ".patch.rse.data",1b-.		\
 	;;					\
 	cmp.ge p6,p7 = 33,r17;			\
 	;;					\

arch/ia64/kernel/vmlinux.lds.S +24 ~~-24~~

112 lines not on this page · raw message

arch/ia64/kvm/vmm_ivt.S +1 -1

@@ -97,7 +97,7 @@
 
 
 
-    .section .text.ivt,"ax"
+    .section .ivt.text,"ax"
 
     .align 32768    // align on 32KB boundary
     .global kvm_ia64_ivt

include/asm-ia64/asmmacro.h +6 -6

@@ -70,12 +70,12 @@
  * path (ivt.S - TLB miss processing) or in places where it might not be
  * safe to use a "tpa" instruction (mca_asm.S - error recovery).
  */
-	.section ".data.patch.vtop", "a"	// declare section & section attributes
+	.section ".patch.vtop.data", "a"	// declare section & section attributes
 	.previous
 
 #define	LOAD_PHYSICAL(pr, reg, obj)		\
 [1:](pr)movl reg = obj;				\
-	.xdata4 ".data.patch.vtop", 1b-.
+	.xdata4 ".patch.vtop.data", 1b-.
 
 /*
  * For now, we always put in the McKinley E9 workaround.  On CPUs that don't need it,

@@ -84,11 +84,11 @@
 #define DO_MCKINLEY_E9_WORKAROUND
 
 #ifdef DO_MCKINLEY_E9_WORKAROUND
-	.section ".data.patch.mckinley_e9", "a"
+	.section ".patch.mckinley_e9.data", "a"
 	.previous
 /* workaround for Itanium 2 Errata 9: */
 # define FSYS_RETURN					\
-	.xdata4 ".data.patch.mckinley_e9", 1f-.;	\
+	.xdata4 ".patch.mckinley_e9.data", 1f-.;	\
 1:{ .mib;						\
 	nop.m 0;					\
 	mov r16=ar.pfs;					\

@@ -107,11 +107,11 @@
  * If physical stack register size is different from DEF_NUM_STACK_REG,
  * dynamically patch the kernel for correct size.
  */
-	.section ".data.patch.phys_stack_reg", "a"
+	.section ".patch.phys_stack_reg.data", "a"
 	.previous
 #define LOAD_PHYS_STACK_REG_SIZE(reg)			\
 [1:]	adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0;	\
-	.xdata4 ".data.patch.phys_stack_reg", 1b-.
+	.xdata4 ".patch.phys_stack_reg.data", 1b-.
 
 /*
  * Up until early 2004, use of .align within a function caused bad unwind info.

include/asm-ia64/cache.h +1 -1

@@ -24,6 +24,6 @@
 # define SMP_CACHE_BYTES	(1 << 3)
 #endif
 
-#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+#define __read_mostly __attribute__((__section__(".read_mostly.data")))
 
 #endif /* _ASM_IA64_CACHE_H */

include/asm-ia64/percpu.h +1 -1

@@ -27,7 +27,7 @@
 
 #else /* ! SMP */
 
-#define PER_CPU_ATTRIBUTES	__attribute__((__section__(".data.percpu")))
+#define PER_CPU_ATTRIBUTES	__attribute__((__section__(".percpu.data")))
 
 #define per_cpu_init()				(__phys_per_cpu_start)