ppc4xx: Add initial 460SX reference board (redwood) config file and defines.
PATCH 2/3 ppc4xx: Add initial 460SX reference board (redwood) config file and defines.
From: Feng Kan <[email protected]>
Signed-off-by Feng Kan <[email protected]>
--- include/asm-ppc/ppc4xx-sdram.h | 3 +- include/asm-ppc/processor.h | 4 + include/configs/redwood.h | 186 ++++++++++++++++++++++++++++++++++++++++ include/ppc440.h | 20 +++-- include/ppc4xx.h | 3 +- 5 files changed, 207 insertions(+), 9 deletions(-) create mode 100644 include/configs/redwood.h
include/asm-ppc/ppc4xx-sdram.h +2 -1
@@ -282,7 +282,8 @@* Memory Bank 0-7 configuration */ #if defined(CONFIG_440SPE ) || \ - defined(CONFIG_460EX ) || defined(CONFIG_460GT ) + defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX )#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000/* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE (n) ((((u32)(n))&0xFFE00000)>>2)#define SDRAM_RXBAS_SDBA_DECODE (n) ((((u32)(n))&0xFFE00000)<<2)
include/asm-ppc/processor.h +4 -0
@@ -810,6 +810,10 @@#define PVR_460EX_RA 0x130218A3/* 460EX rev A without Security Engine */ #define PVR_460GT_SE_RA 0x130218A0/* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1/* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800/* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801/* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802/* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803/* 460GX rev A Variant 1 Security disabled */ #define PVR_601 0x00010000#define PVR_602 0x00050000#define PVR_603 0x00030000
include/configs/redwood.h new file +186 -0
186 lines not on this page · raw message
include/ppc440.h +13 -7
@@ -749,7 +749,8 @@+----------------------------------------------------------------------------*/ #if defined (CONFIG_440GX ) || \ defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) || \ - defined(CONFIG_460EX ) || defined(CONFIG_460GT ) + defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX )#define L2_CACHE_BASE 0x030#define l2_cache_cfg (L2_CACHE_BASE+0x00)/* L2 Cache Config */ #define l2_cache_cmd (L2_CACHE_BASE+0x01)/* L2 Cache Command */
@@ -837,7 +838,8 @@/*----------------------------------------------------------------------------- | Clocking, Power Management and Chip Control +----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX ) || defined(CONFIG_460GT ) +#if defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX )#define CNTRL_DCR_BASE 0x160#else #define CNTRL_DCR_BASE 0x0b0
@@ -896,7 +898,8 @@#if defined(CONFIG_440SPE ) || \ defined(CONFIG_440EPX ) || defined(CONFIG_440GRX ) || \ - defined(CONFIG_460EX ) || defined(CONFIG_460GT ) + defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX )#define UIC2_DCR_BASE 0xe0#define uic2sr (UIC2_DCR_BASE+0x0)/* UIC2 status-Read Clear */ #define uic2srs (UIC2_DCR_BASE+0x1)/* UIC2 status-Read Set */
@@ -1608,7 +1611,8 @@#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) -#elif defined(CONFIG_460EX ) || defined(CONFIG_460GT ) +#elif defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX )#define UICB0_UIC1NCI 0x00000002/* UIC1 Noncritical Interrupt */ #define UICB0_UIC1CI 0x00000001/* UIC1 Critical Interrupt */
@@ -1855,7 +1859,7 @@#define SDR0_DDR0_TUNE_DECODE (n) ((((unsigned long)(n))>>0)&0x2FF)#endif -#if defined(CONFIG_440SPE ) +#if defined(CONFIG_440SPE ) || defined(CONFIG_460SX )#define SDR0_CP440 0x0180#define SDR0_CP440_ERPN_MASK 0x30000000#define SDR0_CP440_ERPN_MASK_HI 0x3000
@@ -2793,7 +2797,8 @@/*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX ) || defined(CONFIG_460GT ) +#if defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX )#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0/* Fwd Div A */ #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f/* Fwd Div B */ #define PLLSYS0_FB_DIV_MASK 0x0000ff00/* Feedback divisor */
@@ -3145,7 +3150,8 @@* GPIO macro register defines ******************************************************************************/ #if defined(CONFIG_440GP ) || defined(CONFIG_440GX ) || \ - defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) + defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) || \ + defined(CONFIG_460SX )#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)#define GPIO0_OR (GPIO0_BASE+0x0)
include/ppc4xx.h +2 -1
@@ -41,7 +41,8 @@#if defined(CONFIG_405EX ) || \ defined(CONFIG_440SP ) || defined(CONFIG_440SPE ) || \ - defined(CONFIG_460EX ) || defined(CONFIG_460GT ) + defined(CONFIG_460EX ) || defined(CONFIG_460GT ) || \ + defined(CONFIG_460SX )#define CONFIG_SDRAM_PPC4xx_IBM_DDR2/* IBM DDR(2) controller */ #endif
Signature · 1 line
1.5.6.1
PATCH 2/3 ppc4xx: Add initial 460SX reference board (redwood) config file and defines.
Quoted 3 lines · fkan at amcc.com
From: Feng Kan <[email protected]>
Signed-off-by Feng Kan <[email protected]>
Applied to "next" branch in u-boot-ppc4xx repository. Thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================