PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)

While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in the 405EX(r), SDRAM_MCSTAT has a different DCR value.

Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF which causes SDRAM initialization to periodically fail since it can prematurely indicate SDRAM ready status.

---
 include/asm-ppc/ppc4xx-sdram.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

index 8a064df..b528497 100644
@@ -353,8 +353,11 @@
 /*
  * Memory controller registers
  */
+#ifndef CONFIG_405EX
 #define SDRAM_MCSTAT	0x14	/* memory controller status                  */
+#else
+#define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
+#endif
 #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
 #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
 #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
--

1.5.4.4

Applied to "next" branch in u-boot-ppc4xx repository. Thanks.

Best regards,
Stefan

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