Add Apollon (OMAP24xx) board support

Add apollon (OMAP24xx) board support
Also fix some GPMC offset handling
Add board descriptions

Signed-off-by Kyungmin Park <[email protected]>

---

hw/boards.h +1 -0

index 22ac332..7043ea7 100644
@@ -88,6 +88,7 @@ extern QEMUMachine palmte_machine;
 /* nseries.c */
 extern QEMUMachine n800_machine;
 extern QEMUMachine n810_machine;
+extern QEMUMachine apollon_machine;
 
 /* gumstix.c */
 extern QEMUMachine connex_machine;

hw/nseries.c +39 -0

index 5e9d8f7..98c5a68 100644
@@ -31,6 +31,7 @@
 #include "devices.h"
 #include "flash.h"
 #include "hw.h"
+#include "net.h"
 
 /* Nokia N8x0 support */
 struct n800_s {

@@ -1312,6 +1313,12 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
       will set the size once configured, so this just sets an initial
       size until the guest activates the display.  */
    dpy_resize(ds, 800, 480);
+
+    if (model == 801) {
+        /* Interrupt line of NIC is connected to GPIO line 74 */
+        smc91c111_init(&nd_table[0], 0x08000300,
+                   omap2_gpio_in_get(s->cpu->gpif, 74)[0]);
+    }
 }
 
 static struct arm_boot_info n800_binfo = {

@@ -1333,6 +1340,14 @@ static struct arm_boot_info n810_binfo = {
    .atag_board = n810_atag_setup,
 };
 
+static struct arm_boot_info apollon_binfo = {
+    .loader_start = OMAP2_Q2_BASE,
+    /* Actually two chips of 0x4000000 bytes each */
+    .ram_size = 0x08000000,
+    .board_id = 0x397,
+    .atag_board = n800_atag_setup,
+};
+
 static void n800_init(ram_addr_t ram_size, int vga_ram_size,
                const char *boot_device, DisplayState *ds,
                const char *kernel_filename, const char *kernel_cmdline,

@@ -1353,6 +1368,23 @@ static void n810_init(ram_addr_t ram_size, int vga_ram_size,
                    cpu_model, &n810_binfo, 810);
 }
 
+static void apollon_init(ram_addr_t ram_size, int vga_ram_size,
+                const char *boot_device, DisplayState *ds,
+                const char *kernel_filename, const char *kernel_cmdline,
+                const char *initrd_filename, const char *cpu_model)
+{
+    uint32_t config7;
+
+    n8x0_init(ram_size, boot_device, ds,
+                    kernel_filename, kernel_cmdline, initrd_filename,
+                    cpu_model, &apollon_binfo, 801);
+
+    /* Set GPMC1 for ethernet at apollon */
+    config7 = 0x00000F40 | (0x08000000 >> 24);
+    cpu_physical_memory_write(0x6800a0a8,              /* GPMC_CONFIG7_1 */
+                    (void *) &config7, sizeof(config7));
+}
+
 QEMUMachine n800_machine = {
    "n800",
    "Nokia N800 tablet aka. RX-34 (OMAP2420)",

@@ -1366,3 +1398,10 @@ QEMUMachine n810_machine = {
    n810_init,
    (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED,
 };
+
+QEMUMachine apollon_machine = {
+    "apollon",
+    "Samsung Apollon (OMAP2420)",
+    apollon_init,
+    (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED,
+};

hw/omap2.c +53 -2

index fa7b35c..84d2180 100644
@@ -3528,6 +3528,32 @@ struct omap_sysctl_s {
    uint32_t msuspendmux[5];
 };
 
+static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
+{
+
+    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+    int offset = addr - s->base;
+    int pad_offset, byte_offset;
+    int value;
+
+    switch (offset) {
+    case 0x030 ... 0x140:      /* CONTROL_PADCONF - only used in the POP */
+        pad_offset = (offset - 0x30) >> 2;
+        byte_offset = (offset - 0x30) & (4 - 1);
+
+        value = s->padconf[pad_offset];
+        value = (value >> (byte_offset * 8)) & 0xff;
+
+        return value;
+
+    default:
+        break;
+    }
+
+    OMAP_BAD_REG(addr);
+    return 0;
+}
+
 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
 {
    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;

@@ -3629,6 +3655,31 @@ static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
    return 0;
 }
 
+static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
+                uint32_t value)
+{
+    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+    int offset = addr - s->base;
+    int pad_offset, byte_offset;
+    int prev_value;
+
+    switch (offset) {
+    case 0x030 ... 0x140:      /* CONTROL_PADCONF - only used in the POP */
+        pad_offset = (offset - 0x30) >> 2;
+        byte_offset = (offset - 0x30) & (4 - 1);
+
+        prev_value = s->padconf[pad_offset];
+        prev_value &= ~(0xff << (byte_offset * 8));
+        prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
+        s->padconf[pad_offset] = prev_value;
+        break;
+
+    default:
+        OMAP_BAD_REG(addr);
+        break;
+    }
+}
+
 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
                uint32_t value)
 {

@@ -3726,13 +3777,13 @@ static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
 }
 
 static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
-    omap_badwidth_read32,      /* TODO */
+    omap_sysctl_read8,
    omap_badwidth_read32,      /* TODO */
    omap_sysctl_read,
 };
 
 static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
-    omap_badwidth_write32,     /* TODO */
+    omap_sysctl_write8,
    omap_badwidth_write32,     /* TODO */
    omap_sysctl_write,
 };

hw/omap2.c +1 -1

    case 0x84: /* SDRC_MR_0 */
    case 0x88: /* SDRC_EMR1_0 */
    case 0x8c: /* SDRC_EMR2_0 */

@@ -4139,7 +4194,7 @@ static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
        cs = (offset - 0x060) / 0x30;
        offset -= cs * 0x30;
        f = s->cs_file + cs;
-        switch (offset - cs * 0x30) {
+        switch (offset) {
            case 0x60: /* GPMC_CONFIG1 */
                return f->config[0];
            case 0x64: /* GPMC_CONFIG2 */

qemu-doc.texi +4 -0

index eb29a9f..d4f6d22 100644
@@ -88,6 +88,7 @@ For system emulation, the following hardware targets are supported:
 @item Arnewsh MCF5206 evaluation board (ColdFire V2).
 @item Palm Tungsten|E PDA (OMAP310 processor)
 @item N800 and N810 tablets (OMAP2420 processor)
+@item Samsung apollon OneNAND board (OMAP2420 processor)
 @item MusicPal (MV88W8618 ARM processor)
 @end itemize
 

@@ -2604,6 +2605,29 @@ Nokia RETU and TAHVO multi-purpose chips with an RTC, connected
 through CBUS
 @end itemize
 
+Samsung Apollon OneNAND development board emulation supports the following elements:
+@itemize @minus
+@item

Quoted 5 lines

hw/omap2.c +1 -0

@@ -3875,7 +3926,11 @@ static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
    case 0x68: /* SDRC_DLLB_CTRL */
    case 0x6c: /* SDRC_DLLB_STATUS */
    case 0x70: /* SDRC_POWER */
+         return 0x00;

hw/omap2.c static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) · line 3933

Quoted 4 lines

hw/omap2.c +3 -0

+
    case 0x80: /* SDRC_MCFG_0 */
+         return 0x4000;
+

This should be made writable (default value is 0) and the bootloader or the board file (hw/nseries.c) needs to write the correct value there.

Would there be much redundancy if apollon setup was in a separate file?

The latter two don't seem to be supported in this patch. OMAP2 on-chip lcdc will require a bit of work to be usable.

qemu-doc.texi Nokia RETU and TAHVO multi-purpose chips with an RTC, connected · line 2626

Quoted 7 lines

qemu-doc.texi +6 -0

+@item
+Secure Digital card connected to OMAP MMC/SD host
+@item
+One OMAP on-chip UARTs
+@item
+External USB transceiver chip connected to USB controller embedded in a TI

(TUSB6010 chip?)

Quoted 3 lines

+@item
+Three GPIO switches and GPIO indicate LEDs

This isn't in the patch either.

I'll commit the omap GPMC improvements for the moment.

Quoted 5 lines

Quoted 5 lines

hw/omap2.c +1 -0

@@ -3875,7 +3926,11 @@ static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
    case 0x68: /* SDRC_DLLB_CTRL */
    case 0x6c: /* SDRC_DLLB_STATUS */
    case 0x70: /* SDRC_POWER */
+         return 0x00;

Quoted 8 lines

hw/omap2.c static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) · line 3933

Quoted 4 lines

hw/omap2.c +3 -0

+
    case 0x80: /* SDRC_MCFG_0 */
+         return 0x4000;
+

This should be made writable (default value is 0) and the bootloader or the board file (hw/nseries.c) needs to write the correct value there.

Agreed, apollon and omap2420h4 read this value at bootloader, Yes it's meanless in qemu.
it's seted at initial bootloader, but it's not in qemu. If sdrc has array value, we can read it

Quoted 3 lines

Would there be much redundancy if apollon setup was in a separate file?

Yes, as you see almost same as n800.

Quoted 4 lines

The latter two don't seem to be supported in this patch. OMAP2 on-chip lcdc will require a bit of work to be usable.

It's initial support we need to work more to support full peripherals.

Quoted 9 lines

qemu-doc.texi Nokia RETU and TAHVO multi-purpose chips with an RTC, connected · line 2626

Quoted 7 lines

qemu-doc.texi +6 -0

+@item
+Secure Digital card connected to OMAP MMC/SD host
+@item
+One OMAP on-chip UARTs
+@item
+External USB transceiver chip connected to USB controller embedded in a TI

(TUSB6010 chip?)

actually ISP1105W.

Quoted 4 lines

Quoted 3 lines

+@item
+Three GPIO switches and GPIO indicate LEDs

Quoted 4 lines

This isn't in the patch either.

I'll commit the omap GPMC improvements for the moment.

same as above.

If you don't mind I want to add mentioned devices later

2008/7/25 Kyungmin Park <[email protected]>:

Quoted 14 lines

Quoted 5 lines

Quoted 5 lines

hw/omap2.c +1 -0

@@ -3875,7 +3926,11 @@ static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
    case 0x68: /* SDRC_DLLB_CTRL */
    case 0x6c: /* SDRC_DLLB_STATUS */
    case 0x70: /* SDRC_POWER */
+         return 0x00;

Quoted 8 lines

hw/omap2.c static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) · line 3933

Quoted 4 lines

hw/omap2.c +3 -0

+
    case 0x80: /* SDRC_MCFG_0 */
+         return 0x4000;
+

This should be made writable (default value is 0) and the bootloader or the board file (hw/nseries.c) needs to write the correct value there.

Quoted 4 lines

Agreed, apollon and omap2420h4 read this value at bootloader, Yes it's meanless in qemu.
it's seted at initial bootloader, but it's not in qemu. If sdrc has array value, we can read it

I mean something like

   uint32_t mcfg0 = (boot_info.ram_size / 0x200000) << 8;        /* RAMSIZE */

   cpu_physical_memory_write(0x68009080,     /* SDRC_MCFG_0 */
                   (void *) &mcfg0, sizeof(mcfg0));

Quoted 5 lines

Quoted 3 lines

Would there be much redundancy if apollon setup was in a separate file?

Yes, as you see almost same as n800.

It seems apollon only uses n8x0_init, n8x0_nand_setup and n8x0_usb_setup, everything else is nseries-specific. (plus maybe the menelaus chip on i2c)

Quoted 28 lines

Quoted 5 lines

The latter two don't seem to be supported in this patch. OMAP2 on-chip lcdc will require a bit of work to be usable.

It's initial support we need to work more to support full peripherals.

Quoted 9 lines

qemu-doc.texi Nokia RETU and TAHVO multi-purpose chips with an RTC, connected · line 2626

Quoted 7 lines

+@item

qemu-doc.texi +5 -0

+Secure Digital card connected to OMAP MMC/SD host
+@item
+One OMAP on-chip UARTs
+@item
+External USB transceiver chip connected to USB controller embedded in a TI

(TUSB6010 chip?)

actually ISP1105W.

Quoted 8 lines

Quoted 3 lines

+@item
+Three GPIO switches and GPIO indicate LEDs

This isn't in the patch either.

I'll commit the omap GPMC improvements for the moment.

Quoted 3 lines

same as above.

If you don't mind I want to add mentioned devices later

You don't have to add them, but they shouldn't be listed in qemu-doc.texi before they are supported.