ath9k: Replace KASSERT() with BUG_ON()

index bfb1967..855cda4 100644
@@ -399,8 +399,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 					avp->av_bslot = slot;
 					/* NB: keep looking for a double slot */
 				}
-			KASSERT(sc->sc_bslot[avp->av_bslot] == ATH_IF_ID_ANY,
-				("beacon slot %u not empty?", avp->av_bslot));
+			BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY);
 			sc->sc_bslot[avp->av_bslot] = if_id;
 			sc->sc_nbcnvaps++;
 		}

index e6c0c17..56cc8a9 100644
@@ -65,7 +65,7 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
 
 	memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
 	rt = sc->sc_rates[mode];
-	KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
+	BUG_ON(!rt);
 
 	for (i = 0; i < rt->rateCount; i++)
 		sc->sc_rixmap[rt->info[i].rateCode] = (u_int8_t) i;

index 94dbac9..6c17088 100644
@@ -79,13 +79,6 @@ struct ath_node;
 		}				\
 	} while (0)
 
-#define KASSERT(exp, msg) do {			\
-		if (unlikely(!(exp))) {         \
-			printk msg;		\
-			BUG();			\
-		}				\
-	} while (0)
-
 /* XXX: remove */
 #define memzero(_buf, _len) memset(_buf, 0, _len)
 

index 6374bf8..4039a98 100644
@@ -284,7 +284,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
 	fc = hdr->frame_control;
 
 	rt = sc->sc_currates;
-	KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
+	BUG_ON(!rt);
 
 	/* Fill misc fields */
 

@@ -781,7 +781,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 * use RTS.
 	 */
 	if (sc->sc_hashtsupport && bf->bf_isdata) {
-		KASSERT(an != NULL, ("an == null"));
+		BUG_ON(!an);
 		/*
 		 * 802.11g protection not needed, use our default behavior
 		 */

@@ -829,7 +829,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 * in whether or not a short preamble is to be used.
 	 */
 	/* NB: cix is set above where RTS/CTS is enabled */
-	KASSERT(cix != 0xff, ("cix not setup"));
+	BUG_ON(cix == 0xff);
 	ctsrate = rt->info[cix].rateCode |
 		(bf->bf_shpreamble ? rt->info[cix].shortPreamble : 0);
 

index ed440a0..3352617 100644
@@ -1059,11 +1059,6 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
 			   const struct hal_node_stats *stats);
 enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set);
 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
-enum hal_bool ath9k_hw_setupxtxdesc(struct ath_hal *ah,
-				    struct ath_desc *ds,
-				    u_int txRate1, u_int txTries1,
-				    u_int txRate2, u_int txTries2,
-				    u_int txRate3, u_int txTries3);
 enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah);
 enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
 enum hal_bool ath9k_hw_getcapability(struct ath_hal *ah,

index 56cc8a9..5752467 100644
@@ -1162,17 +1162,6 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit;
 
 	/*
-	 * Check if the MAC has multi-rate retry support.
-	 * We do this by trying to setup a fake extended
-	 * descriptor.  MAC's that don't have support will
-	 * return false w/o doing anything.  MAC's that do
-	 * support it will return true w/o doing anything.
-	 *
-	 *  XXX This is lame.  Just query a hal property, Luke!
-	 */
-	sc->sc_mrretry = ath9k_hw_setupxtxdesc(ah, NULL, 0, 0, 0, 0, 0, 0);
-
-	/*
 	 * Check if the device has hardware counters for PHY
 	 * errors.  If so we need to enable the MIB interrupt
 	 * so we can act on stat triggers.

index 6c17088..b6a6373 100644
@@ -945,7 +945,6 @@ struct ath_softc {
 	/* Properties, Config */
 	unsigned int
 		sc_invalid             : 1, /* being detached */
-		sc_mrretry             : 1, /* multi-rate retry support */
 		sc_needmib             : 1, /* enable MIB stats intr */
 		sc_hasdiversity        : 1, /* rx diversity available */
 		sc_diversity           : 1, /* enable rx diversity */

index b99e29b..91ba3e4 100644
@@ -7833,30 +7833,6 @@ void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs)
 }
 
 enum hal_bool
-ath9k_hw_setupxtxdesc(struct ath_hal *ah, struct ath_desc *ds,
-		      u_int txRate1, u_int txTries1,
-		      u_int txRate2, u_int txTries2,
-		      u_int txRate3, u_int txTries3)
-{
-	struct ar5416_desc *ads = AR5416DESC(ds);
-
-	if (txTries1) {
-		ads->ds_ctl2 |= AR_DurUpdateEna;
-		ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1);
-		ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
-	}
-	if (txTries2) {
-		ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2);
-		ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
-	}
-	if (txTries3) {
-		ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3);
-		ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
-	}
-	return AH_TRUE;
-}
-
-enum hal_bool
 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
 		    u_int segLen, enum hal_bool firstSeg,
 		    enum hal_bool lastSeg, const struct ath_desc *ds0)

index 855cda4..b2f44b1 100644
@@ -709,27 +709,6 @@ void ath9k_beacon_tasklet(unsigned long data)
 	} else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
 		ath_setslottime(sc);        /* commit change to hardware */
 
-	if ((!sc->sc_stagbeacons || slot == 0) && (!sc->sc_diversity)) {
-		int otherant;
-		/*
-		 * Check recent per-antenna transmit statistics and flip
-		 * the default rx antenna if noticeably more frames went out
-		 * on the non-default antenna.  Only do this if rx diversity
-		 * is off.
-		 * XXX assumes 2 anntenae
-		 */
-		otherant = sc->sc_defant & 1 ? 2 : 1;
-		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] +
-			ATH_ANTENNA_DIFF) {
-			DPRINTF(sc, ATH_DEBUG_BEACON,
-				"%s: flip defant to %u, %u > %u\n",
-				__func__, otherant, sc->sc_ant_tx[otherant],
-				sc->sc_ant_tx[sc->sc_defant]);
-			ath_setdefantenna(sc, otherant);
-		}
-		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
-	}
-
 	if (bfaddr != 0) {
 		/*
 		 * Stop any current dma and put the new frame(s) on the queue.

index 5752467..47d4891 100644
@@ -834,7 +834,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
 	 * Enable MIB interrupts when there are hardware phy counters.
 	 * Note we only do this (at the moment) for station mode.
 	 */
-	if (sc->sc_needmib &&
+	if (ath9k_hw_phycounters(ah) &&
 	    ((sc->sc_opmode == HAL_M_STA) || (sc->sc_opmode == HAL_M_IBSS)))
 		sc->sc_imask |= HAL_INT_MIB;
 	/*

@@ -1161,14 +1161,6 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	/* Get the chipset-specific aggr limit. */
 	sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit;
 
-	/*
-	 * Check if the device has hardware counters for PHY
-	 * errors.  If so we need to enable the MIB interrupt
-	 * so we can act on stat triggers.
-	 */
-	if (ath9k_hw_phycounters(ah))
-		sc->sc_needmib = 1;
-
 	/* Get the hardware key cache size. */
 	sc->sc_keymax = ah->ah_caps.halKeyCacheSize;
 	if (sc->sc_keymax > ATH_KEYMAX) {

@@ -1354,21 +1346,8 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	sc->sc_rxchaindetect_delta5GHz = 30;
 	sc->sc_rxchaindetect_delta2GHz = 30;
 
-	/*
-	 * Query the hal about antenna support
-	 * Enable rx fast diversity if hal has support
-	 */
-	if (ath9k_hw_getcapability(ah, HAL_CAP_DIVERSITY, 0, NULL)) {
-		sc->sc_hasdiversity = 1;
-		ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
-			1, AH_TRUE, NULL);
-		sc->sc_diversity = 1;
-	} else {
-		sc->sc_hasdiversity = 0;
-		sc->sc_diversity = 0;
-		ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
-			1, AH_FALSE, NULL);
-	}
+	ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, AH_TRUE, NULL);
+
 	sc->sc_defant = ath9k_hw_getdefantenna(ah);
 
 	/*

index b6a6373..0995c6e 100644
@@ -944,10 +944,7 @@ struct ath_softc {
 
 	/* Properties, Config */
 	unsigned int
-		sc_invalid             : 1, /* being detached */
-		sc_needmib             : 1, /* enable MIB stats intr */
-		sc_hasdiversity        : 1, /* rx diversity available */
-		sc_diversity           : 1, /* enable rx diversity */
+		sc_invalid,	/* being detached */
 		sc_hasveol             : 1, /* tx VEOL support */
 		sc_beacons             : 1, /* beacons running */
 		sc_hasbmask            : 1, /* bssid mask support */

index 91ba3e4..ab52647 100644
@@ -6701,15 +6701,9 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 	case HAL_CAP_PHYCOUNTERS:
 		return ahp->ah_hasHwPhyCounters ? HAL_OK : HAL_ENXIO;
 	case HAL_CAP_DIVERSITY:
-		switch (capability) {
-		case 0:
-			return AH_TRUE;
-		case 1:
-			return (REG_READ(ah, AR_PHY_CCK_DETECT) &
-				AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
-				AH_TRUE : AH_FALSE;
-		}
-		return AH_FALSE;
+		return (REG_READ(ah, AR_PHY_CCK_DETECT) &
+			AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
+			AH_TRUE : AH_FALSE;
 	case HAL_CAP_PHYDIAG:
 		return AH_TRUE;
 	case HAL_CAP_MCAST_KEYSRCH:

index 7ca0ef9..2446c00 100644
@@ -1110,20 +1110,18 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 		type = ath_rx_indicate(sc, skb,
 			&rx_status, ds->ds_rxstat.rs_keyix);
 
-		if (sc->sc_diversity) {
-			/*
-			 * When using hardware fast diversity, change the
-			 * default rx antenna if rx diversity chooses the
-			 * other antenna 3 times in a row.
-			 */
-			if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
-				if (++sc->sc_rxotherant >= 3)
-					ath_setdefantenna(sc,
-						  ds->ds_rxstat.rs_antenna);
-			} else {
-				sc->sc_rxotherant = 0;
-			}
+		/*
+		 * change the default rx antenna if rx diversity chooses the
+		 * other antenna 3 times in a row.
+		 */
+		if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
+			if (++sc->sc_rxotherant >= 3)
+				ath_setdefantenna(sc,
+						ds->ds_rxstat.rs_antenna);
+		} else {
+			sc->sc_rxotherant = 0;
 		}
+
 		/*
 		 * redo antenna detection for Lenovo devices
 		 */

index 4039a98..127204c 100644
@@ -1257,7 +1257,6 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 	struct sk_buff *skb;
 	struct ieee80211_tx_info *tx_info;
 	struct ath_tx_info_priv *tx_info_priv;
-	u_int8_t txant;
 	int nacked, txok, nbad = 0, isrifs = 0;
 	enum hal_status status;
 

@@ -1345,10 +1344,6 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 			spin_unlock_bh(&sc->sc_txbuflock);
 		}
 
-		if (txok) {
-			txant = ds->ds_txstat.ts_antenna;
-			sc->sc_ant_tx[txant]++;
-		}
 		if (!bf->bf_isampdu) {
 			/*
 			 * This frame is sent out as a single frame.

index 3352617..0c58bb9 100644
@@ -913,7 +913,7 @@ struct ath_hal {
 	u_int32_t ah_magic;
 	u_int16_t ah_devid;
 	u_int16_t ah_subvendorid;
-	void *ah_sc;
+	struct ath_softc *ah_sc;
 	void __iomem *ah_sh;
 	u_int16_t ah_countryCode;
 	u_int32_t ah_macVersion;

@@ -999,7 +999,9 @@ enum hal_status ath_hal_getcapability(struct ath_hal *ah,
 const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
 						   u_int mode);
 void ath9k_hw_detach(struct ath_hal *ah);
-struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
+struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+				struct ath_softc *sc,
+				void __iomem *mem,
 				enum hal_status *error);
 enum hal_bool ath9k_regd_init_channels(struct ath_hal *ah,
 				       struct hal_channel *chans,

index ab52647..f1f7265 100644
@@ -1173,7 +1173,8 @@ static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
 }
 
 
-static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
+static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
+					      struct ath_softc *sc,
 					      void __iomem *mem,
 					      enum hal_status *status)
 {

@@ -3240,7 +3241,8 @@ enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
 	return status;
 }
 
-static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
+static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
+					  struct ath_softc *sc,
 					  void __iomem *mem,
 					  enum hal_status *status)
 {

@@ -8317,7 +8319,9 @@ const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid)
 		ath9k_hw_devname(devid) : NULL;
 }
 
-struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
+struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+				struct ath_softc *sc,
+				void __iomem *mem,
 				enum hal_status *error)
 {
 	struct ath_hal *ah = NULL;

index 0c58bb9..24dad48 100644
@@ -32,19 +32,19 @@
 #define	AR_SUBVENDOR_ID_NOG	0x0e11
 #define AR_SUBVENDOR_ID_NEW_A	0x7065
 
-#define	HAL_TXERR_XRETRY        0x01
-#define	HAL_TXERR_FILT	        0x02
-#define	HAL_TXERR_FIFO		0x04
-#define HAL_TXERR_XTXOP		0x08
-#define HAL_TXERR_TIMER_EXPIRED 0x10
-
-#define HAL_TX_BA               0x01
-#define HAL_TX_PWRMGMT          0x02
-#define HAL_TX_DESC_CFG_ERR     0x04
-#define HAL_TX_DATA_UNDERRUN    0x08
-#define HAL_TX_DELIM_UNDERRUN   0x10
-#define HAL_TX_SW_ABORTED       0x40
-#define HAL_TX_SW_FILTERED      0x80
+#define ATH9K_TXERR_XRETRY         0x01
+#define ATH9K_TXERR_FILT           0x02
+#define ATH9K_TXERR_FIFO           0x04
+#define ATH9K_TXERR_XTXOP          0x08
+#define ATH9K_TXERR_TIMER_EXPIRED  0x10
+
+#define ATH9K_TX_BA                0x01
+#define ATH9K_TX_PWRMGMT           0x02
+#define ATH9K_TX_DESC_CFG_ERR      0x04
+#define ATH9K_TX_DATA_UNDERRUN     0x08
+#define ATH9K_TX_DELIM_UNDERRUN    0x10
+#define ATH9K_TX_SW_ABORTED        0x40
+#define ATH9K_TX_SW_FILTERED       0x80
 
 #define NBBY    8
 #ifndef howmany

@@ -102,19 +102,19 @@ struct ath_rx_status {
 	u_int32_t evm2;
 };
 
-#define	HAL_RXERR_CRC		0x01
-#define	HAL_RXERR_PHY		0x02
-#define	HAL_RXERR_FIFO		0x04
-#define	HAL_RXERR_DECRYPT	0x08
-#define	HAL_RXERR_MIC		0x10
+#define ATH9K_RXERR_CRC           0x01
+#define ATH9K_RXERR_PHY           0x02
+#define ATH9K_RXERR_FIFO          0x04
+#define ATH9K_RXERR_DECRYPT       0x08
+#define ATH9K_RXERR_MIC           0x10
 
-#define HAL_RX_MORE             0x01
-#define HAL_RX_MORE_AGGR        0x02
-#define HAL_RX_GI               0x04
-#define HAL_RX_2040             0x08
-#define HAL_RX_DELIM_CRC_PRE    0x10
-#define HAL_RX_DELIM_CRC_POST   0x20
-#define HAL_RX_DECRYPT_BUSY     0x40
+#define ATH9K_RX_MORE             0x01
+#define ATH9K_RX_MORE_AGGR        0x02
+#define ATH9K_RX_GI               0x04
+#define ATH9K_RX_2040             0x08
+#define ATH9K_RX_DELIM_CRC_PRE    0x10
+#define ATH9K_RX_DELIM_CRC_POST   0x20
+#define ATH9K_RX_DECRYPT_BUSY     0x40
 
 enum hal_bool {
 	AH_FALSE = 0,

@@ -645,9 +645,9 @@ struct hal_country_entry {
 #define HAL_DBG_BEACON          0x00080000
 #define HAL_DBG_KEYCACHE        0x00100000
 #define HAL_DBG_POWER_MGMT      0x00200000
-#define HAL_DBG_MALLOC		0x00400000
-#define HAL_DBG_POWER_OVERRIDE	0x01000000
-#define HAL_DBG_SPUR_MITIGATE	0x02000000
+#define HAL_DBG_MALLOC          0x00400000
+#define HAL_DBG_POWER_OVERRIDE  0x01000000
+#define HAL_DBG_SPUR_MITIGATE   0x02000000
 #define HAL_DBG_UNMASKABLE      0xFFFFFFFF
 
 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)

index 0995c6e..6acf3a6 100644
@@ -611,7 +611,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
 #define ATH_DS_BA_SEQ(_ds)               ((_ds)->ds_us.tx.ts_seqnum)
 #define ATH_DS_BA_BITMAP(_ds)            (&(_ds)->ds_us.tx.ba_low)
-#define ATH_DS_TX_BA(_ds)                ((_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
+#define ATH_DS_TX_BA(_ds)	((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 #define ATH_AN_2_TID(_an, _tidno)        (&(_an)->an_aggr.tx.tid[(_tidno)])
 
 enum ATH_AGGR_STATUS {

index f1f7265..71f6574 100644
@@ -7881,28 +7881,28 @@ ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
 	ds->ds_txstat.ts_flags = 0;
 
 	if (ads->ds_txstatus1 & AR_ExcessiveRetries)
-		ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
 	if (ads->ds_txstatus1 & AR_Filtered)
-		ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
 	if (ads->ds_txstatus1 & AR_FIFOUnderrun)
-		ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
 	if (ads->ds_txstatus9 & AR_TxOpExceeded)
-		ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
 	if (ads->ds_txstatus1 & AR_TxTimerExpired)
-		ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
+		ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
 
 	if (ads->ds_txstatus1 & AR_DescCfgErr)
-		ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
+		ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
 	if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
-		ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
+		ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
 		ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
 	}
 	if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
-		ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
+		ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
 		ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
 	}
 	if (ads->ds_txstatus0 & AR_TxBaStatus) {
-		ds->ds_txstat.ts_flags |= HAL_TX_BA;
+		ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
 		ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
 		ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
 	}

@@ -8206,31 +8206,31 @@ ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
 		(ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
 	ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
 	ds->ds_rxstat.rs_flags =
-		(ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
+		(ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
 	ds->ds_rxstat.rs_flags |=
-		(ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
+		(ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
 
 	if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
-		ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_PRE;
+		ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
 	if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
-		ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_POST;
+		ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
 	if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
-		ds->ds_rxstat.rs_flags |= HAL_RX_DECRYPT_BUSY;
+		ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
 
 	if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
 
 		if (ads.ds_rxstatus8 & AR_CRCErr)
-			ds->ds_rxstat.rs_status |= HAL_RXERR_CRC;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
 		else if (ads.ds_rxstatus8 & AR_PHYErr) {
 			u_int phyerr;
 
-			ds->ds_rxstat.rs_status |= HAL_RXERR_PHY;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
 			phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
 			ds->ds_rxstat.rs_phyerr = phyerr;
 		} else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
-			ds->ds_rxstat.rs_status |= HAL_RXERR_DECRYPT;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
 		else if (ads.ds_rxstatus8 & AR_MichaelErr)
-			ds->ds_rxstat.rs_status |= HAL_RXERR_MIC;
+			ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
 	}
 
 	return HAL_OK;

index ccd599a..1114c32 100644
@@ -1652,7 +1652,7 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
 
 	avp = rc_priv->avp;
 	if ((avp->av_config.av_fixed_rateset != IEEE80211_FIXED_RATE_NONE)
-			|| info_priv->tx.ts_status & HAL_TXERR_FILT)
+			|| info_priv->tx.ts_status & ATH9K_TXERR_FILT)
 		return;
 
 	if (info_priv->tx.ts_rssi > 0) {

@@ -1667,14 +1667,14 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
 	 * times. This affects how ratectrl updates PER for the failed rate.
 	 */
 	if (info_priv->tx.ts_flags &
-		(HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN) &&
+		(ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) &&
 		((sc->sc_ah->ah_txTrigLevel) >= tx_triglevel_max)) {
 		tx_status = 1;
 		is_underrun = 1;
 	}
 
-	if ((info_priv->tx.ts_status & HAL_TXERR_XRETRY) ||
-			(info_priv->tx.ts_status & HAL_TXERR_FIFO))
+	if ((info_priv->tx.ts_status & ATH9K_TXERR_XRETRY) ||
+			(info_priv->tx.ts_status & ATH9K_TXERR_FIFO))
 		tx_status = 1;
 
 	ath_rc_update(sc, rc_priv, info_priv, final_ts_idx, tx_status,

index 2446c00..372c893 100644
@@ -961,14 +961,14 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 #endif
 			/* fall thru for monitor mode handling... */
 		} else if (ds->ds_rxstat.rs_status != 0) {
-			if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
+			if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
 				rx_status.flags |= ATH_RX_FCS_ERROR;
-			if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
+			if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) {
 				phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
 				goto rx_next;
 			}
 
-			if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
+			if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
 				/*
 				 * Decrypt error. We only mark packet status
 				 * here and always push up the frame up to let

@@ -977,7 +977,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 				 * error. This let us keep statistics there.
 				 */
 				rx_status.flags |= ATH_RX_DECRYPT_ERROR;
-			} else if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
+			} else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
 				/*
 				 * Demic error. We only mark frame status here
 				 * and always push up the frame up to let

@@ -992,7 +992,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 					 * Remove these mic errors.
 					 */
 					ds->ds_rxstat.rs_status &=
-						~HAL_RXERR_MIC;
+						~ATH9K_RXERR_MIC;
 				else
 					rx_status.flags |= ATH_RX_MIC_ERROR;
 			}

@@ -1003,12 +1003,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 			 */
 			if (sc->sc_opmode == HAL_M_MONITOR) {
 				if (ds->ds_rxstat.rs_status &
-				    ~(HAL_RXERR_DECRYPT | HAL_RXERR_MIC |
-					HAL_RXERR_CRC))
+				    ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
+					ATH9K_RXERR_CRC))
 					goto rx_next;
 			} else {
 				if (ds->ds_rxstat.rs_status &
-				    ~(HAL_RXERR_DECRYPT | HAL_RXERR_MIC)) {
+				    ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
 					goto rx_next;
 				}
 			}

@@ -1037,12 +1037,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 		/* HT rate */
 		if (rx_status.ratecode & 0x80) {
 			/* TODO - add table to avoid division */
-			if (ds->ds_rxstat.rs_flags & HAL_RX_2040) {
+			if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
 				rx_status.flags |= ATH_RX_40MHZ;
 				rx_status.rateKbps =
 					(rx_status.rateKbps * 27) / 13;
 			}
-			if (ds->ds_rxstat.rs_flags & HAL_RX_GI)
+			if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
 				rx_status.rateKbps =
 					(rx_status.rateKbps * 10) / 9;
 			else

@@ -1083,7 +1083,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 				rx_status.rssictl[2] =
 					ds->ds_rxstat.rs_rssi_ctl2;
 				rx_status.rssi = ds->ds_rxstat.rs_rssi;
-				if (ds->ds_rxstat.rs_flags & HAL_RX_2040) {
+				if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
 					rx_status.rssiextn[0] =
 						ds->ds_rxstat.rs_rssi_ext0;
 					rx_status.rssiextn[1] =

index 127204c..71c2e77 100644
@@ -625,7 +625,7 @@ static int ath_tx_num_badfrms(struct ath_softc *sc,
 	int nbad = 0;
 	int isaggr = 0;
 
-	if (isnodegone || ds->ds_txstat.ts_flags == HAL_TX_SW_ABORTED)
+	if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
 		return 0;
 
 	isaggr = bf->bf_isaggr;

@@ -1069,7 +1069,7 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
 		} else {
 
 			if (!tid->cleanup_inprogress && !isnodegone &&
-			    ds->ds_txstat.ts_flags != HAL_TX_SW_ABORTED) {
+			    ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
 				if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
 					ath_tx_set_retry(sc, bf);
 					txpending = 1;

@@ -1350,7 +1350,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 			 * Use hardware retry status for this frame.
 			 */
 			bf->bf_retries = ds->ds_txstat.ts_longretry;
-			if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
+			if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
 				bf->bf_isxretried = 1;
 			nbad = 0;
 		} else {

@@ -1360,9 +1360,9 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 		tx_info = IEEE80211_SKB_CB(skb);
 		tx_info_priv = (struct ath_tx_info_priv *)
 			tx_info->driver_data[0];
-		if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
+		if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
 			tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
-		if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
+		if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
 				(bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
 			if (ds->ds_txstat.ts_status == 0)
 				nacked++;

@@ -2475,7 +2475,8 @@ void ath_tx_draintxq(struct ath_softc *sc,
 
 		lastbf = bf->bf_lastbf;
 		if (!retry_tx)
-			lastbf->bf_desc->ds_txstat.ts_flags = HAL_TX_SW_ABORTED;
+			lastbf->bf_desc->ds_txstat.ts_flags =
+				ATH9K_TX_SW_ABORTED;
 
 		/* remove ath_buf's of the same mpdu from txq */
 		list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);

index 47d4891..d9c7561 100644
@@ -508,9 +508,10 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
 	 * enabled/disabled setting
 	 */
 	if ((sc->sc_no_tx_3_chains == AH_FALSE) ||
-	    (sc->sc_config.chainmask_sel == AH_FALSE))
+	    (sc->sc_config.chainmask_sel == AH_FALSE)) {
 		cm->cur_tx_mask = sc->sc_tx_chainmask;
 		return cm->cur_tx_mask;
+	}
 
 	if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
 		return cm->cur_tx_mask;

index 24dad48..1f858b0 100644
@@ -116,11 +116,6 @@ struct ath_rx_status {
 #define ATH9K_RX_DELIM_CRC_POST   0x20
 #define ATH9K_RX_DECRYPT_BUSY     0x40
 
-enum hal_bool {
-	AH_FALSE = 0,
-	AH_TRUE = 1,
-};
-
 #define	HAL_RXKEYIX_INVALID	((u_int8_t)-1)
 #define	HAL_TXKEYIX_INVALID	((u_int)-1)
 

@@ -482,11 +477,11 @@ struct hal_channel_internal {
 	int8_t maxRegTxPower;
 	int8_t maxTxPower;
 	int8_t minTxPower;
-	enum hal_bool bssSendHere;
+	bool bssSendHere;
 	u_int8_t gainI;
-	enum hal_bool iqCalValid;
+	bool iqCalValid;
 	int32_t CalValid;
-	enum hal_bool oneTimeCalsDone;
+	bool oneTimeCalsDone;
 	int8_t iCoff;
 	int8_t qCoff;
 	int16_t rawNoiseFloor;

@@ -936,13 +931,13 @@ struct ath_hal {
 	u_int16_t ah_currentRD2G;
 	char ah_iso[4];
 	enum start_adhoc_option ah_adHocMode;
-	enum hal_bool ah_commonMode;
+	bool ah_commonMode;
 	struct hal_channel_internal ah_channels[150];
 	u_int ah_nchan;
 	struct hal_channel_internal *ah_curchan;
 	u_int16_t ah_rfsilent;
-	enum hal_bool ah_rfkillEnabled;
-	enum hal_bool ah_isPciExpress;
+	bool ah_rfkillEnabled;
+	bool ah_isPciExpress;
 	u_int16_t ah_txTrigLevel;
 #ifndef ATH_NF_PER_CHAN
 	struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];

@@ -1003,36 +998,35 @@ struct ath_hal *ath9k_hw_attach(u_int16_t devid,
 				struct ath_softc *sc,
 				void __iomem *mem,
 				enum hal_status *error);
-enum hal_bool ath9k_regd_init_channels(struct ath_hal *ah,
-				       struct hal_channel *chans,
-				       u_int maxchans, u_int *nchans,
-				       u_int8_t *regclassids,
-				       u_int maxregids, u_int *nregids,
-				       u_int16_t cc, u_int32_t modeSelect,
-				       enum hal_bool enableOutdoor,
-				       enum hal_bool
-				       enableExtendedChannels);
+bool ath9k_regd_init_channels(struct ath_hal *ah,
+			      struct hal_channel *chans,
+			      u_int maxchans, u_int *nchans,
+			      u_int8_t *regclassids,
+			      u_int maxregids, u_int *nregids,
+			      u_int16_t cc, u_int32_t modeSelect,
+			      bool enableOutdoor,
+			      bool enableExtendedChannels);
 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
 enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
 				     enum hal_int ints);
-enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
-			     struct hal_channel *chan,
-			     enum hal_ht_macmode macmode,
-			     u_int8_t txchainmask, u_int8_t rxchainmask,
-			     enum hal_ht_extprotspacing extprotspacing,
-			     enum hal_bool bChannelChange,
-			     enum hal_status *status);
-enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah);
+bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
+		    struct hal_channel *chan,
+		    enum hal_ht_macmode macmode,
+		    u_int8_t txchainmask, u_int8_t rxchainmask,
+		    enum hal_ht_extprotspacing extprotspacing,
+		    bool bChannelChange,
+		    enum hal_status *status);
+bool ath9k_hw_phy_disable(struct ath_hal *ah);
 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
-			     enum hal_bool *isCalDone);
+			     bool *isCalDone);
 void ath9k_hw_ani_monitor(struct ath_hal *ah,
 			  const struct hal_node_stats *stats,
 			  struct hal_channel *chan);
-enum hal_bool ath9k_hw_calibrate(struct ath_hal *ah,
-				 struct hal_channel *chan,
-				 u_int8_t rxchainmask,
-				 enum hal_bool longcal,
-				 enum hal_bool *isCalDone);
+bool ath9k_hw_calibrate(struct ath_hal *ah,
+			struct hal_channel *chan,
+			u_int8_t rxchainmask,
+			bool longcal,
+			bool *isCalDone);
 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
 			       struct hal_channel *chan);
 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,

@@ -1040,65 +1034,65 @@ void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
 			    u_int16_t assocId);
-enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
+bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
 void ath9k_hw_reset_tsf(struct ath_hal *ah);
-enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
-enum hal_bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
-				 const u_int8_t *mac);
-enum hal_bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
-					  u_int16_t entry,
-					  const struct hal_keyval *k,
-					  const u_int8_t *mac,
-					  int xorKey);
-enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
-				     u_int32_t setting);
+bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
+			const u_int8_t *mac);
+bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
+				 u_int16_t entry,
+				 const struct hal_keyval *k,
+				 const u_int8_t *mac,
+				 int xorKey);
+bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
+			    u_int32_t setting);
 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
-enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah);
-enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
-enum hal_bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
-					 enum hal_bool bIncTrigLevel);
+bool ath9k_hw_intrpend(struct ath_hal *ah);
+bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
+bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
+				bool bIncTrigLevel);
 void ath9k_hw_procmibevent(struct ath_hal *ah,
 			   const struct hal_node_stats *stats);
-enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set);
+bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
-enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah);
-enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
-enum hal_bool ath9k_hw_getcapability(struct ath_hal *ah,
-				     enum hal_capability_type type,
-				     u_int32_t capability,
-				     u_int32_t *result);
-enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
-				     enum hal_capability_type type,
-				     u_int32_t capability,
-				     u_int32_t setting,
-				     enum hal_status *status);
+bool ath9k_hw_phycounters(struct ath_hal *ah);
+bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_getcapability(struct ath_hal *ah,
+			    enum hal_capability_type type,
+			    u_int32_t capability,
+			    u_int32_t *result);
+bool ath9k_hw_setcapability(struct ath_hal *ah,
+			    enum hal_capability_type type,
+			    u_int32_t capability,
+			    u_int32_t setting,
+			    enum hal_status *status);
 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
-enum hal_bool ath9k_hw_setbssidmask(struct ath_hal *ah,
-				    const u_int8_t *mask);
-enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
-				enum hal_power_mode mode);
+bool ath9k_hw_setbssidmask(struct ath_hal *ah,
+			   const u_int8_t *mask);
+bool ath9k_hw_setpower(struct ath_hal *ah,
+		       enum hal_power_mode mode);
 enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
 u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
-enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
-enum hal_bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
-					enum hal_ant_setting settings,
-					struct hal_channel *chan,
-					u_int8_t *tx_chainmask,
-					u_int8_t *rx_chainmask,
-					u_int8_t *antenna_cfgd);
+bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
+bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
+			       enum hal_ant_setting settings,
+			       struct hal_channel *chan,
+			       u_int8_t *tx_chainmask,
+			       u_int8_t *rx_chainmask,
+			       u_int8_t *antenna_cfgd);
 void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
 enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
 					  u_int32_t cfg);
-enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
-				u_int32_t txdp);
-enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
+bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
+		       u_int32_t txdp);
+bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
 u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
 				 const struct hal_rate_table *rates,
 				 u_int32_t frameLen, u_int16_t rateix,
-				 enum hal_bool shortPreamble);
+				 bool shortPreamble);
 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
 				  struct ath_desc *lastds,
 				  u_int durUpdateEn, u_int rtsctsRate,

@@ -1110,25 +1104,25 @@ void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
 				   u_int burstDuration);
 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
-enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
+bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
 u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
 u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
-	struct hal_channel *chan);
+				     struct hal_channel *chan);
 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
-enum hal_bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
-	struct hal_txq_info *qInfo);
-enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
-				       const struct hal_txq_info *qInfo);
+bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
+			      struct hal_txq_info *qInfo);
+bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
+			      const struct hal_txq_info *qInfo);
 struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
-	const struct hal_channel *c);
+					      const struct hal_channel *c);
 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
-	u_int pktLen, enum hal_pkt_type type,
-	u_int txPower, u_int keyIx,
-	enum hal_key_type keyType, u_int flags);
-enum hal_bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
-	u_int segLen, enum hal_bool firstSeg,
-	enum hal_bool lastSeg,
-	const struct ath_desc *ds0);
+			    u_int pktLen, enum hal_pkt_type type,
+			    u_int txPower, u_int keyIx,
+			    enum hal_key_type keyType, u_int flags);
+bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
+			 u_int segLen, bool firstSeg,
+			 bool lastSeg,
+			 const struct ath_desc *ds0);
 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
 					u_int32_t *rxc_pcnt,
 					u_int32_t *rxf_pcnt,

@@ -1138,18 +1132,18 @@ void ath9k_hw_beaconinit(struct ath_hal *ah,
 			 u_int32_t next_beacon, u_int32_t beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
 				    const struct hal_beacon_state *bs);
-enum hal_bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
-				   u_int32_t size, u_int flags);
+bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
+			  u_int32_t size, u_int flags);
 void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
 void ath9k_hw_rxena(struct ath_hal *ah);
 void ath9k_hw_setopmode(struct ath_hal *ah);
-enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
+bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
 			     u_int32_t filter1);
 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
 void ath9k_hw_startpcureceive(struct ath_hal *ah);
 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
-enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
+bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
 enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
 				    struct ath_desc *ds, u_int32_t pa,
 				    struct ath_desc *nds, u_int64_t tsf);

@@ -1161,26 +1155,26 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
 				u_int aggrLen);
 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
-enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
+bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
 				     struct ath_desc *ds, u_int vmf);
-enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
-enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
+bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
+bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
 			  const struct hal_txq_info *qInfo);
 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
 const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
-enum hal_bool ath9k_hw_disable(struct ath_hal *ah);
+bool ath9k_hw_disable(struct ath_hal *ah);
 void ath9k_hw_rfdetach(struct ath_hal *ah);
 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 				  struct hal_channel_internal *chan,
 				  struct chan_centers *centers);
-enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
-				      u_int16_t flags, u_int16_t *low,
-				      u_int16_t *high);
-enum hal_bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
-					     struct hal_channel *chans,
-					     u_int32_t nchans);
+bool ath9k_get_channel_edges(struct ath_hal *ah,
+			     u_int16_t flags, u_int16_t *low,
+			     u_int16_t *high);
+bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
+				    struct hal_channel *chans,
+				    u_int32_t nchans);
 #endif

index b2f44b1..699159e 100644
@@ -128,8 +128,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
 	/* NB: beacon's BufLen must be a multiple of 4 bytes */
 	ath9k_hw_filltxdesc(ah, ds
 			   , roundup(skb->len, 4) /* buffer length */
-			   , AH_TRUE /* first segment */
-			   , AH_TRUE /* last segment */
+			   , true /* first segment */
+			   , true /* last segment */
 			   , ds /* first descriptor */
 		);
 

@@ -273,7 +273,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
 		 * acquires txq lock inside.
 		 */
 		if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
-			ath_tx_draintxq(sc, cabq, AH_FALSE);
+			ath_tx_draintxq(sc, cabq, false);
 			DPRINTF(sc, ATH_DEBUG_BEACON,
 				"%s: flush previous cabq traffic\n", __func__);
 		}

index d9c7561..99ba213 100644
@@ -19,7 +19,7 @@
 #include "core.h"
 #include "regd.h"
 
-static int ath_outdoor = AH_FALSE;		/* enable outdoor use */
+static int ath_outdoor;		/* enable outdoor use */
 
 static const u_int8_t ath_bcast_mac[ETH_ALEN] =
     { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };

@@ -176,8 +176,8 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
 
 static int ath_getchannels(struct ath_softc *sc,
 			   u_int cc,
-			   enum hal_bool outDoor,
-			   enum hal_bool xchanMode)
+			   bool outDoor,
+			   bool xchanMode)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	struct hal_channel *chans;

@@ -311,7 +311,7 @@ static int ath_stop(struct ath_softc *sc)
 
 	if (!sc->sc_invalid)
 		ath9k_hw_set_interrupts(ah, 0);
-	ath_draintxq(sc, AH_FALSE);
+	ath_draintxq(sc, false);
 	if (!sc->sc_invalid) {
 		ath_stoprecv(sc);
 		ath9k_hw_phy_disable(ah);

@@ -379,7 +379,7 @@ void ath_scan_end(struct ath_softc *sc)
 int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 {
 	struct ath_hal *ah = sc->sc_ah;
-	enum hal_bool fastcc = AH_TRUE, stopped;
+	bool fastcc = true, stopped;
 	enum hal_ht_macmode ht_macmode;
 
 	if (sc->sc_invalid)	/* if the device is invalid or removed */

@@ -410,7 +410,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 		 * the relevant bits of the h/w.
 		 */
 		ath9k_hw_set_interrupts(ah, 0);	/* disable interrupts */
-		ath_draintxq(sc, AH_FALSE);	/* clear pending tx frames */
+		ath_draintxq(sc, false);	/* clear pending tx frames */
 		stopped = ath_stoprecv(sc);	/* turn off frame recv */
 
 		/* XXX: do not flush receive queue here. We don't want

@@ -418,7 +418,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 		 * changing channel. */
 
 		if (!stopped || sc->sc_full_reset)
-			fastcc = AH_FALSE;
+			fastcc = false;
 
 		spin_lock_bh(&sc->sc_resetlock);
 		if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,

@@ -507,8 +507,7 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
 	 * sc_chainmask_auto_sel is used for internal global auto-switching
 	 * enabled/disabled setting
 	 */
-	if ((sc->sc_no_tx_3_chains == AH_FALSE) ||
-	    (sc->sc_config.chainmask_sel == AH_FALSE)) {
+	if (!sc->sc_no_tx_3_chains || !sc->sc_config.chainmask_sel) {
 		cm->cur_tx_mask = sc->sc_tx_chainmask;
 		return cm->cur_tx_mask;
 	}

@@ -716,12 +715,12 @@ int ath_vap_detach(struct ath_softc *sc, int if_id)
 	 * XXX can we do this w/o affecting other vap's?
 	 */
 	ath9k_hw_set_interrupts(ah, 0);	/* disable interrupts */
-	ath_draintxq(sc, AH_FALSE);	/* stop xmit side */
+	ath_draintxq(sc, false);	/* stop xmit side */
 	ath_stoprecv(sc);	/* stop recv side */
 	ath_flushrecv(sc);	/* flush recv queue */
 
 	/* Reclaim any pending mcast bufs on the vap. */
-	ath_tx_draintxq(sc, &avp->av_mcastq, AH_FALSE);
+	ath_tx_draintxq(sc, &avp->av_mcastq, false);
 
 	if (sc->sc_opmode == HAL_M_HOSTAP && sc->sc_nostabeacons)
 		sc->sc_nostabeacons = 0;

@@ -791,7 +790,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
 	spin_lock_bh(&sc->sc_resetlock);
 	if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
 			   sc->sc_tx_chainmask, sc->sc_rx_chainmask,
-			   sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
+			   sc->sc_ht_extprotspacing, false, &status)) {
 		DPRINTF(sc, ATH_DEBUG_FATAL,
 			"%s: unable to reset hardware; hal status %u "
 			"(freq %u flags 0x%x)\n", __func__, status,

@@ -928,7 +927,7 @@ int ath_reset(struct ath_softc *sc)
 	if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
 			   ht_macmode,
 			   sc->sc_tx_chainmask, sc->sc_rx_chainmask,
-			   sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
+			   sc->sc_ht_extprotspacing, false, &status)) {
 		DPRINTF(sc, ATH_DEBUG_FATAL,
 			"%s: unable to reset hardware; hal status %u\n",
 			__func__, status);

@@ -1026,7 +1025,7 @@ int ath_intr(struct ath_softc *sc)
 
 			if (status & HAL_INT_TXURN)
 				/* bump tx trigger level */
-				ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
+				ath9k_hw_updatetxtriglevel(ah, true);
 			/* XXX: optimize this */
 			if (status & HAL_INT_RX)
 				sched = ATH_ISR_SCHED;

@@ -1334,7 +1333,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	 */
 	sc->sc_no_tx_3_chains =
 	    (ah->ah_caps.halTxChainMask == ATH_CHAINMASK_SEL_3X3) ?
-		AH_TRUE : AH_FALSE;
+		true : false;
 	sc->sc_config.chainmask_sel = sc->sc_no_tx_3_chains;
 
 	sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;

@@ -1347,8 +1346,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 	sc->sc_rxchaindetect_delta5GHz = 30;
 	sc->sc_rxchaindetect_delta2GHz = 30;
 
-	ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, AH_TRUE, NULL);
-
+	ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, true, NULL);
 	sc->sc_defant = ath9k_hw_getdefantenna(ah);
 
 	/*

@@ -1560,12 +1558,12 @@ int ath_keyset(struct ath_softc *sc,
 	       struct hal_keyval *hk,
 	       const u_int8_t mac[ETH_ALEN])
 {
-	enum hal_bool status;
+	bool status;
 
 	status = ath9k_hw_set_keycache_entry(sc->sc_ah,
-		keyix, hk, mac, AH_FALSE);
+		keyix, hk, mac, false);
 
-	return status != AH_FALSE;
+	return status != false;
 }
 
 /***********************/

index 6acf3a6..4eaf942 100644
@@ -370,7 +370,7 @@ struct ath_arx {
 };
 
 int ath_startrecv(struct ath_softc *sc);
-enum hal_bool ath_stoprecv(struct ath_softc *sc);
+bool ath_stoprecv(struct ath_softc *sc);
 void ath_flushrecv(struct ath_softc *sc);
 u_int32_t ath_calcrxfilter(struct ath_softc *sc);
 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);

@@ -551,9 +551,9 @@ struct ath_tx_stat {
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 int ath_tx_setup(struct ath_softc *sc, int haltype);
-void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx);
+void ath_draintxq(struct ath_softc *sc, bool retry_tx);
 void ath_tx_draintxq(struct ath_softc *sc,
-	struct ath_txq *txq, enum hal_bool retry_tx);
+	struct ath_txq *txq, bool retry_tx);
 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 void ath_tx_node_cleanup(struct ath_softc *sc,
 	struct ath_node *an, bool bh_flag);

2,301 lines not on this page · raw message

index 089aecd..1a77ed3 100644
@@ -711,7 +711,7 @@ struct ath_hal_5416 {
 	u_int32_t ah_txUrnInterruptMask;
 	struct hal_tx_queue_info ah_txq[HAL_NUM_TX_QUEUES];
 	enum hal_power_mode ah_powerMode;
-	enum hal_bool ah_chipFullSleep;
+	bool ah_chipFullSleep;
 	u_int32_t ah_atimWindow;
 	enum hal_ant_setting ah_diversityControl;
 	u_int16_t ah_antennaSwitchSwap;

@@ -754,7 +754,7 @@ struct ath_hal_5416 {
 	u_int32_t ah_tx6PowerInHalfDbm;
 	u_int32_t ah_staId1Defaults;
 	u_int32_t ah_miscMode;
-	enum hal_bool ah_tpcEnabled;
+	bool ah_tpcEnabled;
 	u_int32_t ah_beaconInterval;
 	enum {
 		AUTO_32KHZ,

@@ -780,9 +780,9 @@ struct ath_hal_5416 {
 	u_int32_t ah_gpioSelect;
 	u_int32_t ah_polarity;
 	u_int32_t ah_gpioBit;
-	enum hal_bool ah_eepEnabled;
+	bool ah_eepEnabled;
 	u_int32_t ah_procPhyErr;
-	enum hal_bool ah_hasHwPhyCounters;
+	bool ah_hasHwPhyCounters;
 	u_int32_t ah_aniPeriod;
 	struct ar5416AniState *ah_curani;
 	struct ar5416AniState ah_ani[255];

@@ -792,7 +792,7 @@ struct ath_hal_5416 {
 	int ah_firpwr[5];
 	u_int16_t ah_ratesArray[16];
 	u_int32_t ah_intrTxqs;
-	enum hal_bool ah_intrMitigation;
+	bool ah_intrMitigation;
 	u_int32_t ah_cycleCount;
 	u_int32_t ah_ctlBusy;
 	u_int32_t ah_extBusy;

@@ -899,8 +899,8 @@ struct ath_hal_5416 {
 #define HAL_ANI_CCK_TRIG_HIGH           200
 #define HAL_ANI_CCK_TRIG_LOW            100
 #define HAL_ANI_NOISE_IMMUNE_LVL        4
-#define HAL_ANI_USE_OFDM_WEAK_SIG       AH_TRUE
-#define HAL_ANI_CCK_WEAK_SIG_THR        AH_FALSE
+#define HAL_ANI_USE_OFDM_WEAK_SIG       true
+#define HAL_ANI_CCK_WEAK_SIG_THR        false
 #define HAL_ANI_SPUR_IMMUNE_LVL         7
 #define HAL_ANI_FIRSTEP_LVL             0
 #define HAL_ANI_RSSI_THR_HIGH           40

index 8baecf1..37af73e 100644
@@ -28,7 +28,7 @@ ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
 	REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
 }
 
-enum hal_bool
+bool
 ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 {
 	u_int32_t channelSel = 0;

@@ -54,7 +54,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 			HDPRINTF(ah, HAL_DBG_CHANNEL,
 				 "%s: invalid channel %u MHz\n", __func__,
 				 freq);
-			return AH_FALSE;
+			return false;
 		}
 
 		channelSel = (channelSel << 2) & 0xff;

@@ -87,7 +87,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 	} else {
 		HDPRINTF(ah, HAL_DBG_CHANNEL,
 			 "%s: invalid channel %u MHz\n", __func__, freq);
-		return AH_FALSE;
+		return false;
 	}
 
 	reg32 =

@@ -100,10 +100,10 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 
 	AH5416(ah)->ah_curchanRadIndex = -1;
 
-	return AH_TRUE;
+	return true;
 }
 
-enum hal_bool
+bool
 ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 			    struct hal_channel_internal *chan)
 {

@@ -171,7 +171,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 
 	AH5416(ah)->ah_curchanRadIndex = -1;
 
-	return AH_TRUE;
+	return true;
 }
 
 static void

@@ -201,7 +201,7 @@ ath9k_phy_modify_rx_buffer(u_int32_t *rfBuf, u_int32_t reg32,
 	}
 }
 
-enum hal_bool
+bool
 ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
 		     u_int16_t modesIndex)
 {

@@ -213,7 +213,7 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
 	int regWrites = 0;
 
 	if (AR_SREV_9280_10_OR_LATER(ah))
-		return AH_TRUE;
+		return true;
 
 	eepMinorRev = ath9k_hw_get_eeprom(ahp, EEP_MINOR_REV);
 

@@ -266,7 +266,7 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct hal_channel_internal *chan,
 	REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data,
 			   regWrites);
 
-	return AH_TRUE;
+	return true;
 }
 
 void

@@ -312,11 +312,11 @@ ath9k_hw_rfdetach(struct ath_hal *ah)
 	}
 }
 
-enum hal_bool
+bool
 ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
 			       struct hal_channel *chans, u_int32_t nchans)
 {
-	enum hal_bool retVal = AH_TRUE;
+	bool retVal = true;
 	int i;
 
 	for (i = 0; i < nchans; i++) {

@@ -327,7 +327,7 @@ ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
 }
 
 
-enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
+bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 {
 	struct ath_hal_5416 *ahp = AH5416(ah);
 

@@ -366,7 +366,7 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 				 "%s: cannot allocate RF banks\n",
 				 __func__);
 			*status = HAL_ENOMEM;
-			return AH_FALSE;
+			return false;
 		}
 
 		ahp->ah_addac5416_21 =

@@ -378,7 +378,7 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 				 "%s: cannot allocate ah_addac5416_21\n",
 				 __func__);
 			*status = HAL_ENOMEM;
-			return AH_FALSE;
+			return false;
 		}
 
 		ahp->ah_bank6Temp =

@@ -389,11 +389,11 @@ enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 				 "%s: cannot allocate ah_bank6Temp\n",
 				 __func__);
 			*status = HAL_ENOMEM;
-			return AH_FALSE;
+			return false;
 		}
 	}
 
-	return AH_TRUE;
+	return true;
 }
 
 void

index 6481944..9b75467 100644
@@ -17,19 +17,19 @@
 #ifndef PHY_H
 #define PHY_H
 
-enum hal_bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
+bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 					  struct hal_channel_internal
 					  *chan);
-enum hal_bool ath9k_hw_set_channel(struct ath_hal *ah,
+bool ath9k_hw_set_channel(struct ath_hal *ah,
 				   struct hal_channel_internal *chan);
 void ath9k_hw_write_regs(struct ath_hal *ah, u_int modesIndex,
 			 u_int freqIndex, int regWrites);
-enum hal_bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
+bool ath9k_hw_set_rf_regs(struct ath_hal *ah,
 				   struct hal_channel_internal *chan,
 				   u_int16_t modesIndex);
 void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
 				   struct hal_channel *chan);
-enum hal_bool ath9k_hw_init_rf(struct ath_hal *ah,
+bool ath9k_hw_init_rf(struct ath_hal *ah,
 			       enum hal_status *status);
 
 #define AR_PHY_BASE     0x9800

index 1114c32..3c2b1cb 100644
@@ -1974,8 +1974,8 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 			  ATH_RC_PROBE_ALLOWED,
 			  tx_info_priv->rcs,
 			  &is_probe,
-			  AH_FALSE);
-	if (is_probe == AH_TRUE)
+			  false);
+	if (is_probe)
 		sel->probe_idx = ((struct ath_tx_ratectrl *)
 			sta->rate_ctrl_priv)->probe_rate;
 

index 372c893..4b724c1 100644
@@ -728,11 +728,11 @@ start_recv:
 
 /* Disable the receive h/w in preparation for a reset. */
 
-enum hal_bool ath_stoprecv(struct ath_softc *sc)
+bool ath_stoprecv(struct ath_softc *sc)
 {
 	struct ath_hal *ah = sc->sc_ah;
 	u_int64_t tsf;
-	enum hal_bool stopped;
+	bool stopped;
 
 	ath9k_hw_stoppcurecv(ah);	/* disable PCU */
 	ath9k_hw_setrxfilter(ah, 0);	/* clear recv filter */

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index 8546117..6d6c89f 100644

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48 lines not on this page · raw message

index 1f858b0..6fa1eb6 100644
@@ -238,7 +238,6 @@ struct hal_ops_config {
 	u_int16_t ath_hal_antennaSwitchSwap;
 	int ath_hal_serializeRegMode;
 	int ath_hal_intrMitigation;
-	int ath_hal_debug;
 #define SPUR_DISABLE        	0
 #define SPUR_ENABLE_IOCTL   	1
 #define SPUR_ENABLE_EEPROM  	2

@@ -618,33 +617,6 @@ struct hal_country_entry {
 	u_int8_t iso[3];
 };
 
-#define HAL_DBG_RESET           0x00000001
-#define HAL_DBG_PHY_IO          0x00000002
-#define HAL_DBG_REG_IO          0x00000004
-#define HAL_DBG_RF_PARAM        0x00000008
-#define HAL_DBG_QUEUE           0x00000010
-#define HAL_DBG_EEPROM_DUMP     0x00000020
-#define HAL_DBG_EEPROM          0x00000040
-#define HAL_DBG_NF_CAL          0x00000080
-#define HAL_DBG_CALIBRATE       0x00000100
-#define HAL_DBG_CHANNEL         0x00000200
-#define HAL_DBG_INTERRUPT       0x00000400
-#define HAL_DBG_DFS             0x00000800
-#define HAL_DBG_DMA             0x00001000
-#define HAL_DBG_REGULATORY      0x00002000
-#define HAL_DBG_TX              0x00004000
-#define HAL_DBG_TXDESC          0x00008000
-#define HAL_DBG_RX              0x00010000
-#define HAL_DBG_RXDESC          0x00020000
-#define HAL_DBG_ANI             0x00040000
-#define HAL_DBG_BEACON          0x00080000
-#define HAL_DBG_KEYCACHE        0x00100000
-#define HAL_DBG_POWER_MGMT      0x00200000
-#define HAL_DBG_MALLOC          0x00400000
-#define HAL_DBG_POWER_OVERRIDE  0x01000000
-#define HAL_DBG_SPUR_MITIGATE   0x02000000
-#define HAL_DBG_UNMASKABLE      0xFFFFFFFF
-
 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
 

@@ -944,12 +916,6 @@ struct ath_hal {
 #endif
 };
 
-#define HDPRINTF(_ah, _m, _fmt, ...) do {				\
-		if (((_ah) == NULL && _m == HAL_DBG_UNMASKABLE) ||	\
-		    (((struct ath_hal *)(_ah))->ah_config.ath_hal_debug & _m)) \
-			printk(KERN_DEBUG _fmt , ##__VA_ARGS__);	\
-	} while (0)
-
 enum wireless_mode {
 	WIRELESS_MODE_11a = 0,
 	WIRELESS_MODE_11b = 2,

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280 lines not on this page · raw message

index 4eaf942..964ba58 100644
@@ -100,23 +100,29 @@ static inline unsigned long get_timestamp(void)
 /*************/
 
 enum ATH_DEBUG {
-	ATH_DEBUG_XMIT          = 0x00000001,   /* basic xmit operation */
-	ATH_DEBUG_RECV          = 0x00000002,   /* basic recv operation */
-	ATH_DEBUG_BEACON        = 0x00000004,   /* beacon handling */
-	ATH_DEBUG_TX_PROC       = 0x00000008,   /* tx ISR proc */
-	ATH_DEBUG_RX_PROC       = 0x00000010,   /* rx ISR proc */
-	ATH_DEBUG_BEACON_PROC   = 0x00000020,   /* beacon ISR proc */
-	ATH_DEBUG_RATE          = 0x00000040,   /* rate control */
-	ATH_DEBUG_CONFIG        = 0x00000080,   /* configuration */
-	ATH_DEBUG_KEYCACHE      = 0x00000100,   /* key cache management */
-	ATH_DEBUG_NODE          = 0x00000200,   /* node management */
-	ATH_DEBUG_AGGR		= 0x00000400,	/* Aggregation */
-	ATH_DEBUG_CWM		= 0x00000800,	/* Channel Width Management */
-	ATH_DEBUG_FATAL         = 0x00001000,   /* fatal errors */
-	ATH_DEBUG_ANY           = 0xffffffff
+	ATH_DBG_RESET		= 0x00000001,
+	ATH_DBG_PHY_IO		= 0x00000002,
+	ATH_DBG_REG_IO		= 0x00000004,
+	ATH_DBG_QUEUE		= 0x00000008,
+	ATH_DBG_EEPROM		= 0x00000010,
+	ATH_DBG_NF_CAL		= 0x00000020,
+	ATH_DBG_CALIBRATE	= 0x00000040,
+	ATH_DBG_CHANNEL		= 0x00000080,
+	ATH_DBG_INTERRUPT	= 0x00000100,
+	ATH_DBG_REGULATORY	= 0x00000200,
+	ATH_DBG_ANI		= 0x00000400,
+	ATH_DBG_POWER_MGMT	= 0x00000800,
+	ATH_DBG_XMIT		= 0x00001000,
+	ATH_DBG_BEACON		= 0x00002000,
+	ATH_DBG_RATE		= 0x00004000,
+	ATH_DBG_CONFIG		= 0x00008000,
+	ATH_DBG_KEYCACHE	= 0x00010000,
+	ATH_DBG_AGGR		= 0x00020000,
+	ATH_DBG_FATAL		= 0x00040000,
+	ATH_DBG_ANY		= 0xffffffff
 };
 
-#define DBG_DEFAULT (ATH_DEBUG_FATAL)
+#define DBG_DEFAULT (ATH_DBG_FATAL)
 
 #define	DPRINTF(sc, _m, _fmt, ...) do {			\
 		if (sc->sc_debug & (_m))                \

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351 lines not on this page · raw message

index 37af73e..e1fc9c6 100644
@@ -14,7 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "ath9k.h"
+#include "core.h"
 #include "hw.h"
 #include "reg.h"
 #include "phy.h"

@@ -51,7 +51,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 			channelSel = ((freq - 704) * 2 - 3040) / 10;
 			bModeSynth = 1;
 		} else {
-			HDPRINTF(ah, HAL_DBG_CHANNEL,
+			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 				 "%s: invalid channel %u MHz\n", __func__,
 				 freq);
 			return false;

@@ -85,7 +85,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct hal_channel_internal *chan)
 		channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
 		aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 	} else {
-		HDPRINTF(ah, HAL_DBG_CHANNEL,
+		DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 			 "%s: invalid channel %u MHz\n", __func__, freq);
 		return false;
 	}

@@ -362,7 +362,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 		    || ahp->ah_analogBank6Data == NULL
 		    || ahp->ah_analogBank6TPCData == NULL
 		    || ahp->ah_analogBank7Data == NULL) {
-			HDPRINTF(ah, HAL_DBG_MALLOC,
+			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate RF banks\n",
 				 __func__);
 			*status = HAL_ENOMEM;

@@ -374,7 +374,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 			     ahp->ah_iniAddac.ia_rows *
 			     ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
 		if (ahp->ah_addac5416_21 == NULL) {
-			HDPRINTF(ah, HAL_DBG_MALLOC,
+			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate ah_addac5416_21\n",
 				 __func__);
 			*status = HAL_ENOMEM;

@@ -385,7 +385,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, enum hal_status *status)
 		    kzalloc((sizeof(u_int32_t) *
 			     ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 		if (ahp->ah_bank6Temp == NULL) {
-			HDPRINTF(ah, HAL_DBG_MALLOC,
+			DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 				 "%s: cannot allocate ah_bank6Temp\n",
 				 __func__);
 			*status = HAL_ENOMEM;

index 9b75467..6c05257 100644
@@ -518,7 +518,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah,
 		int r;							\
 		for (r = 0; r < ((iniarray)->ia_rows); r++) {		\
 			REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
-			HDPRINTF(ah, HAL_DBG_CHANNEL, \
+			DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, \
 				"RF 0x%x V 0x%x\n", \
 				INI_RA((iniarray), r, 0), (regData)[r]); \
 			DO_DELAY(regWr);				\

index 3c2b1cb..996b54c 100644
@@ -1149,7 +1149,7 @@ void ath_rate_findrate(struct ath_softc *sc,
 {
 	struct ath_vap         *avp = ath_rc_priv->avp;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	if (!num_rates || !num_tries)
 		return;
 

@@ -1822,7 +1822,7 @@ static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta)
 	struct ath_rate_node *rc_priv = sta->rate_ctrl_priv;
 	int i, j = 0;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	sband =  local->hw.wiphy->bands[local->hw.conf.channel->band];
 	for (i = 0; i < sband->n_bitrates; i++) {
 		if (sta->supp_rates[local->hw.conf.channel->band] & BIT(i)) {

@@ -1920,7 +1920,7 @@ static void ath_tx_aggr_resp(struct ath_softc *sc,
 		txtid->addba_exchangeinprogress = 0;
 		txtid->baw_size = buffersize;
 
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Resuming tid, buffersize: %d\n",
 			__func__,
 			buffersize);

@@ -1949,7 +1949,7 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 	u8 *qc, tid;
 	DECLARE_MAC_BUF(mac);
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s\n", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
 
 	/* allocate driver private area of tx_info */
 	tx_info->driver_data[0] = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);

@@ -1999,7 +1999,7 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 			spin_unlock_bh(&sc->node_lock);
 
 			if (!an) {
-				DPRINTF(sc, ATH_DEBUG_AGGR,
+				DPRINTF(sc, ATH_DBG_AGGR,
 					"%s: Node not found to "
 					"init/chk TX aggr\n", __func__);
 				return;

@@ -2010,13 +2010,13 @@ static void ath_get_rate(void *priv, struct net_device *dev,
 				ret = ieee80211_start_tx_ba_session(hw,
 					hdr->addr1, tid);
 				if (ret)
-					DPRINTF(sc, ATH_DEBUG_AGGR,
+					DPRINTF(sc, ATH_DBG_AGGR,
 						"%s: Unable to start tx "
 						"aggr for: %s\n",
 						__func__,
 						print_mac(mac, hdr->addr1));
 				else
-					DPRINTF(sc, ATH_DEBUG_AGGR,
+					DPRINTF(sc, ATH_DBG_AGGR,
 						"%s: Started tx aggr for: %s\n",
 						__func__,
 						print_mac(mac, hdr->addr1));

@@ -2037,7 +2037,7 @@ static void ath_rate_init(void *priv, void *priv_sta,
 	struct hal_channel hchan;
 	int i, j = 0;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 
 	sband = local->hw.wiphy->bands[local->hw.conf.channel->band];
 	sta->txrate_idx = rate_lowest_index(local, sband, sta);

@@ -2045,7 +2045,7 @@ static void ath_rate_init(void *priv, void *priv_sta,
 	hchan.channel = conf->channel->center_freq;
 	hchan.channelFlags = ath_chan2flags(conf->channel, sc);
 	if (ath_set_channel(sc, &hchan) < 0)
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s: Unable to set channel\n",
+		DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
 			__func__);
 	ath_setup_rates(local, sta);
 	if (conf->flags&IEEE80211_CONF_SUPPORT_HT_MODE) {

@@ -2071,7 +2071,7 @@ static void *ath_rate_alloc(struct ieee80211_local *local)
 	struct ieee80211_hw *hw = local_to_hw(local);
 	struct ath_softc *sc = hw->priv;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	return local->hw.priv;
 }
 

@@ -2086,10 +2086,10 @@ static void *ath_rate_alloc_sta(void *priv, gfp_t gfp)
 	struct ath_vap *avp = sc->sc_vaps[0];
 	struct ath_rate_node *rate_priv;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	rate_priv = ath_rate_node_alloc(avp, sc->sc_rc, gfp);
 	if (!rate_priv) {
-		DPRINTF(sc, ATH_DEBUG_FATAL, "%s:Unable to allocate"
+		DPRINTF(sc, ATH_DBG_FATAL, "%s:Unable to allocate"
 				"private rate control structure", __func__);
 		return NULL;
 	}

@@ -2102,7 +2102,7 @@ static void ath_rate_free_sta(void *priv, void *priv_sta)
 	struct ath_rate_node *rate_priv = priv_sta;
 	struct ath_softc *sc = priv;
 
-	DPRINTF(sc, ATH_DEBUG_RATE, "%s", __func__);
+	DPRINTF(sc, ATH_DBG_RATE, "%s", __func__);
 	ath_rate_node_free(rate_priv);
 }
 

index 4b724c1..963bcd9 100644
@@ -457,7 +457,7 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
 		if (off != 0)
 			skb_reserve(skb, sc->sc_cachelsz - off);
 	} else {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: skbuff alloc of size %u failed\n",
 			__func__, len);
 		return NULL;

@@ -545,7 +545,7 @@ static void ath_opmode_init(struct ath_softc *sc)
 	mfilt[0] = mfilt[1] = ~0;
 
 	ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
-	DPRINTF(sc, ATH_DEBUG_RECV ,
+	DPRINTF(sc, ATH_DBG_CONFIG ,
 		"%s: RX filter 0x%x, MC filter %08x:%08x\n",
 		__func__, rfilt, mfilt[0], mfilt[1]);
 }

@@ -571,7 +571,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
 					   min(sc->sc_cachelsz,
 					       (u_int16_t)64));
 
-		DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
+		DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
 			__func__, sc->sc_cachelsz, sc->sc_rxbufsize);
 
 		/* Initialize rx descriptors */

@@ -579,7 +579,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
 		error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
 					  "rx", nbufs, 1);
 		if (error != 0) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: failed to allocate rx descriptors: %d\n",
 				__func__, error);
 			break;

@@ -802,8 +802,6 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
 	enum hal_status retval;
 	__le16 fc;
 
-	DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s\n", __func__);
-
 	do {
 		/* If handling rx interrupt and flush is in progress => exit */
 		if (sc->sc_rxflush && (flush == 0))

@@ -1160,7 +1158,7 @@ rx_next:
 	} while (TRUE);
 
 	if (chainreset) {
-		DPRINTF(sc, ATH_DEBUG_CONFIG,
+		DPRINTF(sc, ATH_DBG_CONFIG,
 			"%s: Reset rx chain mask. "
 			"Do internal reset\n", __func__);
 		ASSERT(flush == 0);

@@ -1189,7 +1187,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 	spin_unlock_bh(&sc->node_lock);
 
 	if (!an) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Node not found to initialize RX aggregation\n",
 			__func__);
 		return -1;

@@ -1214,7 +1212,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 		rxtid->seq_next = *ssn;
 
 		/* Allocate the receive buffers for this TID */
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Allcating rxbuffer for TID %d\n", __func__, tid);
 
 		if (rxtid->rxbuf == NULL) {

@@ -1229,7 +1227,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 				sizeof(struct ath_rxbuf), GFP_ATOMIC);
 		}
 		if (rxtid->rxbuf == NULL) {
-			DPRINTF(sc, ATH_DEBUG_AGGR,
+			DPRINTF(sc, ATH_DBG_AGGR,
 				"%s: Unable to allocate RX buffer, "
 				"refusing ADDBA\n", __func__);
 		} else {

@@ -1237,7 +1235,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
 			 * pointers are null) */
 			memzero(rxtid->rxbuf, ATH_TID_MAX_BUFS *
 				sizeof(struct ath_rxbuf));
-			DPRINTF(sc, ATH_DEBUG_AGGR,
+			DPRINTF(sc, ATH_DBG_AGGR,
 				"%s: Allocated @%p\n", __func__, rxtid->rxbuf);
 
 			/* Allow aggregation reception */

@@ -1262,7 +1260,7 @@ int ath_rx_aggr_stop(struct ath_softc *sc,
 	spin_unlock_bh(&sc->node_lock);
 
 	if (!an) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: RX aggr stop for non-existent node\n", __func__);
 		return -1;
 	}

@@ -1288,7 +1286,7 @@ void ath_rx_aggr_teardown(struct ath_softc *sc,
 	/* De-allocate the receive buffer array allocated when addba started */
 
 	if (rxtid->rxbuf) {
-		DPRINTF(sc, ATH_DEBUG_AGGR,
+		DPRINTF(sc, ATH_DBG_AGGR,
 			"%s: Deallocating TID %d rxbuff @%p\n",
 			__func__, tid, rxtid->rxbuf);
 		kfree(rxtid->rxbuf);

286 lines not on this page · raw message

index 4f46517..152f9f4 100644
@@ -118,11 +118,11 @@ static void ath_tx_mcastqaddbuf(struct ath_softc *sc,
 	txq->axq_totalqueued++;
 	txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
 
-	DPRINTF(sc, ATH_DEBUG_TX_PROC,
+	DPRINTF(sc, ATH_DBG_QUEUE,
 		"%s: txq depth = %d\n", __func__, txq->axq_depth);
 	if (txq->axq_link != NULL) {
 		*txq->axq_link = bf->bf_daddr;
-		DPRINTF(sc, ATH_DEBUG_XMIT,
+		DPRINTF(sc, ATH_DBG_XMIT,
 			"%s: link[%u](%p)=%llx (%p)\n",
 			__func__,
 			txq->axq_qnum, txq->axq_link,

@@ -158,18 +158,18 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc,
 	txq->axq_totalqueued++;
 	txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
 
-	DPRINTF(sc, ATH_DEBUG_TX_PROC,
+	DPRINTF(sc, ATH_DBG_QUEUE,
 		"%s: txq depth = %d\n", __func__, txq->axq_depth);
 
 	if (txq->axq_link == NULL) {
 		ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-		DPRINTF(sc, ATH_DEBUG_XMIT,
+		DPRINTF(sc, ATH_DBG_XMIT,
 			"%s: TXDP[%u] = %llx (%p)\n",
 			__func__, txq->axq_qnum,
 			ito64(bf->bf_daddr), bf->bf_desc);
 	} else {
 		*txq->axq_link = bf->bf_daddr;
-		DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
+		DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
 			__func__,
 			txq->axq_qnum, txq->axq_link,
 			ito64(bf->bf_daddr), bf->bf_desc);

@@ -334,7 +334,7 @@ static int ath_tx_prepare(struct ath_softc *sc,
 
 	/* Try to avoid running out of descriptors */
 	if (txq->axq_depth >= (ATH_TXBUF - 20)) {
-		DPRINTF(sc, ATH_DEBUG_FATAL,
+		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: TX queue: %d is full, depth: %d\n",
 			__func__,
 			txctl->qnum,

@@ -1260,7 +1260,7 @@ static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
 	int nacked, txok, nbad = 0, isrifs = 0;
 	enum hal_status status;
 
-	DPRINTF(sc, ATH_DEBUG_TX_PROC,
+	DPRINTF(sc, ATH_DBG_QUEUE,
 		"%s: tx queue %d (%x), link %p\n", __func__,
 		txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
 		txq->axq_link);

@@ -1417,7 +1417,7 @@ static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
 	struct ath_hal *ah = sc->sc_ah;
 
 	(void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
-	DPRINTF(sc, ATH_DEBUG_XMIT, "%s: tx queue [%u] %x, link %p\n",
+	DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
 		__func__, txq->axq_qnum,
 		ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
 }

@@ -1449,7 +1449,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
 		enum hal_status status;
 
 		/* TxDMA not stopped, reset the hal */
-		DPRINTF(sc, ATH_DEBUG_XMIT,
+		DPRINTF(sc, ATH_DBG_XMIT,
 			"%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
 
 		spin_lock_bh(&sc->sc_resetlock);

@@ -1458,7 +1458,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
 			sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 			sc->sc_ht_extprotspacing, true, &status)) {
 
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: unable to reset hardware; hal status %u\n",
 				__func__,
 				status);

@@ -2163,7 +2163,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
 		error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
 			"tx", nbufs * ATH_FRAG_PER_MSDU, ATH_TXDESC);
 		if (error != 0) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: failed to allocate tx descriptors: %d\n",
 				__func__, error);
 			break;

@@ -2173,7 +2173,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
 		error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
 					  "beacon", ATH_BCBUF, 1);
 		if (error != 0) {
-			DPRINTF(sc, ATH_DEBUG_FATAL,
+			DPRINTF(sc, ATH_DBG_FATAL,
 				"%s: failed to allocate "
 				"beacon descripotrs: %d\n",
 				__func__, error);

@@ -2247,7 +2247,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
 		return NULL;
 	}
 	if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
[… more lines in the raw message]

Lines of this file are not shown. View the raw message.

index 5229710..b6281e5 100644
@@ -964,11 +964,12 @@ int ath_suspend(struct ath_softc *sc)
 /* Interrupt handler.  Most of the actual processing is deferred.
  * It's the caller's responsibility to ensure the chip is awake. */
 
-int ath_intr(struct ath_softc *sc)
+irqreturn_t ath_isr(int irq, void *dev)
 {
+	struct ath_softc *sc = dev;
 	struct ath_hal *ah = sc->sc_ah;
 	enum hal_int status;
-	int sched = ATH_ISR_NOSCHED;
+	bool sched = false;
 
 	do {
 		if (sc->sc_invalid) {

@@ -977,10 +978,10 @@ int ath_intr(struct ath_softc *sc)
 			 * touch anything. Note this can happen early
 			 * on if the IRQ is shared.
 			 */
-			return ATH_ISR_NOTMINE;
+			return IRQ_NONE;
 		}
 		if (!ath9k_hw_intrpend(ah)) {	/* shared irq, not for us */
-			return ATH_ISR_NOTMINE;
+			return IRQ_NONE;
 		}
 
 		/*

@@ -999,16 +1000,16 @@ int ath_intr(struct ath_softc *sc)
 		 */
 
 		if (!status)
-			return ATH_ISR_NOTMINE;
+			return IRQ_NONE;
 
 		sc->sc_intrstatus = status;
 
 		if (status & HAL_INT_FATAL) {
 			/* need a chip reset */
-			sched = ATH_ISR_SCHED;
+			sched = true;
 		} else if (status & HAL_INT_RXORN) {
 			/* need a chip reset */
-			sched = ATH_ISR_SCHED;
+			sched = true;
 		} else {
 			if (status & HAL_INT_SWBA) {
 				/* schedule a tasklet for beacon handling */

@@ -1020,7 +1021,7 @@ int ath_intr(struct ath_softc *sc)
 				 *     RXE bit is written, but it doesn't work
 				 *     at least on older hardware revs.
 				 */
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			}
 
 			if (status & HAL_INT_TXURN)

@@ -1028,14 +1029,14 @@ int ath_intr(struct ath_softc *sc)
 				ath9k_hw_updatetxtriglevel(ah, true);
 			/* XXX: optimize this */
 			if (status & HAL_INT_RX)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			if (status & HAL_INT_TX)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			if (status & HAL_INT_BMISS)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			/* carrier sense timeout */
 			if (status & HAL_INT_CST)
-				sched = ATH_ISR_SCHED;
+				sched = true;
 			if (status & HAL_INT_MIB) {
 				/*
 				 * Disable interrupts until we service the MIB

@@ -1059,19 +1060,19 @@ int ath_intr(struct ath_softc *sc)
 					/* Set flag indicating we're waiting
 					 * for a beacon */
 					sc->sc_waitbeacon = 1;
-
-					sched = ATH_ISR_SCHED;
+					sched = true;
 				}
 			}
 		}
 	} while (0);
 
-	if (sched == ATH_ISR_SCHED)
+	if (sched) {
 		/* turn off every interrupt except SWBA */
 		ath9k_hw_set_interrupts(ah, (sc->sc_imask & HAL_INT_SWBA));
+		tasklet_schedule(&sc->intr_tq);
+	}
 
-	return sched;
-
+	return IRQ_HANDLED;
 }
 
 /* Deferred interrupt processing  */

index 964ba58..7024c90 100644
@@ -879,12 +879,6 @@ void ath_setdefantenna(void *sc, u_int antenna);
 
 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 
-#define ATH_ISR_NOSCHED         0x0000	/* Do not schedule bottom half */
-/* Schedule the bottom half for execution */
-#define ATH_ISR_SCHED           0x0001
-/* This was not my interrupt, for shared IRQ's */
-#define ATH_ISR_NOTMINE         0x0002
-
 #define RSSI_LPF_THRESHOLD         -20
 #define ATH_RSSI_EP_MULTIPLIER     (1<<7)  /* pow2 to optimize out * and / */
 #define ATH_RATE_DUMMY_MARKER      0

@@ -1084,7 +1078,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc);
 void ath_deinit(struct ath_softc *sc);
 int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
 int ath_suspend(struct ath_softc *sc);
-int ath_intr(struct ath_softc *sc);
+irqreturn_t ath_isr(int irq, void *dev);
 int ath_reset(struct ath_softc *sc);
 void ath_scan_start(struct ath_softc *sc);
 void ath_scan_end(struct ath_softc *sc);

index 24f69ef..7a8b42e 100644
@@ -1430,26 +1430,6 @@ bad:
 	return error;
 }
 
-static irqreturn_t ath_isr(int irq, void *dev_id)
-{
-	struct ath_softc *sc = dev_id;
-	int sched;
-
-	/* always acknowledge the interrupt */
-	sched = ath_intr(sc);
-
-	switch (sched) {
-	case ATH_ISR_NOSCHED:
-		return IRQ_HANDLED;
-	case ATH_ISR_NOTMINE:
-		return IRQ_NONE;
-	default:
-		tasklet_schedule(&sc->intr_tq);
-		return IRQ_HANDLED;
-
-	}
-}
-
 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	void __iomem *mem;

index b6281e5..25ae517 100644
@@ -627,7 +627,6 @@ int ath_vap_attach(struct ath_softc *sc,
 		   int if_id,
 		   struct ieee80211_vif *if_data,
 		   enum hal_opmode opmode,
-		   enum hal_opmode iv_opmode,
 		   int nostabeacons)
 {
 	struct ath_vap *avp;

@@ -664,7 +663,7 @@ int ath_vap_attach(struct ath_softc *sc,
 	memzero(avp, sizeof(struct ath_vap));
 	avp->av_if_data = if_data;
 	/* Set the VAP opmode */
-	avp->av_opmode = iv_opmode;
+	avp->av_opmode = opmode;
 	avp->av_bslot = -1;
 	INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
 	INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);

index 7024c90..10ec3ae 100644
@@ -799,7 +799,6 @@ int ath_vap_attach(struct ath_softc *sc,
 		   int if_id,
 		   struct ieee80211_vif *if_data,
 		   enum hal_opmode opmode,
-		   enum hal_opmode iv_opmode,
 		   int nostabeacons);
 int ath_vap_detach(struct ath_softc *sc, int if_id);
 int ath_vap_config(struct ath_softc *sc,

index 7a8b42e..59f1204 100644
@@ -395,7 +395,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
 	/* Support only vap for now */
 
 	if (sc->sc_nvaps)
-		return -1;
+		return -ENOBUFS;
 
 	switch (conf->type) {
 	case IEEE80211_IF_TYPE_STA:

@@ -405,24 +405,25 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
 		ic_opmode = HAL_M_IBSS;
 		break;
 	default:
-		break;
+		DPRINTF(sc, ATH_DBG_FATAL,
+			"%s: Only STA and IBSS are supported currently\n",
+			__func__);
+		return -EOPNOTSUPP;
 	}
 
 	DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
 		__func__,
 		ic_opmode);
 
-	error = ath_vap_attach(sc, 0, conf->vif, ic_opmode, ic_opmode, 0);
+	error = ath_vap_attach(sc, 0, conf->vif, ic_opmode, 0);
 	if (error) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unable to attach vap, error: %d\n",
 			__func__, error);
-		goto bad;
+		return error;
 	}
 
 	return 0;
-bad:
-	return -1;
 }
 
 static void ath9k_remove_interface(struct ieee80211_hw *hw,

index 6fa1eb6..c3294c0 100644
@@ -622,17 +622,15 @@ struct hal_country_entry {
 
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
-#define OS_REG_RMW(_a, _r, _set, _clr)    \
+#define REG_RMW(_a, _r, _set, _clr)    \
 	REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
-#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
+#define REG_RMW_FIELD(_a, _r, _f, _v) \
 	REG_WRITE(_a, _r, \
 	(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
-#define OS_REG_SET_BIT(_a, _r, _f) \
+#define REG_SET_BIT(_a, _r, _f) \
 	REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
-#define OS_REG_CLR_BIT(_a, _r, _f) \
+#define REG_CLR_BIT(_a, _r, _f) \
 	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
-#define OS_REG_ath9k_regd_is_bit_set(_a, _r, _f) \
-	((REG_READ(_a, _r) & _f) != 0)
 
 #define HAL_COMP_BUF_MAX_SIZE   9216
 #define HAL_COMP_BUF_ALIGN_SIZE 512

858 lines not on this page · raw message

index e1fc9c6..6751bed 100644
@@ -150,8 +150,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 			refDivA = 1;
 			channelSel = (freq * 0x8000) / 15;
 
-			OS_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
-					 AR_AN_SYNTH9_REFDIVA, refDivA);
+			REG_RMW_FIELD(ah, AR_AN_SYNTH9,
+				      AR_AN_SYNTH9_REFDIVA, refDivA);
 		}
 		if (!fracMode) {
 			ndiv = (freq * (refDivA >> aModeRefSel)) / 60;

index 0507940..596591e 100644
@@ -84,7 +84,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
 
 	flags = HAL_TXDESC_NOACK;
 
-	if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol) {
+	if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
 		ds->ds_link = bf->bf_daddr; /* self-linked */
 		flags |= HAL_TXDESC_VEOL;
 		/* Let hardware handle antenna switching. */

@@ -97,11 +97,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
 		 * SWBA's
 		 * XXX assumes two antenna
 		 */
-		if (sc->sc_stagbeacons)
-			antenna = ((sc->ast_be_xmit /
-					sc->sc_nbcnvaps) & 1 ? 2 : 1);
-		else
-			antenna = (sc->ast_be_xmit & 1 ? 2 : 1);
+		antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1);
 	}
 
 	ds->ds_data = bf->bf_buf_addr;

@@ -272,7 +268,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
 		 * the lock again which is a common function and that
 		 * acquires txq lock inside.
 		 */
-		if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
+		if (sc->sc_nvaps > 1) {
 			ath_tx_draintxq(sc, cabq, false);
 			DPRINTF(sc, ATH_DBG_BEACON,
 				"%s: flush previous cabq traffic\n", __func__);

@@ -377,7 +373,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 				struct ath_buf, list);
 		list_del(&avp->av_bcbuf->list);
 
-		if (sc->sc_opmode == HAL_M_HOSTAP || !sc->sc_hasveol) {
+		if (sc->sc_opmode == HAL_M_HOSTAP ||
+			!sc->sc_ah->ah_caps.halVEOLSupport) {
 			int slot;
 			/*
 			 * Assign the vap to a beacon xmit slot. As

@@ -435,7 +432,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 	 * of the beacon frame leaves the tstamp field immediately
 	 * following the header.
 	 */
-	if (sc->sc_stagbeacons && avp->av_bslot > 0) {
+	if (avp->av_bslot > 0) {
 		u_int64_t tsfadjust;
 		__le64 val;
 		int intval;

@@ -460,7 +457,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
 
 		DPRINTF(sc, ATH_DBG_BEACON,
 			"%s: %s beacons, bslot %d intval %u tsfadjust %llu\n",
-			__func__, sc->sc_stagbeacons ? "stagger" : "burst",
+			__func__, "stagger",
 			avp->av_bslot, intval, (unsigned long long)tsfadjust);
 
 		wh = (struct ieee80211_hdr *)skb->data;

@@ -552,6 +549,9 @@ void ath9k_beacon_tasklet(unsigned long data)
 	u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
 	u_int32_t show_cycles = 0;
 	u_int32_t bc = 0; /* beacon count */
+	u_int64_t tsf;
+	u_int32_t tsftu;
+	u_int16_t intval;
 
 	if (sc->sc_noreset) {
 		show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,

@@ -636,55 +636,29 @@ void ath9k_beacon_tasklet(unsigned long data)
 	}
 
 	/*
-	 * Generate beacon frames.  If we are sending frames
-	 * staggered then calculate the slot for this frame based
+	 * Generate beacon frames. we are sending frames
+	 * staggered so calculate the slot for this frame based
 	 * on the tsf to safeguard against missing an swba.
-	 * Otherwise we are bursting all frames together and need
-	 * to generate a frame for each vap that is up and running.
 	 */
-	if (sc->sc_stagbeacons) {
-		/* staggered beacons */
-		u_int64_t tsf;
-		u_int32_t tsftu;
-		u_int16_t intval;
 
-		/* FIXME: Use default value for now - Sujith */
-		intval = ATH_DEFAULT_BINTVAL;
+	/* FIXME: Use default value for now - Sujith */
+	intval = ATH_DEFAULT_BINTVAL;
 
-		tsf = ath9k_hw_gettsf64(ah);
-		tsftu = TSF_TO_TU(tsf>>32, tsf);
-		slot = ((tsftu % intval) * ATH_BCBUF) / intval;
-		if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
-		DPRINTF(sc, ATH_DBG_BEACON,
+	tsf = ath9k_hw_gettsf64(ah);
+	tsftu = TSF_TO_TU(tsf>>32, tsf);
+	slot = ((tsftu % intval) * ATH_BCBUF) / intval;
+	if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
+	DPRINTF(sc, ATH_DBG_BEACON,
 			"%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
 			__func__, slot, (unsigned long long) tsf, tsftu,
 			intval, if_id);
-		bfaddr = 0;
-		if (if_id != ATH_IF_ID_ANY) {
-			bf = ath_beacon_generate(sc, if_id);
-			if (bf != NULL) {
-				bfaddr = bf->bf_daddr;
-				bc = 1;
-			}
+	bfaddr = 0;
+	if (if_id != ATH_IF_ID_ANY) {
+		bf = ath_beacon_generate(sc, if_id);
+		if (bf != NULL) {
+			bfaddr = bf->bf_daddr;
+			bc = 1;
 		}
-	} else {
-		/* XXX: Clean this up, move work to a helper */
-		/* burst'd beacons */
-		u_int32_t *bflink;
-		bflink = &bfaddr;
-		/* XXX rotate/randomize order? */
-		for (slot = 0; slot < ATH_BCBUF; slot++) {
-			if_id = sc->sc_bslot[slot];
-			if (if_id != ATH_IF_ID_ANY) {
-				bf = ath_beacon_generate(sc, if_id);
-				if (bf != NULL) {
-					*bflink = bf->bf_daddr;
-					bflink = &bf->bf_desc->ds_link;
-					bc++;
-				}
-			}
-		}
-		*bflink = 0;    /* link of last frame */
 	}
 	/*
 	 * Handle slot time change when a non-ERP station joins/leaves

@@ -803,11 +777,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		 */
 		/* NB: the beacon interval is kept internally in TU's */
 		intval = conf.beacon_interval & HAL_BEACON_PERIOD;
-		if (sc->sc_stagbeacons)
-			intval /= ATH_BCBUF;    /* for staggered beacons */
-		if ((sc->sc_nostabeacons) &&
-		    (av_opmode == HAL_M_HOSTAP))
-			nexttbtt = 0;
+		intval /= ATH_BCBUF;    /* for staggered beacons */
 	} else {
 		intval = conf.beacon_interval & HAL_BEACON_PERIOD;
 	}

@@ -819,10 +789,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 	DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
 		__func__, nexttbtt, intval, conf.beacon_interval);
 	/* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
-	if ((sc->sc_opmode == HAL_M_STA) ||
-	     ((sc->sc_opmode == HAL_M_HOSTAP) &&
-	      (av_opmode == HAL_M_STA) &&
-	      (sc->sc_nostabeacons))) {
+	if (sc->sc_opmode == HAL_M_STA) {
 		struct hal_beacon_state bs;
 		u_int64_t tsf;
 		u_int32_t tsftu;

@@ -932,12 +899,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 			, bs.bs_timoffset
 			);
 
-		if (!(sc->sc_nostabeacons)) {
-			ath9k_hw_set_interrupts(ah, 0);
-			ath9k_hw_set_sta_beacon_timers(ah, &bs);
-			sc->sc_imask |= HAL_INT_BMISS;
-			ath9k_hw_set_interrupts(ah, sc->sc_imask);
-		}
+		ath9k_hw_set_interrupts(ah, 0);
+		ath9k_hw_set_sta_beacon_timers(ah, &bs);
+		sc->sc_imask |= HAL_INT_BMISS;
+		ath9k_hw_set_interrupts(ah, sc->sc_imask);
 	} else {
 		u_int64_t tsf;
 		u_int32_t tsftu;

@@ -973,7 +938,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 			 * deal with things.
 			 */
 			intval |= HAL_BEACON_ENA;
-			if (!sc->sc_hasveol)
+			if (!ah->ah_caps.halVEOLSupport)
 				sc->sc_imask |= HAL_INT_SWBA;
 			ath_beaconq_config(sc);
 		} else if (sc->sc_opmode == HAL_M_HOSTAP) {

@@ -992,7 +957,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
 		 * When using a self-linked beacon descriptor in
 		 * ibss mode load it once here.
 		 */
-		if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol)
+		if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
 			ath_beacon_start_adhoc(sc, 0);
 	}
 #undef TSF_TO_TU

176 lines not on this page · raw message

index 10ec3ae..fdd0f87 100644
@@ -136,7 +136,6 @@ enum ATH_DEBUG {
 /* Per-instance load-time (note: NOT run-time) configurations
  * for Atheros Device */
 struct ath_config {
-	u_int8_t    chainmask_sel; /* enable automatic tx chainmask selection */
 	u_int32_t   ath_aggr_prot;
 	u_int16_t   txpowlimit;
 	u_int16_t   txpowlimit_override;

@@ -798,8 +797,7 @@ struct ath_vap {
 int ath_vap_attach(struct ath_softc *sc,
 		   int if_id,
 		   struct ieee80211_vif *if_data,
-		   enum hal_opmode opmode,
-		   int nostabeacons);
+		   enum hal_opmode opmode);
 int ath_vap_detach(struct ath_softc *sc, int if_id);
 int ath_vap_config(struct ath_softc *sc,
 	int if_id, struct ath_vap_config *if_config);

@@ -942,30 +940,13 @@ struct ath_softc {
 	enum hal_opmode         sc_opmode;  /* current operating mode */
 
 	/* Properties, Config */
-	unsigned int
-		sc_invalid,	/* being detached */
-		sc_hasveol             : 1, /* tx VEOL support */
-		sc_beacons             : 1, /* beacons running */
-		sc_hasbmask            : 1, /* bssid mask support */
-		sc_hastsfadd           : 1, /* tsf adjust support */
-		sc_scanning            : 1, /* scanning active */
-		sc_nostabeacons        : 1, /* no beacons for station */
-		sc_hasclrkey           : 1, /* CLR key supported */
-		sc_stagbeacons         : 1, /* use staggered beacons */
-		sc_txaggr              : 1, /* enable 11n tx aggregation */
-		sc_rxaggr              : 1, /* enable 11n rx aggregation */
-		sc_hasautosleep        : 1, /* automatic sleep after TIM */
-		sc_waitbeacon          : 1, /* waiting for first beacon
-						after waking up */
-		sc_no_tx_3_chains      : 1, /* user, hardware, regulatory
-					or country may disallow transmit on
-					three chains. */
-		sc_update_chainmask    : 1, /* change chain mask */
-		sc_rx_chainmask_detect : 1, /* enable rx chain mask detection */
-		sc_rx_chainmask_start  : 1, /* start rx chain mask detection */
-		sc_hashtsupport        : 1, /* supports 11n */
-		sc_full_reset          : 1, /* force full reset */
-		sc_slowAntDiv          : 1; /* enable slow antenna diversity */
+	u_int8_t                sc_invalid;	/* being detached */
+	u_int8_t                sc_beacons;	/* beacons running */
+	u_int8_t                sc_scanning;	/* scanning active */
+	u_int8_t                sc_txaggr;	/* enable 11n tx aggregation */
+	u_int8_t                sc_rxaggr;	/* enable 11n rx aggregation */
+	u_int8_t                sc_update_chainmask;	/* change chain mask */
+	u_int8_t                sc_full_reset;		/* force full reset */
 	enum wireless_mode      sc_curmode;     /* current phy mode */
 	u_int16_t               sc_curtxpow;    /* current tx power limit */
 	u_int16_t               sc_curaid;      /* current association id */

index 08b4bd4..a16dbfb 100644
@@ -6719,14 +6719,8 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
 		}
 		return false;
 	case HAL_CAP_TSF_ADJUST:
-		switch (capability) {
-		case 0:
-			return true;
-		case 1:
-			return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
-				true : false;
-		}
-		return false;
+		return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
+			true : false;
 	case HAL_CAP_RFSILENT:
 		if (capability == 3)
 			return false;

index 59f1204..7ef0d58 100644
@@ -415,7 +415,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
 		__func__,
 		ic_opmode);
 
-	error = ath_vap_attach(sc, 0, conf->vif, ic_opmode, 0);
+	error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
 	if (error) {
 		DPRINTF(sc, ATH_DBG_FATAL,
 			"%s: Unable to attach vap, error: %d\n",

@@ -443,8 +443,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
 	}
 
 #ifdef CONFIG_SLOW_ANT_DIV
-	if (sc->sc_slowAntDiv)
-		ath_slow_ant_div_stop(&sc->sc_antdiv);
+	ath_slow_ant_div_stop(&sc->sc_antdiv);
 #endif
 
 	/* Update ratectrl */

@@ -526,10 +525,6 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
 			ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 					       sc->sc_curaid);
 
-			/* Enable rx chain mask detection if configured
-			   to do so */
-			sc->sc_rx_chainmask_detect = 0;
-
 			/* Set aggregation protection mode parameters */
 			sc->sc_config.ath_aggr_prot = 0;
 

@@ -1369,7 +1364,7 @@ static int ath_attach(u_int16_t devid,
 		sc->rates[IEEE80211_BAND_2GHZ];
 	sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
 
-	if (sc->sc_hashtsupport)
+	if (sc->sc_ah->ah_caps.halHTSupport)
 		/* Setup HT capabilities for 2.4Ghz*/
 		setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
 

@@ -1384,7 +1379,7 @@ static int ath_attach(u_int16_t devid,
 		sc->sbands[IEEE80211_BAND_5GHZ].band =
 			IEEE80211_BAND_5GHZ;
 
-		if (sc->sc_hashtsupport)
+		if (sc->sc_ah->ah_caps.halHTSupport)
 			/* Setup HT capabilities for 5Ghz*/
 			setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
 

120 lines not on this page · raw message

index 152f9f4..2e3ae65 100644
@@ -780,7 +780,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 * let rate series flags determine which rates will actually
 	 * use RTS.
 	 */
-	if (sc->sc_hashtsupport && bf->bf_isdata) {
+	if (ah->ah_caps.halHTSupport && bf->bf_isdata) {
 		BUG_ON(!an);
 		/*
 		 * 802.11g protection not needed, use our default behavior

@@ -896,7 +896,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 	 * For non-HT devices, calculate RTS/CTS duration in software
 	 * and disable multi-rate retry.
 	 */
-	if (flags && !sc->sc_hashtsupport) {
+	if (flags && !ah->ah_caps.halHTSupport) {
 		/*
 		 * Compute the transmit duration based on the frame
 		 * size and the size of an ACK frame.  We call into the

index d2c7109..a3dee36 100644
@@ -111,10 +111,9 @@ static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
 		 __func__, rd);
 
 	if (rd & COUNTRY_ERD_FLAG) {
-
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
-			 "%s: EEPROM setting is country code %u\n",
-			 __func__, rd & ~COUNTRY_ERD_FLAG);
+			"%s: EEPROM setting is country code %u\n",
+			__func__, rd & ~COUNTRY_ERD_FLAG);
 		return cc == (rd & ~COUNTRY_ERD_FLAG);
 	}
 

@@ -193,8 +192,8 @@ bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah)
 	return false;
 }
 
-static struct country_code_to_enum_rd *ath9k_regd_find_country(u_int16_t
-							       countryCode)
+static struct country_code_to_enum_rd*
+ath9k_regd_find_country(u_int16_t countryCode)
 {
 	int i;
 

@@ -283,7 +282,6 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 	}
 
 	if ((regDmn & MULTI_DOMAIN_MASK) == 0) {
-
 		for (i = 0, found = 0;
 		     (i < ARRAY_SIZE(regDomainPairs)) && (!found); i++) {
 			if (regDomainPairs[i].regDmnEnum == regDmn) {

@@ -293,8 +291,8 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 		}
 		if (!found) {
 			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
-				 "%s: Failed to find reg domain pair %u\n",
-				 __func__, regDmn);
+				"%s: Failed to find reg domain pair %u\n",
+				__func__, regDmn);
 			return false;
 		}
 		if (!(channelFlag & CHANNEL_2GHZ)) {

@@ -310,8 +308,8 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
 	found = ath9k_regd_is_valid_reg_domain(regDmn, rd);
 	if (!found) {
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
-			 "%s: Failed to find unitary reg domain %u\n",
-			 __func__, regDmn);
+			"%s: Failed to find unitary reg domain %u\n",
+			__func__, regDmn);
 		return false;
 	} else {
 		rd->pscan &= regPair->pscanMask;

@@ -396,6 +394,186 @@ static void ath9k_regd_init_rf_buffer(struct hal_channel_internal *ichans,
 }
 #endif
 
+static bool
+ath9k_regd_add_channel(struct ath_hal *ah,
+		       u_int16_t c,
+		       u_int16_t c_lo,
+		       u_int16_t c_hi,
+		       u_int16_t maxChan,
+		       u_int8_t ctl,
+		       int pos,
+		       struct regDomain rd5GHz,
+		       struct RegDmnFreqBand *fband,
+		       struct regDomain *rd,
+		       const struct cmode *cm,
+		       struct hal_channel_internal *ichans,
+		       bool enableExtendedChannels)
+{
+	struct hal_channel_internal icv;
+
+	if (!(c_lo <= c && c <= c_hi)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: c %u out of range [%u..%u]\n",
+			__func__, c, c_lo, c_hi);
+		return false;
+	}
+	if ((fband->channelBW == CHANNEL_HALF_BW) &&
+	    !ah->ah_caps.halChanHalfRate) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: Skipping %u half rate channel\n",
+			__func__, c);
+		return false;
+	}
+
+	if ((fband->channelBW == CHANNEL_QUARTER_BW) &&
+	    !ah->ah_caps.halChanQuarterRate) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: Skipping %u quarter rate channel\n",
+			__func__, c);
+		return false;
+	}
+
+	if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"%s: c %u > maxChan %u\n",
+			__func__, c, maxChan);
+		return false;
+	}
+
+	if ((fband->usePassScan & IS_ECM_CHAN) && !enableExtendedChannels) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping ecm channel\n");
+		return false;
+	}
+
+	if ((rd->flags & NO_HOSTAP) && (ah->ah_opmode == HAL_M_HOSTAP)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HOSTAP channel\n");
+		return false;
+	}
+
+	if (IS_HT40_MODE(cm->mode) &&
+	    !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_FCC_DFS_HT40)) &&
+	    (fband->useDfs) &&
+	    (rd->conformanceTestLimit != MKK)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HT40 channel (en_fcc_dfs_ht40 = 0)\n");
+		return false;
+	}
+
+	if (IS_HT40_MODE(cm->mode) &&
+	    !(ath9k_regd_get_eeprom_reg_ext_bits(ah,
+						 REG_EXT_JAPAN_NONDFS_HT40)) &&
+	    !(fband->useDfs) && (rd->conformanceTestLimit == MKK)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HT40 channel (en_jap_ht40 = 0)\n");
+		return false;
+	}
+
+	if (IS_HT40_MODE(cm->mode) &&
+	    !(ath9k_regd_get_eeprom_reg_ext_bits(ah, REG_EXT_JAPAN_DFS_HT40)) &&
+	    (fband->useDfs) &&
+	    (rd->conformanceTestLimit == MKK)) {
+		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+			"Skipping HT40 channel (en_jap_dfs_ht40 = 0)\n");
+		return false;
+	}
+
+	memset(&icv, 0, sizeof(icv));
+	icv.channel = c;
+	icv.channelFlags = cm->flags;
+
+	switch (fband->channelBW) {
+	case CHANNEL_HALF_BW:
+		icv.channelFlags |= CHANNEL_HALF;
+		break;
+	case CHANNEL_QUARTER_BW:
+		icv.channelFlags |= CHANNEL_QUARTER;
+		break;
+	}
+
+	icv.maxRegTxPower = fband->powerDfs;
+	icv.antennaMax = fband->antennaMax;
+	icv.regDmnFlags = rd->flags;
+	icv.conformanceTestLimit = ctl;
+	if (fband->usePassScan & rd->pscan)
+		icv.channelFlags |= CHANNEL_PASSIVE;
+	else
+		icv.channelFlags &= ~CHANNEL_PASSIVE;
+	if (fband->useDfs & rd->dfsMask)
+		icv.privFlags = CHANNEL_DFS;
+	else
+		icv.privFlags = 0;
+	if (rd->flags & LIMIT_FRAME_4MS)
+		icv.privFlags |= CHANNEL_4MS_LIMIT;
+	if (icv.privFlags & CHANNEL_DFS)
+		icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+	if (icv.regDmnFlags & ADHOC_PER_11D)
+		icv.privFlags |= CHANNEL_PER_11D_ADHOC;
+
+	if (icv.channelFlags & CHANNEL_PASSIVE) {
+		if ((icv.channel < 2412) || (icv.channel > 2462)) {
+			if (rd5GHz.regDmnEnum == MKK1 ||
+			    rd5GHz.regDmnEnum == MKK2) {
+				u_int32_t regcap = ah->ah_caps.halRegCap;
+				if (!(regcap &
+				      (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
+				       AR_EEPROM_EEREGCAP_EN_KK_U2 |
+				       AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) &&
+				    isUNII1OddChan(icv.channel)) {
+					icv.channelFlags &= ~CHANNEL_PASSIVE;
+				} else {
+					icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+				}
+			} else {
+				icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+			}
+		}
+	}
+
+	if (cm->mode & (ATH9K_MODE_SEL_11A |
+			ATH9K_MODE_SEL_11NA_HT20 |
+			ATH9K_MODE_SEL_11NA_HT40PLUS |
+			ATH9K_MODE_SEL_11NA_HT40MINUS)) {
+		if (icv.regDmnFlags & (ADHOC_NO_11A | DISALLOW_ADHOC_11A))
+			icv.privFlags |= CHANNEL_DISALLOW_ADHOC;
+	}
+
+	memcpy(&ichans[pos], &icv,
+	       sizeof(struct hal_channel_internal));
+
+	return true;
+}
+
+static bool ath9k_regd_japan_check(struct ath_hal *ah,
+				   int b,
+				   struct regDomain *rd5GHz)
+{
+	bool skipband = false;
+	int i;
+	u_int32_t regcap;
+
+	for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
+		if (j_bandcheck[i].freqbandbit == b) {
+			regcap = ah->ah_caps.halRegCap;
+			if ((j_bandcheck[i].eepromflagtocheck & regcap) == 0) {
+				skipband = true;
+			} else if ((regcap & AR_EEPROM_EEREGCAP_EN_KK_U2) ||
+				  (regcap & AR_EEPROM_EEREGCAP_EN_KK_MIDBAND)) {
+				rd5GHz->dfsMask |= DFS_MKK4;
+				rd5GHz->pscan |= PSCAN_MKK3;
+			}
+			break;
+		}
+	}
+
+	DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
+		"%s: Skipping %d freq band\n",
+		__func__, j_bandcheck[i].freqbandbit);
+
+	return skipband;
+}
+
 bool
 ath9k_regd_init_channels(struct ath_hal *ah,
 			 struct hal_channel *chans, u_int maxchans,

@@ -412,7 +590,6 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 	struct hal_channel_internal *ichans = &ah->ah_channels[0];
 	int next = 0, b;
 	u_int8_t ctl;
-	int is_quarterchan_cap, is_halfchan_cap;
 	int regdmn;
 	u_int16_t chanSep;
 

@@ -422,31 +599,27 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 		 enableExtendedChannels ? " Enable ecm" : "");
 
 	if (!ath9k_regd_is_ccode_valid(ah, cc)) {
-
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
-			 "%s: invalid country code %d\n", __func__, cc);
+			"%s: invalid country code %d\n", __func__, cc);
 		return false;
 	}
 
 	if (!ath9k_regd_is_eeprom_valid(ah)) {
-
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
-			 "%s: invalid EEPROM contents\n", __func__);
+			"%s: invalid EEPROM contents\n", __func__);
 		return false;
 	}
 
 	ah->ah_countryCode = ath9k_regd_get_default_country(ah);
 
 	if (ah->ah_countryCode == CTRY_DEFAULT) {
-
 		ah->ah_countryCode = cc & COUNTRY_CODE_MASK;
-
 		if ((ah->ah_countryCode == CTRY_DEFAULT) &&
 		    (ath9k_regd_get_eepromRD(ah) == CTRY_DEFAULT)) {
-
 			ah->ah_countryCode = CTRY_UNITED_STATES;
 		}
 	}
+
 #ifdef AH_SUPPORT_11D
 	if (ah->ah_countryCode == CTRY_DEFAULT) {
 		regdmn = ath9k_regd_get_eepromRD(ah);

@@ -454,22 +627,19 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 	} else {
 #endif
 		country = ath9k_regd_find_country(ah->ah_countryCode);
-
 		if (country == NULL) {
 			DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
-				 "Country is NULL!!!!, cc= %d\n",
-				 ah->ah_countryCode);
+				"Country is NULL!!!!, cc= %d\n",
+				ah->ah_countryCode);
 			return false;
 		} else {
 			regdmn = country->regDmnEnum;
 #ifdef AH_SUPPORT_11D
-			if (((ath9k_regd_get_eepromRD(ah) & WORLD_SKU_MASK)
-			     == WORLD_SKU_PREFIX)
-			    && (cc == CTRY_UNITED_STATES)) {
+			if (((ath9k_regd_get_eepromRD(ah) &
+			      WORLD_SKU_MASK) == WORLD_SKU_PREFIX) &&
+			    (cc == CTRY_UNITED_STATES)) {
 				if (!isWwrSKU_NoMidband(ah)
-				    &&
-				    ath9k_regd_is_fcc_midband_supported
-				    (ah))
+				    && ath9k_regd_is_fcc_midband_supported(ah))
 					regdmn = FCC3_FCCA;
 				else
 					regdmn = FCC1_FCCA;

@@ -479,35 +649,38 @@ ath9k_regd_init_channels(struct ath_hal *ah,
 #ifdef AH_SUPPORT_11D
 	}
 #endif
-
-	if (!ath9k_regd_get_wmode_regdomain
-	    (ah, regdmn, ~CHANNEL_2GHZ, &rd5GHz)) {
+	if (!ath9k_regd_get_wmode_regdomain(ah,
+					    regdmn,
+					    ~CHANNEL_2GHZ,
+					    &rd5GHz)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 			"%s: couldn't find unitary "
 			"5GHz reg domain for country %u\n",
-			 __func__, ah->ah_countryCode);
+			__func__, ah->ah_countryCode);
 		return false;
 	}
-	if (!ath9k_regd_get_wmode_regdomain
-	    (ah, regdmn, CHANNEL_2GHZ, &rd2GHz)) {
+	if (!ath9k_regd_get_wmode_regdomain(ah,
+					    regdmn,
+					    CHANNEL_2GHZ,
+					    &rd2GHz)) {
 		DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 			"%s: couldn't find unitary 2GHz "
 			"reg domain for country %u\n",
-			 __func__, ah->ah_countryCode);
+			__func__, ah->ah_countryCode);
 		return false;
 	}
 
-	if (!isWwrSKU(ah)
-	    && ((rd5GHz.regDmnEnum == FCC1)
-		|| (rd5GHz.regDmnEnum == FCC2))) {
+	if (!isWwrSKU(ah) && ((rd5GHz.regDmnEnum == FCC1) ||
+			      (rd5GHz.regDmnEnum == FCC2))) {
 		if (ath9k_regd_is_fcc_midband_supported(ah)) {
-
-			if (!ath9k_regd_get_wmode_regdomain
-			    (ah, FCC3_FCCA, ~CHANNEL_2GHZ, &rd5GHz)) {
+			if (!ath9k_regd_get_wmode_regdomain(ah,
+							    FCC3_FCCA,
+							    ~CHANNEL_2GHZ,
+							    &rd5GHz)) {
 				DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
 					"%s: couldn't find unitary 5GHz "
 					"reg domain for country %u\n",
-					 __func__, ah->ah_countryCode);
+					__func__, ah->ah_countryCode);
 				return false;
 			}
 		}