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SH2(A) cache update

PATCH In review Yoshinori Sato 2 participants 4 messages Jul 6, 2008 – Aug 5, 2008 SuperH

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Yoshinori Sato

author maintainer
#0 lore raw

PATCH 1/1 SH2(A) cache update

Include
- SH2 (7619) Writeback support.
- SH2A cache handling fix.

Signed-off-by Yoshinori Sato <[email protected]>
arch/sh/mm/Kconfig +0 -1
index 29d8e3c..a84a104 100644
@@ -229,7 +229,6 @@ choice
 
 config CACHE_WRITEBACK
 	bool "Write-back"
-	depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
 
 config CACHE_WRITETHROUGH
 	bool "Write-through"
arch/sh/mm/Makefile_32 +3 -1
index e295db6..e3f95b2 100644
@@ -5,7 +5,9 @@
 obj-y			:= init.o extable_32.o consistent.o
 
 ifndef CONFIG_CACHE_OFF
-obj-$(CONFIG_CPU_SH2)		+= cache-sh2.o
+sh2-$(CONFIG_CPU_SH2)		:= cache-sh2.o
+sh2-$(CONFIG_CPU_SH2A)		:= cache-sh2a.o
+obj-$(CONFIG_CPU_SH2)		+= $(sh2-y)
 obj-$(CONFIG_CPU_SH3)		+= cache-sh3.o
 obj-$(CONFIG_CPU_SH4)		+= cache-sh4.o
 obj-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o
arch/sh/mm/cache-sh2.c +70 -0

86 lines not on this page · raw message

arch/sh/mm/cache-sh2a.c new file +101 -0

101 lines not on this page · raw message

include/asm-sh/cpu-sh2/cache.h +4 -2
index 4e0b165..673515b 100644
@@ -21,11 +21,11 @@
 #define CCR		0xffffffec
 
 #define CCR_CACHE_CE	0x01	/* Cache enable */
-#define CCR_CACHE_WT	0x06    /* CCR[bit1=1,bit2=1] */
+#define CCR_CACHE_WT	0x02    /* CCR[bit1=1,bit2=1] */
 				/* 0x00000000-0x7fffffff: Write-through  */
 				/* 0x80000000-0x9fffffff: Write-back     */
                                 /* 0xc0000000-0xdfffffff: Write-through  */
-#define CCR_CACHE_CB	0x00    /* CCR[bit1=0,bit2=0] */
+#define CCR_CACHE_CB	0x04    /* CCR[bit1=0,bit2=0] */
 				/* 0x00000000-0x7fffffff: Write-back     */
 				/* 0x80000000-0x9fffffff: Write-through  */
                                 /* 0xc0000000-0xdfffffff: Write-back     */

@@ -36,6 +36,8 @@
 
 #define CCR_CACHE_ENABLE	CCR_CACHE_CE
 #define CCR_CACHE_INVALIDATE	CCR_CACHE_CF
+#define CACHE_PHYSADDR_MASK	0x1ffffc00
+
 #endif
 
 #endif /* __ASM_CPU_SH2_CACHE_H */
include/asm-sh/cpu-sh2a/cache.h +3 -0
index afe228b..defb0ba 100644
@@ -36,5 +36,8 @@
 
 #define CCR_CACHE_ENABLE	(CCR_CACHE_OCE | CCR_CACHE_ICE)
 #define CCR_CACHE_INVALIDATE	(CCR_CACHE_OCI | CCR_CACHE_ICI)
+#define CCR_ICACHE_INVALIDATE	CCR_CACHE_ICI
+#define CCR_OCACHE_INVALIDATE	CCR_CACHE_OCI
+#define CACHE_PHYSADDR_MASK	0x1ffffc00
 
 #endif /* __ASM_CPU_SH2A_CACHE_H */
Signature · 2 lines
Yoshinori Sato
<[email protected]>
author maintainer
#1 lore raw

Sorry I forget flush_icache_region.
Update patch.

Signed-off-by Yoshinori Sato <[email protected]>
arch/sh/mm/Kconfig +0 -1
index 29d8e3c..a84a104 100644
@@ -229,7 +229,6 @@ choice
 
 config CACHE_WRITEBACK
 	bool "Write-back"
-	depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
 
 config CACHE_WRITETHROUGH
 	bool "Write-through"
arch/sh/mm/Makefile_32 +7 -4
index e295db6..70e0906 100644
@@ -5,12 +5,15 @@
 obj-y			:= init.o extable_32.o consistent.o
 
 ifndef CONFIG_CACHE_OFF
-obj-$(CONFIG_CPU_SH2)		+= cache-sh2.o
-obj-$(CONFIG_CPU_SH3)		+= cache-sh3.o
-obj-$(CONFIG_CPU_SH4)		+= cache-sh4.o
-obj-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o
+cache-$(CONFIG_CPU_SH2)		:= cache-sh2.o
+cache-$(CONFIG_CPU_SH2A)	:= cache-sh2a.o
+cache-$(CONFIG_CPU_SH3)		:= cache-sh3.o
+cache-$(CONFIG_CPU_SH4)		:= cache-sh4.o
+cache-$(CONFIG_SH7705_CACHE_32KB)	+= cache-sh7705.o
 endif
 
+obj-y			+= $(cache-y)
+
 mmu-y			:= tlb-nommu.o pg-nommu.o
 mmu-$(CONFIG_MMU)	:= fault_32.o tlbflush_32.o ioremap_32.o
arch/sh/mm/cache-sh2.c +70 -0

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arch/sh/mm/cache-sh2a.c new file +134 -0

134 lines not on this page · raw message

include/asm-sh/cpu-sh2/cache.h +4 -2
index 4e0b165..673515b 100644
@@ -21,11 +21,11 @@
 #define CCR		0xffffffec
 
 #define CCR_CACHE_CE	0x01	/* Cache enable */
-#define CCR_CACHE_WT	0x06    /* CCR[bit1=1,bit2=1] */
+#define CCR_CACHE_WT	0x02    /* CCR[bit1=1,bit2=1] */
 				/* 0x00000000-0x7fffffff: Write-through  */
 				/* 0x80000000-0x9fffffff: Write-back     */
                                 /* 0xc0000000-0xdfffffff: Write-through  */
-#define CCR_CACHE_CB	0x00    /* CCR[bit1=0,bit2=0] */
+#define CCR_CACHE_CB	0x04    /* CCR[bit1=0,bit2=0] */
 				/* 0x00000000-0x7fffffff: Write-back     */
 				/* 0x80000000-0x9fffffff: Write-through  */
                                 /* 0xc0000000-0xdfffffff: Write-back     */

@@ -36,6 +36,8 @@
 
 #define CCR_CACHE_ENABLE	CCR_CACHE_CE
 #define CCR_CACHE_INVALIDATE	CCR_CACHE_CF
+#define CACHE_PHYSADDR_MASK	0x1ffffc00
+
 #endif
 
 #endif /* __ASM_CPU_SH2_CACHE_H */
include/asm-sh/cpu-sh2a/cache.h +3 -0
index afe228b..defb0ba 100644
@@ -36,5 +36,8 @@
 
 #define CCR_CACHE_ENABLE	(CCR_CACHE_OCE | CCR_CACHE_ICE)
 #define CCR_CACHE_INVALIDATE	(CCR_CACHE_OCI | CCR_CACHE_ICI)
+#define CCR_ICACHE_INVALIDATE	CCR_CACHE_ICI
+#define CCR_OCACHE_INVALIDATE	CCR_CACHE_OCI
+#define CACHE_PHYSADDR_MASK	0x1ffffc00
 
 #endif /* __ASM_CPU_SH2A_CACHE_H */
include/asm-sh/cpu-sh2a/cacheflush.h +43 -1

44 lines not on this page · raw message

Signature · 2 lines
Yoshinori Sato
<[email protected]>
#2 lore raw
In reply to Yoshinori Sato
Quoted 5 lines · Yoshinori Sato

Sorry I forget flush_icache_region.
Update patch.

Signed-off-by Yoshinori Sato <[email protected]>

I've checked in a cleaned up version of this patch, thanks. Hopefully this will also fix the signal trampoline problems Yoshii-san was running in to on SH-2A due to the missing flush_icache_region().

author maintainer
#3 lore raw
In reply to Yoshinori Sato

At Mon, 4 Aug 2008 16:35:25 +0900,

Quoted 10 lines · Paul Mundt
Quoted 5 lines · Yoshinori Sato

Sorry I forget flush_icache_region.
Update patch.

Signed-off-by Yoshinori Sato <[email protected]>

I've checked in a cleaned up version of this patch, thanks. Hopefully this will also fix the signal trampoline problems Yoshii-san was running in to on SH-2A due to the missing flush_icache_region().

addrspace.h?
Sorry I missing commit.

I checked now. No missing files.

Signature · 2 lines
Yoshinori Sato
<[email protected]>