SMDK6400 support

nand_spl/nand_boot.c +3 -1

 	block = offs / CFG_NAND_BLOCK_SIZE;
+	blocks = (uboot_size + offs - ((block - 1) * CFG_NAND_BLOCK_SIZE) - 1) /
+		CFG_NAND_BLOCK_SIZE;
 	blockcopy_count = 0;
 
-	while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
+	while (blockcopy_count < blocks) {
 		if (!nand_is_bad_block(mtd, block)) {

Quoted 5 lines · Guennadi Liakhovetski

nand_spl/nand_boot.c +2 -0

 	block = offs / CFG_NAND_BLOCK_SIZE;
+	blocks = (uboot_size + offs - ((block - 1) * CFG_NAND_BLOCK_SIZE) - 1) /
+		CFG_NAND_BLOCK_SIZE;
 	blockcopy_count = 0;

nand_spl/nand_boot.c static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) · line 212

Quoted 13 lines

nand_spl/nand_boot.c +5 -2

-	while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
+	while (blockcopy_count < blocks) {
 		if (!nand_is_bad_block(mtd, block)) {
 			/*
 			 * Skip bad blocks
 			 */
 			for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
 				nand_read_page(mtd, block, page, dst);
-				dst += CFG_NAND_PAGE_SIZE;
+				/* Overwrite skipped pages */
+				if (read >= offs)
+					dst += CFG_NAND_PAGE_SIZE;
+				read += CFG_NAND_PAGE_SIZE;

This looks wrong if offs isn't within the first block.

I've pushed a fixed and simplified version to nand-flash/testing -- can you test it?

cpu/arm1176/s3c64xx/interrupts.c

Quoted 6 lines

cpu/arm1176/s3c64xx/interrupts.c new file +0 -0

new file mode 100644
index 0000000..4233e8c

You can remove anything from enable_interrupts() to do_irq() here. It's already in lib_arm/interrupts.c.

Based on the original S3C64XX port by Samsung for U-Boot 1.1.6.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---
 cpu/arm1176/Makefile                    |   50 ++
 cpu/arm1176/config.mk                   |   35 ++
 cpu/arm1176/cpu.c                       |  189 +++++++
 cpu/arm1176/s3c64xx/Makefile            |   48 ++
 cpu/arm1176/s3c64xx/config.mk           |   34 ++
 cpu/arm1176/s3c64xx/cpu_init.S          |  142 +++++
 cpu/arm1176/s3c64xx/interrupts.c        |  280 ++++++++++
 cpu/arm1176/s3c64xx/speed.c             |  140 +++++
 cpu/arm1176/start.S                     |  469 ++++++++++++++++
 include/asm-arm/arch-s3c64xx/hardware.h |   63 +++
 include/common.h                        |    3 +-
 include/s3c6400.h                       |  884 +++++++++++++++++++++++++++++++
 include/s3c64x0.h                       |   92 ++++

Is it intended to put the CPU specific header files directly into the include directory (s3c6400.h and s3c64x0.h)?

Quoted 2 lines · In message <[email protected]> you wrote:

Is it intended to put the CPU specific header files directly into the include directory (s3c6400.h and s3c64x0.h)?

That's what we've been doing so far:

	-> ls -l include/s3c*
	-rw-rw-r-- 1 wd wd 21763 Dec  9  2007 include/s3c2400.h
	-rw-rw-r-- 1 wd wd  7629 Dec  9  2007 include/s3c2410.h
	-rw-rw-r-- 1 wd wd 38129 Oct 13  2007 include/s3c24x0.h

Quoted 7 lines

That's what we've been doing so far:

	-> ls -l include/s3c*
	-rw-rw-r-- 1 wd wd 21763 Dec  9  2007 include/s3c2400.h
	-rw-rw-r-- 1 wd wd  7629 Dec  9  2007 include/s3c2410.h
	-rw-rw-r-- 1 wd wd 38129 Oct 13  2007 include/s3c24x0.h

Sorry, don't understand. So is it okay, that these files reside in the include directory or not?

Quoted 6 lines · In message <[email protected]> you wrote:

Quoted 6 lines

That's what we've been doing so far:

	-> ls -l include/s3c*
	-rw-rw-r-- 1 wd wd 21763 Dec  9  2007 include/s3c2400.h
	-rw-rw-r-- 1 wd wd  7629 Dec  9  2007 include/s3c2410.h
	-rw-rw-r-- 1 wd wd 38129 Oct 13  2007 include/s3c24x0.h

Quoted 2 lines

Sorry, don't understand. So is it okay, that these files reside in the include directory or not?

Unless you want to submit a clenaup patch for many existing processors, yes.

What is your suggestion instead?

Quoted 10 lines · Wolfgang Denk

Quoted 8 lines · In message <[email protected]> you wrote:

Quoted 6 lines

That's what we've been doing so far:

	-> ls -l include/s3c*
	-rw-rw-r-- 1 wd wd 21763 Dec  9  2007 include/s3c2400.h
	-rw-rw-r-- 1 wd wd  7629 Dec  9  2007 include/s3c2410.h
	-rw-rw-r-- 1 wd wd 38129 Oct 13  2007 include/s3c24x0.h

Sorry, don't understand. So is it okay, that these files reside in the include directory or not?

Quoted 4 lines

Unless you want to submit a clenaup patch for many existing processors, yes.

What is your suggestion instead?

It was just a question to read your opinion. Personally, I can live with it. I thought, CPU specific header files had to go to the include/asm-<arch>/arch-<cpu> directory.

cpu/arm1176/s3c64xx/interrupts.c +0 -0

Hi Guennadi,

Quoted 2 lines · Guennadi Liakhovetski

cpu/arm1176/s3c64xx/interrupts.c +0 -0

[snip]

Quoted 9 lines

cpu/arm1176/s3c64xx/interrupts.c +9 -0

+void udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = (usec + 9) / 10;
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)/* loop till event */

cpu/arm1176/s3c64xx/interrupts.c line 280

Quoted 2 lines

cpu/arm1176/s3c64xx/interrupts.c +2 -0

+		 /*NOP*/;
+}

I tried to follow the interrupt init function, but it's difficult. What is the least possible delay with the udelay function?
I remember that i.mx31 udelay cannot currently be below 30 microsseconds due to the low input clock. If someone uses udelay(1) in polling loops with timeout, the actual duration is much more longer than assumed.

Quoted 7 lines · Jens Gehrlein

Hi Guennadi,

Quoted 2 lines · Guennadi Liakhovetski

cpu/arm1176/s3c64xx/interrupts.c +0 -0

[snip]

Quoted 16 lines

cpu/arm1176/s3c64xx/interrupts.c line 280

Quoted 11 lines

cpu/arm1176/s3c64xx/interrupts.c +11 -0

+void udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = (usec + 9) / 10;
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)/* loop till event */
+		 /*NOP*/;
+}

I tried to follow the interrupt init function, but it's difficult. What is the least possible delay with the udelay function?
I remember that i.mx31 udelay cannot currently be below 30 microsseconds due to the low input clock. If someone uses udelay(1) in polling loops with timeout, the actual duration is much more longer than assumed.

Actually, the "/ 10" and this comment

/*
* We use the following scheme for the timer:
* Prescaler is hard fixed at 167, divider at 1/4.
* This gives at PCLK frequency 66MHz approx. 10us ticks
* The timer is set to wrap after 100s, at 66MHz this obviously
* happens after 10,000,000 ticks. A long variable can thus
* keep values up to 40,000s, i.e., 11 hours. This should be
* enough for most uses:-) Possible optimizations: select a
* binary-friendly frequency, e.g., 1ms / 128. Also calculate
* the prescaler automatically for other PCLK frequencies. */

shall make it clear, that the timer resolution is configured to 10us, which is also the minimum udelay. The timer could also do better, but then we get other disadvantages, e.g., shorter wrap-around time.

(quoted diff) +22 -0

+	write_p15_c1 (reg & ~C1_DC);
+}
+
+int dcache_status (void)
+{
+	return (read_p15_c1 () & C1_DC) != 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	/* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
+	/* mem barrier to sync things */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
+}
+	 * The timer is set to wrap after 100s, at 66MHz this obviously
+	 * happens after 10,000,000 ticks. A long variable can thus
+	 * keep values up to 40,000s, i.e., 11 hours. This should be
+	 * enough for most uses:-) Possible optimizations: select a
+	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
+	 * the prescaler automatically for other PCLK frequencies.

cpu/arm1176/s3c64xx/interrupts.c new file +31 -0

+	/* load value for 10 ms timeout */
+	lastdec = timers->TCNTB4 = timer_load_val;
+	/* auto load, manual update of Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
+		TCON_4_UPDATE;
+	/* auto load, start Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	ulong now = read_timer();
+
+	if (lastdec >= now) {
+		/* normal mode */
+#define MPLL 1
+#define EPLL 2
+
+/* ------------------------------------------------------------------------- */
+/*

cpu/arm1176/s3c64xx/speed.c new file +10 -0

+{
+	ulong fclk;
+
+	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
+	uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
+
+	/*
+	 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
+	 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
+	 */

cpu/arm1176/s3c64xx/speed.c new file +5 -0

+{
+	ulong fclk;
+	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
+	uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
+

cpu/arm1176/s3c64xx/speed.c new file +7 -0

+
+	if (OTHERS_REG & 0x80)
+		printf("(SYNC Mode) \n");
+	else
+		printf("(ASYNC Mode) \n");
+	return 0;
+}

cpu/arm1176/start.S new file +56 -0

new file mode 100644
index 0000000..00cc186
@@ -0,0 +1,469 @@
+/*
+ *  armboot - Startup Code for S3C6400/ARM1176 CPU-core
+ *
+ * Copyright (c) 2007	Samsung Electronics
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 2007-09-21 - Restructured codes by jsgood (jsgood.yang at samsung.com)
+ * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
+ * jsgood (jsgood.yang at samsung.com)
+ * Base codes by scsuh (sc.suh)
+ */
+
+#include <config.h>
+#include <version.h>
+#ifdef CONFIG_ENABLE_MMU
+#include <asm/proc/domain.h>
+#endif
+#include <s3c6400.h>
+
+#if !defined(CONFIG_ENABLE_MMU) && !defined(CFG_PHY_UBOOT_BASE)
+#define CFG_PHY_UBOOT_BASE	CFG_UBOOT_BASE
+#endif
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:

cpu/arm1176/start.S new file +19 -0

+	mrs	r0,cpsr
+	bic	r0,r0,#0x3f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */

include/common.h +0 -0

index 06ed278..ba87322 100644

+#define NFDATA (ELFIN_NAND_BASE+NFDATA_OFFSET)

+#define NFMECCDATA0 (ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)

+#define NFMECCDATA1 (ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)

+#define NFSECCDATA0 (ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)

+#define NFSBLK (ELFIN_NAND_BASE+NFSBLK_OFFSET)

+#define NFEBLK (ELFIN_NAND_BASE+NFEBLK_OFFSET)

+#define NFSTAT (ELFIN_NAND_BASE+NFSTAT_OFFSET)

+#define NFESTAT0 (ELFIN_NAND_BASE+NFESTAT0_OFFSET)

+#define NFESTAT1 (ELFIN_NAND_BASE+NFESTAT1_OFFSET)

+#define NFMECC0 (ELFIN_NAND_BASE+NFMECC0_OFFSET)

+#define NFMECC1 (ELFIN_NAND_BASE+NFMECC1_OFFSET)

+#define NFSECC (ELFIN_NAND_BASE+NFSECC_OFFSET)

+#define NFMLCBITPT (ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)

+#define NFDATA_REG __REG(ELFIN_NAND_BASE+NFDATA_OFFSET)

+#define NFDATA8_REG __REGb(ELFIN_NAND_BASE+NFDATA_OFFSET)

+#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)

+#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)

+#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)

+#define NFSBLK_REG __REG(ELFIN_NAND_BASE+NFSBLK_OFFSET)

+#define NFEBLK_REG __REG(ELFIN_NAND_BASE+NFEBLK_OFFSET)

+#define NFSTAT_REG __REG(ELFIN_NAND_BASE+NFSTAT_OFFSET)

+#define NFESTAT0_REG __REG(ELFIN_NAND_BASE+NFESTAT0_OFFSET)

+#define NFESTAT1_REG __REG(ELFIN_NAND_BASE+NFESTAT1_OFFSET)

+#define NFMECC0_REG __REG(ELFIN_NAND_BASE+NFMECC0_OFFSET)

+#define NFMECC1_REG __REG(ELFIN_NAND_BASE+NFMECC1_OFFSET)

+#define NFSECC_REG __REG(ELFIN_NAND_BASE+NFSECC_OFFSET)

+#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)

+

+#define NFCONF_REG __REG(ELFIN_NAND_BASE+NFCONF_OFFSET)

include/s3c6400.h new file +4 -0

+#define DMC_DDR_MEM_CASLAT	3
+/* 6   Set Cas Latency to 3 */
+#define DMC_DDR_CAS_LATENCY	(DDR_CASL << 1)
+/* Min 0.75 ~ 1.25 */

include/s3c64x0.h new file +33 -0

@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2003
+ * David M??ller ELSOFT AG Switzerland. d.mueller at elsoft.ch
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME	    : S3C64XX.h
+ * Version  : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C64XX SoC
+ ************************************************/
+

include/s3c64x0.h new file +21 -0

+
+/* UART (see manual chapter 11) */
+typedef struct {
+	S3C64XX_REG32	ULCON;
+	S3C64XX_REG32	UCON;
+	S3C64XX_REG32	UFCON;
+	S3C64XX_REG32	UMCON;
+	S3C64XX_REG32	UTRSTAT;
+	S3C64XX_REG32	UERSTAT;
+	S3C64XX_REG32	UFSTAT;
+	S3C64XX_REG32	UMSTAT;
+#ifdef __BIG_ENDIAN
+	S3C64XX_REG8	res1[3];
+	S3C64XX_REG8	UTXH;
+	S3C64XX_REG8	res2[3];
+	S3C64XX_REG8	URXH;
+#else /* Little Endian */
+	S3C64XX_REG8	UTXH;
+	S3C64XX_REG8	res1[3];
+	S3C64XX_REG8	URXH;
+	S3C64XX_REG8	res2[3];

cpu/arm1176/s3c64xx/interrupts.c line 193

Quoted 7 lines

cpu/arm1176/s3c64xx/interrupts.c new file +6 -0

+		/*
+		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 and
+		 * prescaler = 16. Should be 10390 @33.25MHz and 15625 @ 50 MHz
+		 */
+		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
+		/*printf("Calculated %lu timer_load_val\n", timer_load_val);*/

please remove if not need

cpu/arm1176/s3c64xx/interrupts.c line 196

Quoted 3 lines

cpu/arm1176/s3c64xx/interrupts.c new file +3 -0

+		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
+	}
+

please add some empty line to be more readable

Quoted 1 line

+#define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET)

                 ^^^^^^^^^^^

please remove whitesapce

Quoted 8 lines · In message <[email protected]> you wrote:

cpu/arm1176/s3c64xx/interrupts.c line 193

Quoted 7 lines

cpu/arm1176/s3c64xx/interrupts.c new file +6 -0

+		/*
+		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 and
+		 * prescaler = 16. Should be 10390 @33.25MHz and 15625 @ 50 MHz
+		 */
+		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
+		/*printf("Calculated %lu timer_load_val\n", timer_load_val);*/

please remove if not need

Or even better convert it into a debug() call so it can be enabled again for debugging purposes.

Quoted 4 lines

cpu/arm1176/s3c64xx/interrupts.c line 196

Quoted 3 lines

cpu/arm1176/s3c64xx/interrupts.c new file +3 -0

+		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
+	}
+

please add some empty line to be more readable

No. One empty line os enough here.

cpu/arm1176/s3c64xx/interrupts.c new file +8 -0

+     /* load value for 10 ms timeout */
+     lastdec = timers->TCNTB4 = timer_load_val;
+     /* auto load, manual update of Timer 4 */
+     timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
+             TCON_4_UPDATE;
+     /* auto load, start Timer 4 */
+     timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
+     timestamp = 0;

Quoted 3 lines

Quoted 1 line

+#define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET)

                 ^^^^^^^^^^^

please remove whitesapce

Not remove, but use TABs vor vertical alignment.

cpu/arm1176/cpu.c line 174

Quoted 9 lines

cpu/arm1176/cpu.c new file +9 -0

+
+void dcache_disable (void)
+{
+	ulong reg;
+
+	reg = read_p15_c1 ();
+	cp_delay ();
+	reg &= ~C1_DC;
+	write_p15_c1 (reg);

why not as the other implementation?

cpu/arm1176/s3c64xx/interrupts.c line 193

Quoted 1 line

cpu/arm1176/s3c64xx/interrupts.c new file +1 -0

+		/*printf("Calculated %lu timer_load_val\n", timer_load_val);*/

please remove if not need

please add some empty line to be more readable

cpu/arm1176/s3c64xx/interrupts.c line 204

Quoted 8 lines

cpu/arm1176/s3c64xx/interrupts.c new file +8 -0

+	/* load value for 10 ms timeout */
+	lastdec = timers->TCNTB4 = timer_load_val;
+	/* auto load, manual update of Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
+		TCON_4_UPDATE;
+	/* auto load, start Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
+	timestamp = 0;

Quoted 1 line

+static ulong get_PLLCLK(int pllreg)

please not uppercase

cpu/arm1176/s3c64xx/speed.c line 62

Quoted 8 lines

cpu/arm1176/s3c64xx/speed.c new file +8 -0

+	if (pllreg == APLL)
+		r = APLL_CON_REG;
+	else if (pllreg == MPLL)
+		r = MPLL_CON_REG;
+	else if (pllreg == EPLL)
+		r = EPLL_CON0_REG;
+	else
+		hang();

please move to switch implementation

cpu/arm1176/s3c64xx/speed.c line 133

Quoted 4 lines

cpu/arm1176/s3c64xx/speed.c new file +4 -0

+	printf("\nCPU:     S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
+	printf("         Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
+	       get_FCLK() / 1000000, get_HCLK() / 1000000,
+	       get_PCLK() / 1000000);

maybe a macro like HZ_TO_MHZ(x) could be helpfull to avoid typo

please add space between parameter

cpu/arm1176/start.S line 136

Quoted 4 lines

cpu/arm1176/start.S new file +4 -0

+	mrs	r0,cpsr
+	bic	r0,r0,#0x3f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0

Quoted 4 lines

include/common.h +0 -0

index 06ed278..ba87322 100644

include/common.h int prt_mpc8220_clks (void); · line 495

Quoted 7 lines

include/common.h +2 -1

@@ -491,7 +491,8 @@ int	prt_mpc8220_clks (void);
 ulong	get_OPB_freq (void);
 ulong	get_PCI_freq (void);
 #endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X)
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
+	defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400)

Is it possible to have a better and simpler ifdef?

include/common.h int prt_mpc8220_clks (void); · line 498

Quoted 3 lines

include/common.h +0 -0

 void	s3c2410_irq(void);
 #define ARM920_IRQ_CALLBACK s3c2410_irq
 ulong	get_FCLK (void);

Quoted 1 line

+#define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET)

                 ^^^^^^^^^^^

please remove whitesapce

btw on all macro please add space beetwen operator like

Quoted 1 line

+#define NFCONF_REG __REG(ELFIN_NAND_BASE+NFCONF_OFFSET)

to
#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)

Quoted 1 line

+#define Startup_AMDIV 400

for macro I'll prefer upercase

include/common.h

Quoted 3 lines

include/common.h +3 -0

+#define Startup_MDIV		400
+#define Startup_PDIV		6
+#define Startup_SDIV		1

include/common.h

Quoted 3 lines

include/common.h +3 -0

+typedef vu_char		S3C64XX_REG8;
+typedef vu_short	S3C64XX_REG16;
+typedef vu_long		S3C64XX_REG32;

I'll prefer you use the type directly

Quoted 1 line

+} /*__attribute__((__packed__))*/ s3c64xx_uart;

why do you remove the packed attribute?

Notice: USB on S3C6400 currently works _only_ with switched off MMU. One could try to enable the MMU, but map addresses 1-to-1, and disable data cache, then it should work too and we could still profit from instruction cache.

Signed-off-by Guennadi Liakhovetski <[email protected]>

Quoted 4 lines · Guennadi Liakhovetski

Notice: USB on S3C6400 currently works _only_ with switched off MMU. One could try to enable the MMU, but map addresses 1-to-1, and disable data cache, then it should work too and we could still profit from instruction cache.

Quoted 1 line

Signed-off-by Guennadi Liakhovetski <[email protected]>

Acked-by Markus Klotzbuecher <[email protected]>

I can't apply this to the USB custodian repository without the rest of the patchset being applied. I'm also fine if the ARM custodian picks this one up.

Quoted 3 lines · Markus Klotzb?cher

I can't apply this to the USB custodian repository without the rest of the patchset being applied. I'm also fine if the ARM custodian picks this one up.

I'll do.

drivers/serial/s3c64xx.c line 76

Quoted 4 lines

drivers/serial/s3c64xx.c new file +4 -0

+	u32 reg;
+	u32 pclk_ratio = get_PCLK() / gd->baudrate;
+	int i;
+

IMHO it's still obscur

drivers/serial/s3c64xx.c line 80

Quoted 4 lines

drivers/serial/s3c64xx.c new file +4 -0

+	/* PCLK / (16 * baudrate) - 1 */
+	reg = pclk_ratio / 16 - 1;
+	/* i = pclk_ratio % 16 */
+	i = pclk_ratio - (reg + 1) * 16;

Quoted 8 lines

drivers/serial/s3c64xx.c line 76

Quoted 5 lines

drivers/serial/s3c64xx.c new file +4 -0

+	u32 reg;
+	u32 pclk_ratio = get_PCLK() / gd->baudrate;
+	int i;
+

IMHO it's still obscur

drivers/serial/s3c64xx.c line 78

Quoted 2 lines

drivers/serial/s3c64xx.c new file +2 -0

+	/* PCLK / (16 * baudrate) - 1 */
+	reg = pclk_ratio / 16 - 1;

Quoted 2 lines

drivers/serial/s3c64xx.c line 80

Quoted 2 lines

drivers/serial/s3c64xx.c new file +2 -0

+	/* i = pclk_ratio % 16 */
+	i = pclk_ratio - (reg + 1) * 16;

Sorry, I don't understand how this can be made clearer yet. If you have any specific ideas, please let me know now, before v7 appears, because I would really like to make it final.

Dear Guennadi Liakhovetski,

Quoted 8 lines · In message <[email protected]> you wrote:

Quoted 8 lines

drivers/serial/s3c64xx.c line 76

Quoted 5 lines

drivers/serial/s3c64xx.c new file +4 -0

+	u32 reg;
+	u32 pclk_ratio = get_PCLK() / gd->baudrate;
+	int i;
+

IMHO it's still obscur

drivers/serial/s3c64xx.c line 78

Quoted 2 lines

drivers/serial/s3c64xx.c new file +2 -0

+	/* PCLK / (16 * baudrate) - 1 */
+	reg = pclk_ratio / 16 - 1;

I don't see any baudrate in this calculation. From the comment I would expect to see

	reg = pclk_ratio / (16 * gd->baudrate) - 1;

or similar. For the reader the comment is misleading as it is difficult to figure out that "PCLK" and "pclk_ratio" are not the same thing.

Quoted 2 lines

Quoted 2 lines

drivers/serial/s3c64xx.c line 80

Quoted 2 lines

drivers/serial/s3c64xx.c new file +2 -0

+	/* i = pclk_ratio % 16 */
+	i = pclk_ratio - (reg + 1) * 16;

I don't see any % operation in this calculation. From the comment I would expect to see

	i = pclk_ratio % 16;

or similar. Either the comment or the code or both are wrong.

Quoted 3 lines

Sorry, I don't understand how this can be made clearer yet. If you have any specific ideas, please let me know now, before v7 appears, because I would really like to make it final.

Well, maybe the code and the comments should be in sync. Actually, if the comment just says the same as the code, it is redundant and should be omitted. If the comment tries to describe what the code implements in a different way that should be made clear, too.

Probably it doesn't make much sense to try to factor out common expressions when it makes thew code more difficult to read - the compiler is pretty clever about such things, too.

Ok, would this be better

	u32 reg;
	u32 pclk = get_PCLK();
	u32 baudrate = gd->baudrate;
	int i;

	reg = pclk / baudrate / 16 - 1;
	i = (pclk / baudrate) % 16;

This way the compiler does optimize it to only one division, and the operations say what they do, and there doesn't seem to be any need for comment left. Still, the code produced by this is 1 asm instruction longer than my original code:-)

Quoted 8 lines · In message <[email protected]> you wrote:

Ok, would this be better

	u32 reg;
	u32 pclk = get_PCLK();
	u32 baudrate = gd->baudrate;
	int i;

Quoted 2 lines

	reg = pclk / baudrate / 16 - 1;
	i = (pclk / baudrate) % 16;

Is "reg" still used anywhere else?

Quoted 4 lines

This way the compiler does optimize it to only one division, and the operations say what they do, and there doesn't seem to be any need for comment left. Still, the code produced by this is 1 asm instruction longer than my original code:-)

Is the generated code equivalent? This smells like a subtle bug...

SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl driver for it too. The board can also boot from the NOR flash, but due to hardware limitations it can only address 64KiB on it, which is not enough for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6.

Signed-off-by Guennadi Liakhovetski <[email protected]>

---

Changes since v5: adjust the configuration to more precisely desribe NAND ECC layout.

 MAKEALL                                    |    1 +
 Makefile                                   |   17 ++

 board/samsung/smdk6400/Makefile            |   54 +++++
 board/samsung/smdk6400/config.mk           |   30 +++
 board/samsung/smdk6400/lowlevel_init.S     |  316 ++++++++++++++++++++++++++++
 board/samsung/smdk6400/smdk6400.c          |  130 ++++++++++++
 board/samsung/smdk6400/u-boot-nand.lds     |   62 ++++++
 include/configs/smdk6400.h                 |  306 +++++++++++++++++++++++++++
 nand_spl/board/samsung/smdk6400/Makefile   |  106 ++++++++++
 nand_spl/board/samsung/smdk6400/config.mk  |   40 ++++
 nand_spl/board/samsung/smdk6400/u-boot.lds |   61 ++++++
 11 files changed, 1123 insertions(+), 0 deletions(-)
 create mode 100644 board/samsung/smdk6400/Makefile
 create mode 100644 board/samsung/smdk6400/config.mk
 create mode 100644 board/samsung/smdk6400/lowlevel_init.S
 create mode 100644 board/samsung/smdk6400/smdk6400.c
 create mode 100644 board/samsung/smdk6400/u-boot-nand.lds
 create mode 100644 include/configs/smdk6400.h
 create mode 100644 nand_spl/board/samsung/smdk6400/Makefile
 create mode 100644 nand_spl/board/samsung/smdk6400/config.mk
 create mode 100644 nand_spl/board/samsung/smdk6400/u-boot.lds

board/samsung/smdk6400/Makefile new file +10 -0

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk

board/samsung/smdk6400/config.mk new file +27 -0

new file mode 100644
index 0000000..298d387
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <[email protected]>
+# David Mueller, ELSOFT AG, <[email protected]>
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <[email protected]>
+#
+# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+
+# On SMDK6400 we use the 64 MB SDRAM bank at
+#
+# 0x50000000 to 0x58000000
+#
+# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
+#
+# we load ourselves to 0x57e00000 without MMU
+# with MMU, load address is changed to 0xc7e00000
+#
+# download area is 0x5000c000
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef CONFIG_NAND_SPL
+TEXT_BASE = $(RAM_TEXT)

index 0000000..77fd2c8

board/samsung/smdk6400/smdk6400.c new file +18 -0

@@ -0,0 +1,130 @@
+/*
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+			  "bne 1b"
+			  : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
+		print_size(nand_dev_desc[0].totlen, "\n");
+}
+#endif

board/samsung/smdk6400/smdk6400.c new file +1 -0

+}

include/configs/smdk6400.h new file +12 -0

new file mode 100644
index 0000000..1bc8996
@@ -0,0 +1,306 @@
+/*
+#define CONFIG_SMDK6400		1	/* on a SAMSUNG SMDK6400 Board  */
+
+#define CFG_SDRAM_BASE	0x50000000
+
+/* input clock of PLL: SMDK6400 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+

include/configs/smdk6400.h new file +7 -0

+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*

include/configs/smdk6400.h new file +22 -0

+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#define CONFIG_CMDLINE_EDITING
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NAND
+#if defined(CONFIG_BOOT_ONENAND)

include/configs/smdk6400.h new file +33 -0

+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use	 */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory	      */
+#define CFG_PROMPT		"SMDK6400 # "	/* Monitor Command Prompt     */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size    */
+#define CFG_PBSIZE		384		/* Print Buffer Size          */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* memtest works on	      */
+#define CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
+
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* default load address	*/
+
+#define CFG_HZ			1000
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	0x40000		/* regular stack 256KB */
+
+/**********************************
+ Support Clock Settings

include/configs/smdk6400.h new file +8 -0

+
+/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CFG_SDRAM_BASE	/* SDRAM Bank #1	*/
+#define CONFIG_BOOT_MOVINAND
+#define CONFIG_BOOT_ONENAND
+*/
+

nand_spl/board/samsung/smdk6400/Makefile new file +50 -0

new file mode 100644
index 0000000..ae9eb2a
@@ -0,0 +1,106 @@
+#
+# (C) Copyright 2006-2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <[email protected]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CONFIG_NAND_SPL	= y
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o cpu_init.o lowlevel_init.o
+COBJS	= nand_boot.o nand_ecc.o s3c64xx.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+