ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC 440SP/SPe, PPC405EX and PPC 460EX/GT

Resending the patch since it was not copied to Stefan. Stefan, please ignore the previous post.

Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors Add register bit definitions for Memory Queue Configuration registers

---
 cpu/ppc4xx/44x_spd_ddr2.c      |   27 ++++++++++++++++---
 cpu/ppc4xx/cpu_init.c          |   16 ++++++++++-
 include/asm-ppc/ppc4xx-sdram.h |   48 ++++++++++++++++++++++-----------
 include/ppc440.h               |   47 ---------------------------------
 include/ppc4xx.h               |   56 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 126 insertions(+), 68 deletions(-)

index 1c36324..0431754 100644
@@ -2172,6 +2172,11 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	unsigned long i;
 	unsigned long bank_0_populated = 0;
 	phys_size_t total_size = 0;
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
+	unsigned long val;
+#endif
 
 	/*------------------------------------------------------------------
 	 * Reset the rank_base_address.

@@ -2249,17 +2254,31 @@ static void program_memory_queue(unsigned long *dimm_populated,
 		}
 	}
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
+
 	/*
-	 * Enable high bandwidth access on 460EX/GT.
-	 * This should/could probably be done on other
-	 * PPC's too, like 440SPe.
+	 * Enable high bandwidth access 
 	 * This is currently not used, but with this setup
 	 * it is possible to use it later on in e.g. the Linux
 	 * EMAC driver for performance gain.
 	 */
 	mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
 	mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
+
+	/*
+	 * Set optimal value for Memory Queue HB/LL Configuration registers
+	 */
+
+	val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
+	mtdcr(SDRAM_CONF1HB, val); 
+
+	val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+	mtdcr(SDRAM_CONF1LL, val); 
+
+	val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
+	mtdcr(SDRAM_CONFPATHB, val);
 #endif
 }
 

index e2d0402..c7c429e 100644
@@ -138,7 +138,9 @@ void reconfigure_pll(u32 new_cpu_freq)
 void
 cpu_init_f (void)
 {
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX)   || \
+    defined(CONFIG_460GT) || defined(CONFIG_460SX)
 	u32 val;
 #endif
 

@@ -301,6 +303,18 @@ cpu_init_f (void)
 	val |= 0x400;
 	mtsdr(SDR0_USB2HOST_CFG, val);
 #endif /* CONFIG_460EX */
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
+    defined(CONFIG_405EX) || defined(CONFIG_460SX)
+	/*
+	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read 
+	 */
+	val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	mtdcr(plb0_acr, val);
+	val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	mtdcr(plb1_acr, val);
+#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }
 
 /*

1.5.5

Applied to u-boot-ppc4xx. Thanks.

Still a few comments though (for the next time):

- Please don't add too long lines to the commit text. Since tools like git-log will indent the commit text, please restrict this text to something like 70 chars per line.
- The line "Resending the patch..." above needs to go below the "---" line. This way it will not appear in the commit text after applying.
- Don't indent the commit text.
- You still introduced a few too long lines in the code (I already commented about this). I'll clean this up with a follow up patch.
- Your patch introduces trailing white spaces. I fixed this. Please take extra care next time. I suggest running checkpatch.pl or applying the patch to your local repo via git-am. This will give you some warnings/errors.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

Hi Stefan,
Thanks for your comments. I did not know about the commit text conventions. I will be more careful in future.

Could you please let me know which lines were the problem.
I would like to know the problem so that it does not get repeated in future.

Best regards,
Prodyut Hazarika

======================
Staff S/W Engineer
AMCC
======================

Hi Prodyut,

Good. Thanks.

Sure:

[stefan at kubuntu linus (master)]$ ./scripts/checkpatch.pl ~/git/u-boot/u-boot-ppc4xx/patches_amcc/\[PATCH\]\ ppc4xx\:\ Optimize\ PLB4\
Arbiter\ and\ Memory\ Queue\ settings\ for\ PPC\ 440SP_SPe\,\ PPC405EX\ and\
PPC\ 460EX_GT.mbox
ERROR: trailing whitespace
#101: FILE: cpu/ppc4xx/44x_spd_ddr2.c:2262:
+^I * Enable high bandwidth access $

WARNING: line over 80 characters
#113: FILE: cpu/ppc4xx/44x_spd_ddr2.c:2274:
+ val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);

ERROR: trailing whitespace
#114: FILE: cpu/ppc4xx/44x_spd_ddr2.c:2275:
+^Imtdcr(SDRAM_CONF1HB, val); $

WARNING: line over 80 characters
#116: FILE: cpu/ppc4xx/44x_spd_ddr2.c:2277:
+ val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);

ERROR: trailing whitespace
#117: FILE: cpu/ppc4xx/44x_spd_ddr2.c:2278:
+^Imtdcr(SDRAM_CONF1LL, val); $

Again, you can also apply the patch (email) to your repo with git-am and should see some warnings there.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================