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cpu_is_omap15xx() doesn't get set for OMAP310

DISCUSSION Russell King - ARM Linux 2 participants 4 messages Sep 4, 2008 – Sep 10, 2008

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Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP1 support +2 more subsystems
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Russell King - ARM Linux

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#0 lore raw

While trying out some of the changes in qemu (which emulates an OMAP310) I found that cpu_is_omap15xx() returns false.

The comment says:

* Macros to group OMAP into cpu classes.
* These can be used in most places.
* cpu_is_omap7xx(): True for OMAP730
* cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310

and cpu_is_omap15xx() is defined as:

# define cpu_is_omap15xx() is_omap15xx()

#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff)

#define IS_OMAP_CLASS(class, id)                        \
static inline int is_omap ##class (void)                \
{                                                       \
        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \

}

IS_OMAP_CLASS(15xx, 0x15)

So, it's looking for the top byte of system_rev to be 0x15. However, the ID table in arch/arm/mach-omap1/id.c contains:

{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},

so the top byte contains 0x03. Moreover, it goes on to say:

        /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
        cpu_type = system_rev >> 24;
        switch (cpu_type) {
        case 0x03:
                system_rev |= 0x15;
                break;

So, if this code is supposed to be setting the cpu class, it's setting it in the low byte.

It looks to me like the omap1 ID code is out of step with the omap2 ID code, or omap310 ID support is broken.

maintainer
#1 lore raw
Quoted 39 lines · Russell King - ARM Linux

While trying out some of the changes in qemu (which emulates an OMAP310) I found that cpu_is_omap15xx() returns false.

The comment says:

* Macros to group OMAP into cpu classes.
* These can be used in most places.
* cpu_is_omap7xx(): True for OMAP730
* cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310

and cpu_is_omap15xx() is defined as:

# define cpu_is_omap15xx() is_omap15xx()

#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff)

#define IS_OMAP_CLASS(class, id)                        \
static inline int is_omap ##class (void)                \
{                                                       \
        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \

}

IS_OMAP_CLASS(15xx, 0x15)

So, it's looking for the top byte of system_rev to be 0x15. However, the ID table in arch/arm/mach-omap1/id.c contains:

{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},

so the top byte contains 0x03. Moreover, it goes on to say:

        /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
        cpu_type = system_rev >> 24;
        switch (cpu_type) {
        case 0x03:
                system_rev |= 0x15;
                break;
Quoted 5 lines

So, if this code is supposed to be setting the cpu class, it's setting it in the low byte.

It looks to me like the omap1 ID code is out of step with the omap2 ID code, or omap310 ID support is broken.

Looks like adding omap2 detection has broken this by stuffing in other data there and tweaking GET_OMAP_CLASS macro. And again we have something that's mostly working only by accident.

Probably the right fix would be to keep the original low byte as the cpu class, fix the GET_OMAP_CLASS macro, clean-up mach-omap2/id.c and set up static u32 system_mode to indicate HS or GP omap (High Security vs General Purpose). That would still leave one byte in system_rev to indicate processor revision (ES1, ES2.0).

The ugly short term fix would be to define IS_OMAP_CLASS in a different way for omap1 and omap2. Anyways, I can fix it properly unless you're already patching it.

Tony

author
#2 lore raw
Quoted 3 lines · Tony Lindgren

The ugly short term fix would be to define IS_OMAP_CLASS in a different way for omap1 and omap2. Anyways, I can fix it properly unless you're already patching it.

Haven't pushed any fix for it; my temporary workaround for it was quite hacky to the extent of breaking omap2.

maintainer
#3 lore raw
Quoted 7 lines · Russell King - ARM Linux
Quoted 3 lines · Tony Lindgren

The ugly short term fix would be to define IS_OMAP_CLASS in a different way for omap1 and omap2. Anyways, I can fix it properly unless you're already patching it.

Haven't pushed any fix for it; my temporary workaround for it was quite hacky to the extent of breaking omap2.

Here's a fix (mostly untested) to look. I ended up removing bunch of stuff from mach-omap2/id.c.. Ugly patch.. I guess it should be broken down a bit.

Currently it does not apply to the mainline kernel, as it depends on some patches from the pending omap2-upstream series.

Anyways, I'll post some better patches tomorrow and try to work out something for mainline kernel.

Tony

Quoted 1 line

From b776efe3e4d77547d9d28c557160860b61a89572 Mon Sep 17 00:00:00 2001

From: Tony Lindgren <[email protected]>
Date: Tue, 9 Sep 2008 20:27:55 -0700
Subject: [PATCH] ARM: OMAP: Fix cpu detection

Fix cpu detection

Signed-off-by Tony Lindgren <[email protected]>
arch/arm/mach-omap1/id.c +0 -3
index da13c3e..4e79f3e 100644
@@ -179,9 +179,6 @@ void __init omap_check_revision(void)
 	case 0x17:
 		system_rev |= 0x16;
 		break;
-	case 0x24:
-		system_rev |= 0x24;
-		break;
 	default:
 		printk("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
 	}
arch/arm/mach-omap2/board-3430sdp-flash.c +1 -1
index 945a2ae..835c8f6 100644
@@ -148,7 +148,7 @@ void __init sdp3430_flash_init(void)
 	u8		onenandcs = GPMC_CS_NUM + 1;
 
 	/* Configure start address and size of NOR device */
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+	if (system_rev > OMAP3430_REV_ES1_0) {
 		sdp_nor_resource.start	= FLASH_BASE_SDPV2;
 		sdp_nor_resource.end	= FLASH_BASE_SDPV2
 						+ FLASH_SIZE_SDPV2 - 1;
arch/arm/mach-omap2/board-3430sdp.c +6 -5
index d27158e..8823ee2 100644
@@ -135,7 +135,8 @@ static int twl4030_rtc_init(void)
 	int ret = 0;
 
 	/* 3430ES2.0 doesn't have msecure/gpio-22 line connected to T2 */
-	if (is_device_type_gp() && is_sil_rev_less_than(OMAP3430_REV_ES2_0)) {
+	if (omap_type() == OMAP2_DEVICE_TYPE_GP &&
+			system_rev < OMAP3430_REV_ES2_0) {
 		u32 msecure_pad_config_reg = omap_ctrl_base_get() + 0xA3C;
 		int mux_mask = 0x04;
 		u16 tmp;

@@ -166,8 +167,8 @@ out:
 
 static void twl4030_rtc_exit(void)
 {
-	if (is_device_type_gp() &&
-			is_sil_rev_less_than(OMAP3430_REV_ES2_0)) {
+	if (omap_type() == OMAP2_DEVICE_TYPE_GP &&
+			system_rev < OMAP3430_REV_ES2_0) {
 		omap_free_gpio(TWL4030_MSECURE_GPIO);
 	}
 }

@@ -298,7 +299,7 @@ static inline void __init sdp3430_init_smc91x(void)
 	sdp3430_smc91x_resources[0].end   = cs_mem_base + 0xf;
 	udelay(100);
 
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
+	if (system_rev > OMAP3430_REV_ES1_0)
 		eth_gpio = OMAP34XX_ETHR_GPIO_IRQ_SDPV2;
 	else
 		eth_gpio = OMAP34XX_ETHR_GPIO_IRQ_SDPV1;

@@ -357,7 +358,7 @@ static void __init omap_3430sdp_init(void)
 	platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
 	omap_board_config = sdp3430_config;
 	omap_board_config_size = ARRAY_SIZE(sdp3430_config);
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
+	if (system_rev > OMAP3430_REV_ES1_0)
 		ts_gpio = OMAP34XX_TS_GPIO_IRQ_SDPV2;
 	else
 		ts_gpio = OMAP34XX_TS_GPIO_IRQ_SDPV1;
arch/arm/mach-omap2/board-ldp.c +2 -1
index 987f860..ab714a3 100644
@@ -55,7 +55,8 @@ static int twl4030_rtc_init(void)
 	int ret = 0;
 
 	/* 3430ES2.0 doesn't have msecure/gpio-22 line connected to T2 */
-	if (is_device_type_gp() && is_sil_rev_less_than(OMAP3430_REV_ES2_0)) {
+	if (omap_device_type() == OMAP2_DEVICE_TYPE_GP &&
+			system_rev < OMAP3430_REV_ES2_0) {
 		u32 msecure_pad_config_reg = omap_ctrl_base_get() + 0xA3C;
 		int mux_mask = 0x04;
 		u16 tmp;
arch/arm/mach-omap2/clock.c +3 -3
index 88c8ef4..4713918 100644
@@ -261,7 +261,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 		    (reg & 0x0f) == 0 &&
 		    clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
 
-			if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+			if (system_rev == OMAP3430_REV_ES1_0)
 				return;
 
 			idlest_bit = OMAP3430ES2_ST_SSI_IDLE;

@@ -271,7 +271,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 		if (prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0)) {
 
 			/* 3430ES1 DSS has no target idlest bits */
-			if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+			if (system_rev == OMAP3430_REV_ES1_0)
 				return;
 
 			/*

@@ -285,7 +285,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
 		}
 
 		/* USBHOST */
-		if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&
+		if (system_rev > OMAP3430_REV_ES1_0 &&
 		    prcm_mod == OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, 0)) {
 
 			/*
arch/arm/mach-omap2/clock34xx.c +2 -2
index 21492c2..152d095 100644
@@ -336,7 +336,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
 	 * on DPLL4.
 	 */
-	if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
+	if (system_rev == OMAP3430_REV_ES1_0 &&
 	    !strcmp("dpll4_ck", clk->name)) {
 		printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
 		       "silicon 'Limitation 2.5' on 3430ES1.\n");

@@ -682,7 +682,7 @@ int __init omap2_clk_init(void)
 		 * Update this if there are further clock changes between ES2
 		 * and production parts
 		 */
-		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
+		if (system_rev == OMAP3430_REV_ES1_0) {
 			/* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
 			cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
 		} else {
arch/arm/mach-omap2/id.c +130 -183

371 lines not on this page · raw message

arch/arm/mach-omap2/pm34xx.c +5 -5
index a16eb33..688be12 100644
@@ -109,7 +109,7 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 		cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
 	}
 
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+	if (system_rev > OMAP3430_REV_ES1_0) {
 		/* USBHOST */
 		wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
 		if (wkst) {

@@ -187,7 +187,7 @@ static int omap3_fclks_active(void)
 
 	fck_core1 = cm_read_mod_reg(CORE_MOD,
 				    CM_FCLKEN1);
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+	if (system_rev > OMAP3430_REV_ES1_0) {
 		fck_core3 = cm_read_mod_reg(CORE_MOD,
 					    OMAP3430ES2_CM_FCLKEN3);
 		fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,

@@ -377,7 +377,7 @@ static void __init prcm_setup_regs(void)
 	prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 	prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 	prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+	if (system_rev > OMAP3430_REV_ES1_0) {
 		prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 		prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 	} else

@@ -427,7 +427,7 @@ static void __init prcm_setup_regs(void)
 		OMAP3430_AUTO_DES1,
 		CORE_MOD, CM_AUTOIDLE2);
 
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+	if (system_rev > OMAP3430_REV_ES1_0) {
 		cm_write_mod_reg(
 			OMAP3430ES2_AUTO_USBTLL,
 			CORE_MOD, CM_AUTOIDLE3);

@@ -474,7 +474,7 @@ static void __init prcm_setup_regs(void)
 		OMAP3430_PER_MOD,
 		CM_AUTOIDLE);
 
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+	if (system_rev > OMAP3430_REV_ES1_0) {
 		cm_write_mod_reg(
 			OMAP3430ES2_AUTO_USBHOST,
 			OMAP3430ES2_USBHOST_MOD,
arch/arm/mach-omap2/smartreflex.c +1 -1
index ffd49d1..e54c0fb 100644
@@ -766,7 +766,7 @@ static int __init omap3_sr_init(void)
 	int ret = 0;
 	u8 RdReg;
 
-	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+	if (system_rev > OMAP3430_REV_ES1_0) {
 		current_vdd1_opp = PRCM_VDD1_OPP3;
 		current_vdd2_opp = PRCM_VDD2_OPP3;
 	} else {
arch/arm/plat-omap/include/mach/cpu.h +26 -51

114 lines not on this page · raw message