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OMAP2/3 clock: encode prcm_mod for each struct clk

PATCH Superseded Paul Walmsley 2 participants 5 messages Sep 16, 2008 – Sep 17, 2008

Subsystems (4)
Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP clock framework support

v1 of 2 Superseded Latest is v2 →

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Paul Walmsley

author maintainer
#0 lore raw

cover OMAP2/3 clock: encode prcm_mod for each struct clk

Add a new field, prcm_mod, to the OMAP2/3 struct clk. Major effects of this change include:

- the removal of the register rewriting code for OMAP2xxx clock framework,

- the resolution of gcc and sparse warnings for the clock code,

- the removal of many __force void __iomem * casts in the clock tree,

- and the reduction of the register address field size in struct clk by two bytes per clk.

This series applies on top of the "OMAP2/3 clock: revise DPLL bypass handling in clock tree" series. This series is a prerequisite for the IDLEST handling revision patches, following shortly.

Boot-tested on 3430SDP and 2430SDP.

---

text data bss dec hex filename

3457748  160200  106600 3724548  38d504 vmlinux.3430sdp.orig
3457832  159768  106600 3724200  38d3a8 vmlinux.3430sdp
 arch/arm/mach-omap2/clock.c             |  223 +++++-----
 arch/arm/mach-omap2/clock.h             |    3 
 arch/arm/mach-omap2/clock24xx.c         |   58 ---
 arch/arm/mach-omap2/clock24xx.h         |  458 +++++++++++++--------
 arch/arm/mach-omap2/clock34xx.c         |   27 +
 arch/arm/mach-omap2/clock34xx.h         |  672 ++++++++++++++++++++-----------
 arch/arm/mach-omap2/cm.h                |    3 
 arch/arm/plat-omap/common.c             |    1 
 arch/arm/plat-omap/include/mach/clock.h |   26 +
 9 files changed, 874 insertions(+), 597 deletions(-)
author maintainer
#1 lore raw

PATCH 1/3 OMAP3 clock: split mcbspX_src_fck from mcbspX_fck

McBSP clock source control registers are located in the System Control Module, not the PRCM. However, the clock enable/disable registers are in the CM. Since the following patches require all registers in a struct clk to be in only one of {CM, PRM, SCM}, we must split the source clock selection into a separate struct clk from the clock enable/disable control.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock34xx.h |   82 +++++++++++++++++++++++++++++++--------
 1 files changed, 66 insertions(+), 16 deletions(-)
arch/arm/mach-omap2/clock34xx.h +66 -16
index 3ee60bc..3bd2bd9 100644
@@ -1463,12 +1463,10 @@ static const struct clksel mcbsp_15_clksel[] = {
 	{ .parent = NULL }
 };
 
-static struct clk mcbsp5_fck = {
-	.name		= "mcbsp_fck",
+static struct clk mcbsp5_src_fck = {
+	.name		= "mcbsp_src_fck",
 	.id		= 5,
 	.init		= &omap2_init_clksel_parent,
-	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 	.clksel_mask	= OMAP2_MCBSP5_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,

@@ -1477,12 +1475,21 @@ static struct clk mcbsp5_fck = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
-static struct clk mcbsp1_fck = {
+static struct clk mcbsp5_fck = {
 	.name		= "mcbsp_fck",
+	.id		= 5,
+	.parent		= &mcbsp5_src_fck,
+	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "core_l4_clkdm" },
+	.recalc		= &followparent_recalc,
+};
+
+static struct clk mcbsp1_src_fck = {
+	.name		= "mcbsp_src_fck",
 	.id		= 1,
 	.init		= &omap2_init_clksel_parent,
-	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,

@@ -1491,6 +1498,17 @@ static struct clk mcbsp1_fck = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
+static struct clk mcbsp1_fck = {
+	.name		= "mcbsp_fck",
+	.id		= 1,
+	.parent		= &mcbsp1_src_fck,
+	.enable_reg	= _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "core_l4_clkdm" },
+	.recalc		= &followparent_recalc,
+};
+
 /* CORE_48M_FCK-derived clocks */
 
 static struct clk core_48m_fck = {

@@ -2764,14 +2782,35 @@ static const struct clksel mcbsp_234_clksel[] = {
 	{ .parent = NULL }
 };
 
+static struct clk mcbsp2_src_fck = {
+	.name		= "mcbsp_src_fck",
+	.id		= 2,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
+	.clksel		= mcbsp_234_clksel,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "per_clkdm" },
+	.recalc		= &omap2_clksel_recalc,
+};
+
 static struct clk mcbsp2_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 2,
-	.init		= &omap2_init_clksel_parent,
+	.parent		= &mcbsp2_src_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
-	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "per_clkdm" },
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_src_fck = {
+	.name		= "mcbsp_src_fck",
+	.id		= 3,
+	.init		= &omap2_init_clksel_parent,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.clkdm		= { .name = "per_clkdm" },

@@ -2781,11 +2820,20 @@ static struct clk mcbsp2_fck = {
 static struct clk mcbsp3_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 3,
-	.init		= &omap2_init_clksel_parent,
+	.parent		= &mcbsp3_src_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
+	.flags		= CLOCK_IN_OMAP343X,
+	.clkdm		= { .name = "per_clkdm" },
+	.recalc		= &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_src_fck = {
+	.name		= "mcbsp_src_fck",
+	.id		= 4,
+	.init		= &omap2_init_clksel_parent,
 	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
+	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.clkdm		= { .name = "per_clkdm" },

@@ -2795,12 +2843,9 @@ static struct clk mcbsp3_fck = {
 static struct clk mcbsp4_fck = {
 	.name		= "mcbsp_fck",
 	.id		= 4,
-	.init		= &omap2_init_clksel_parent,
+	.parent		= &mcbsp4_src_fck,
 	.enable_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
-	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
-	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.clkdm		= { .name = "per_clkdm" },
 	.recalc		= &omap2_clksel_recalc,

@@ -3082,7 +3127,9 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&i2c3_fck,
 	&i2c2_fck,
 	&i2c1_fck,
+	&mcbsp5_src_fck,
 	&mcbsp5_fck,
+	&mcbsp1_src_fck,
 	&mcbsp1_fck,
 	&core_48m_fck,
 	&mcspi4_fck,

@@ -3198,8 +3245,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
 	&mcbsp2_ick,
 	&mcbsp3_ick,
 	&mcbsp4_ick,
+	&mcbsp2_src_fck,
 	&mcbsp2_fck,
+	&mcbsp3_src_fck,
 	&mcbsp3_fck,
+	&mcbsp4_src_fck,
 	&mcbsp4_fck,
 	&emu_src_ck,
 	&pclk_fck,
author maintainer
#2 lore raw

PATCH 2/3 OMAP2/3 clock: shorten some variable names in clock.c for legibility

In reply to Paul Walmsley

Some unnecessarily verbose variable names are used in several clock.c functions; clean these up per CodingStyle.

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/clock.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)
arch/arm/mach-omap2/clock.c +9 -9
index a2211fb..a604c38 100644
@@ -351,7 +351,7 @@ static void omap2_clk_wait_ready(struct clk *clk)
  */
 static int _omap2_clk_enable(struct clk *clk)
 {
-	u32 regval32;
+	u32 v;
 
 	if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
 		return 0;

@@ -365,11 +365,11 @@ static int _omap2_clk_enable(struct clk *clk)
 		return 0; /* REVISIT: -EINVAL */
 	}
 
-	regval32 = __raw_readl(clk->enable_reg);
+	v = __raw_readl(clk->enable_reg);
 	if (clk->flags & INVERT_ENABLE)
-		regval32 &= ~(1 << clk->enable_bit);
+		v &= ~(1 << clk->enable_bit);
 	else
-		regval32 |= (1 << clk->enable_bit);
+		v |= (1 << clk->enable_bit);
 	__raw_writel(regval32, clk->enable_reg);
 	wmb();
 

@@ -381,7 +381,7 @@ static int _omap2_clk_enable(struct clk *clk)
 /* Disables clock without considering parent dependencies or use count */
 static void _omap2_clk_disable(struct clk *clk)
 {
-	u32 regval32;
+	u32 v;
 
 	if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
 		return;

@@ -401,12 +401,12 @@ static void _omap2_clk_disable(struct clk *clk)
 		return;
 	}
 
-	regval32 = __raw_readl(clk->enable_reg);
+	v = __raw_readl(clk->enable_reg);
 	if (clk->flags & INVERT_ENABLE)
-		regval32 |= (1 << clk->enable_bit);
+		v |= (1 << clk->enable_bit);
 	else
-		regval32 &= ~(1 << clk->enable_bit);
-	__raw_writel(regval32, clk->enable_reg);
+		v &= ~(1 << clk->enable_bit);
+	__raw_writel(v, clk->enable_reg);
 	wmb();
 }
maintainer
#3 lore raw
In reply to Paul Walmsley
Quoted 25 lines · Paul Walmsley

Add a new field, prcm_mod, to the OMAP2/3 struct clk. Major effects of this change include:

- the removal of the register rewriting code for OMAP2xxx clock framework,

- the resolution of gcc and sparse warnings for the clock code,

- the removal of many __force void __iomem * casts in the clock tree,

- and the reduction of the register address field size in struct clk by two bytes per clk.

This series applies on top of the "OMAP2/3 clock: revise DPLL bypass handling in clock tree" series. This series is a prerequisite for the IDLEST handling revision patches, following shortly.

Boot-tested on 3430SDP and 2430SDP.

---

text data bss dec hex filename

3457748  160200  106600 3724548  38d504 vmlinux.3430sdp.orig
3457832  159768  106600 3724200  38d3a8 vmlinux.3430sdp
Quoted 10 lines
 arch/arm/mach-omap2/clock.c             |  223 +++++-----
 arch/arm/mach-omap2/clock.h             |    3 
 arch/arm/mach-omap2/clock24xx.c         |   58 ---
 arch/arm/mach-omap2/clock24xx.h         |  458 +++++++++++++--------
 arch/arm/mach-omap2/clock34xx.c         |   27 +
 arch/arm/mach-omap2/clock34xx.h         |  672 ++++++++++++++++++++-----------
 arch/arm/mach-omap2/cm.h                |    3 
 arch/arm/plat-omap/common.c             |    1 
 arch/arm/plat-omap/include/mach/clock.h |   26 +
 9 files changed, 874 insertions(+), 597 deletions(-)

Looks like patch 3/3 is missing?

Tony

author maintainer
#4 lore raw
Quoted 1 line · Tony Lindgren

Looks like patch 3/3 is missing?

vger ate it. Will split it up,

- Paul