Fix the NAND size overflow issue.

PATCH New Jason Jin 5 participants 10 messages Sep 19, 2008 – Oct 14, 2008

Subsystems (2)

Memory technology devices (MTD) NAND flash

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Jason Jin

author

2008-09-19 09:32 UTC #0 lore raw

PATCH 1/4 Fix the NAND size overflow issue.

When the NAND size is or large than 4G, the size will overflow, The adjustment in this patch try to fix this.

Signed-off-by Jason Jin <[email protected]>

---
 drivers/mtd/nand/nand.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

drivers/mtd/nand/nand.c +2 -2

index ebd2acd..71a0e4b 100644
@@ -63,11 +63,11 @@ void nand_init(void)
 	unsigned int size = 0;
 	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
 		nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
-		size += nand_info[i].size;
+		size += nand_info[i].size / 1024;
 		if (nand_curr_device == -1)
 			nand_curr_device = i;
 	}
-	printf("%u MiB\n", size / (1024 * 1024));
+	printf("%u MiB\n", size / 1024);
 
 #ifdef CFG_NAND_SELECT_DEVICE
 	/*

Signature · 1 line

1.5.4

Jason Jin

author

2008-09-19 09:32 UTC #1 lore raw

PATCH 2/4 Make the fsl_elbc_nand driver work for both 83xx and 85xx

This patch try to make the fsl_elbc_nand driver work for both 83xx and 85xx boards.
Move the FMR Macros from 83xx.h to fsl_lbc.h and redefine the elbc register structure in the driver.

Signed-off-by Jason Jin <[email protected]>

---
 drivers/mtd/nand/fsl_elbc_nand.c |   63 ++++++++++++++++++++++++----
 include/asm-ppc/fsl_lbc.h        |   85 ++++++++++++++++++++++++++++++++++++++
 include/mpc83xx.h                |   85 --------------------------------------
 3 files changed, 140 insertions(+), 93 deletions(-)

drivers/mtd/nand/fsl_elbc_nand.c +55 -8

index 4351824..b12c540 100644
@@ -52,6 +52,50 @@
 
 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
 
+/*
+ * Local Bus Controller Registers.
+ */
+typedef struct lbus_bank {
+	u32 br;			/* Base Register */
+	u32 or;			/* Option Register */
+} lbus_bank_t;
+
+typedef struct fsl_lbus {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;		/* UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;		/* UPMA Mode Register */
+	u32 mbmr;		/* UPMB Mode Register */
+	u32 mcmr;		/* UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
+	u32 mdr;		/* UPM Data Register */
+	u8 res3[0x4];
+	u32 lsor;		/* Special Operation Initiation Register */
+	u32 lsdmr;		/* SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;		/* UPM Refresh Timer */
+	u32 lsrt;		/* SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;		/* Transfer Error Status Register */
+	u32 ltedr;		/* Transfer Error Disable Register */
+	u32 lteir;		/* Transfer Error Interrupt Register */
+	u32 lteatr;		/* Transfer Error Attributes Register */
+	u32 ltear;		/* Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;		/* Configuration Register */
+	u32 lcrr;		/* Clock Ratio Register */
+	u8 res7[0x8];
+	u32 fmr;		/* Flash Mode Register */
+	u32 fir;		/* Flash Instruction Register */
+	u32 fcr;		/* Flash Command Register */
+	u32 fbar;		/* Flash Block Addr Register */
+	u32 fpar;		/* Flash Page Addr Register */
+	u32 fbcr;		/* Flash Byte Count Register */
+	u8 res8[0xF08];
+}fsl_lbus_t;
+
 struct fsl_elbc_ctrl;
 
 /* mtd information per set */

@@ -75,7 +119,7 @@ struct fsl_elbc_ctrl {
 	struct fsl_elbc_mtd *chips[MAX_BANKS];
 
 	/* device info */
-	lbus83xx_t *regs;
+	fsl_lbus_t *regs;
 	u8 __iomem *addr;        /* Address of assigned FCM buffer        */
 	unsigned int page;       /* Last page written to / read from      */
 	unsigned int read_bytes; /* Number of bytes read during command   */

@@ -171,7 +215,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 	int buf_num;
 
 	ctrl->page = page_addr;

@@ -211,7 +255,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 	long long end_tick;
 	u32 ltesr;

@@ -261,7 +305,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	if (priv->page_size) {
 		out_be32(&lbc->fir,

@@ -295,7 +339,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	ctrl->use_mdr = 0;

@@ -633,7 +677,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-	lbus83xx_t *lbc = ctrl->regs;
+	fsl_lbus_t *lbc = ctrl->regs;
 
 	if (ctrl->status != LTESR_CC)
 		return NAND_STATUS_FAIL;

@@ -693,13 +737,16 @@ static struct fsl_elbc_ctrl *elbc_ctrl;
 
 static void fsl_elbc_ctrl_init(void)
 {
-	immap_t *im = (immap_t *)CFG_IMMR;
-
 	elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 	if (!elbc_ctrl)
 		return;
 
+#ifdef CONFIG_MPC85xx
+	elbc_ctrl->regs = (void *)CFG_MPC85xx_LBC_ADDR;
+#else
+	immap_t *im = (immap_t *)CFG_IMMR;
 	elbc_ctrl->regs = &im->lbus;
+#endif
 
 	/* clear event registers */
 	out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);

include/asm-ppc/fsl_lbc.h +85 -0

89 lines not on this page · raw message

include/mpc83xx.h +0 ~~-85~~

91 lines not on this page · raw message

Signature · 1 line

1.5.4

Jason Jin

author

2008-09-19 09:32 UTC #2 lore raw

PATCH 3/4 Enable NAND support for MPC8536DS board

Define NAND support the 8536DS board. Add mem space and corresponding law/tlb entries for it.

Signed-off-by Jason Jin <[email protected]>

---
 board/freescale/mpc8536ds/law.c |    1 +
 board/freescale/mpc8536ds/tlb.c |    4 +++
 include/configs/MPC8536DS.h     |   52 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 56 insertions(+), 1 deletions(-)

board/freescale/mpc8536ds/law.c +1 -0

index cdf5215..84b23a3 100644
@@ -38,6 +38,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_NAND_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8536ds/tlb.c +4 -0

index 28a9fa8..55e5702 100644
@@ -66,6 +66,10 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256K, 1),
+
+	SET_TLB_ENTRY(1, CFG_NAND_BASE, CFG_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_16M, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

include/configs/MPC8536DS.h +51 -1

65 lines not on this page · raw message

Signature · 1 line

1.5.4

Jason Jin

author

2008-09-19 09:32 UTC #3 lore raw

PATCH 4/4 Enable NAND support for MPC8572DS board.

Define NAND support the 8572DS board. Add mem space and corresponding law/tlb entries for it.

Signed-off-by Jason Jin <[email protected]>

---
 board/freescale/mpc8572ds/law.c |    1 +
 board/freescale/mpc8572ds/tlb.c |    5 ++++
 include/configs/MPC8572DS.h     |   51 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 57 insertions(+), 0 deletions(-)

board/freescale/mpc8572ds/law.c +1 -0

index d69b593..5094de7 100644
@@ -36,6 +36,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_NAND_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8572ds/tlb.c +5 -0

index 965356a..df9dc50 100644
@@ -80,6 +80,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CFG_NAND_BASE, CFG_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

include/configs/MPC8572DS.h +51 -0

63 lines not on this page · raw message

Signature · 1 line

1.5.4

Scott Wood

2008-10-07 16:32 UTC #4 lore raw

PATCH 2/4 Make the fsl_elbc_nand driver work for both 83xx and 85xx

In reply to Jason Jin

Quoted 33 lines · Jason Jin

drivers/mtd/nand/fsl_elbc_nand.c +33 -0

+/*
+ * Local Bus Controller Registers.
+ */
+typedef struct lbus_bank {
+	u32 br;			/* Base Register */
+	u32 or;			/* Option Register */
+} lbus_bank_t;
+
+typedef struct fsl_lbus {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;		/* UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;		/* UPMA Mode Register */
+	u32 mbmr;		/* UPMB Mode Register */
+	u32 mcmr;		/* UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
+	u32 mdr;		/* UPM Data Register */
+	u8 res3[0x4];
+	u32 lsor;		/* Special Operation Initiation Register */
+	u32 lsdmr;		/* SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;		/* UPM Refresh Timer */
+	u32 lsrt;		/* SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;		/* Transfer Error Status Register */
+	u32 ltedr;		/* Transfer Error Disable Register */
+	u32 lteir;		/* Transfer Error Interrupt Register */
+	u32 lteatr;		/* Transfer Error Attributes Register */
+	u32 ltear;		/* Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;		/* Configuration Register */

drivers/mtd/nand/fsl_elbc_nand.c line 97

Quoted 10 lines

drivers/mtd/nand/fsl_elbc_nand.c +10 -0

+	u32 lcrr;		/* Clock Ratio Register */
+	u8 res7[0x8];
+	u32 fmr;		/* Flash Mode Register */
+	u32 fir;		/* Flash Instruction Register */
+	u32 fcr;		/* Flash Command Register */
+	u32 fbar;		/* Flash Block Addr Register */
+	u32 fpar;		/* Flash Page Addr Register */
+	u32 fbcr;		/* Flash Byte Count Register */
+	u8 res8[0xF08];
+}fsl_lbus_t;

Space after brace.

Can we put this in a header file that is shared by immap_83xx.h, immap_85xx.h, etc., rather than duplicating it here?

Quoted 4 lines

static void fsl_elbc_ctrl_init(void)
{
drivers/mtd/nand/fsl_elbc_nand.c +0 -2
-	immap_t *im = (immap_t *)CFG_IMMR;
-

drivers/mtd/nand/fsl_elbc_nand.c static struct fsl_elbc_ctrl *elbc_ctrl; · line 749

Quoted 10 lines

drivers/mtd/nand/fsl_elbc_nand.c +5 -0

 	elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 	if (!elbc_ctrl)
 		return;
 
+#ifdef CONFIG_MPC85xx
+	elbc_ctrl->regs = (void *)CFG_MPC85xx_LBC_ADDR;
+#else
+	immap_t *im = (immap_t *)CFG_IMMR;
 	elbc_ctrl->regs = &im->lbus;
+#endif

Did you try building this on 83xx? You'll get a type conflict warning because you duplicated the struct.

-Scott

Jin Zhengxiong-R64188

author

2008-10-08 09:45 UTC #5 lore raw

PATCH 2/4 Make the fsl_elbc_nand driver work for both 83xxand 85xx

Quoted 57 lines

-----Original Message-----
From: Wood Scott-B07421
Sent: Wednesday, October 08, 2008 12:33 AM
To: Jin Zhengxiong-R64188
Cc: u-boot at lists.denx.de
Subject: Re: [PATCH 2/4] Make the fsl_elbc_nand driver work for both 83xxand 85xx

Quoted 8 lines · Jason Jin

drivers/mtd/nand/fsl_elbc_nand.c +8 -0

+/*
+ * Local Bus Controller Registers.
+ */
+typedef struct lbus_bank {
+	u32 br;			/* Base Register */
+	u32 or;			/* Option Register */
+} lbus_bank_t;
+

drivers/mtd/nand/fsl_elbc_nand.c

Quoted 10 lines

drivers/mtd/nand/fsl_elbc_nand.c +10 -0

+typedef struct fsl_lbus {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;		/* UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;		/* UPMA Mode Register */
+	u32 mbmr;		/* UPMB Mode Register */
+	u32 mcmr;		/* UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;		/* Memory Refresh Timer

Prescaler Register */

drivers/mtd/nand/fsl_elbc_nand.c

Quoted 3 lines

drivers/mtd/nand/fsl_elbc_nand.c +3 -0

+	u32 mdr;		/* UPM Data Register */
+	u8 res3[0x4];
+	u32 lsor;		/* Special Operation Initiation

Quoted 12 lines

drivers/mtd/nand/fsl_elbc_nand.c +12 -0

+	u32 lsdmr;		/* SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;		/* UPM Refresh Timer */
+	u32 lsrt;		/* SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;		/* Transfer Error Status Register */
+	u32 ltedr;		/* Transfer Error Disable Register */
+	u32 lteir;		/* Transfer Error Interrupt Register */
+	u32 lteatr;		/* Transfer Error Attributes Register */
+	u32 ltear;		/* Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;		/* Configuration Register */

drivers/mtd/nand/fsl_elbc_nand.c line 97

Quoted 10 lines

drivers/mtd/nand/fsl_elbc_nand.c +10 -0

+	u32 lcrr;		/* Clock Ratio Register */
+	u8 res7[0x8];
+	u32 fmr;		/* Flash Mode Register */
+	u32 fir;		/* Flash Instruction Register */
+	u32 fcr;		/* Flash Command Register */
+	u32 fbar;		/* Flash Block Addr Register */
+	u32 fpar;		/* Flash Page Addr Register */
+	u32 fbcr;		/* Flash Byte Count Register */
+	u8 res8[0xF08];
+}fsl_lbus_t;

Space after brace.

Quoted 3 lines

Can we put this in a header file that is shared by immap_83xx.h, immap_85xx.h, etc., rather than duplicating it here?

Thanks.
I was trying to avoid too much changes to the code, which maybe result in other functions
can not work. Actually, As the different immap definition, to completly avoid the duplicating, we need to merge the lbc immap for 85xx/83xx and change the related code.

There is already a fsl_lbc.h file in include/asm but it is included by some .S file and can not move the structure into it. How about define a immap_fsl_lbc.h file for the structure?

Quoted 8 lines

Quoted 8 lines
static void fsl_elbc_ctrl_init(void)
{
drivers/mtd/nand/fsl_elbc_nand.c +0 -2
-	immap_t *im = (immap_t *)CFG_IMMR;
-
 	elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 	if (!elbc_ctrl)
 		return;

Quoted 8 lines

drivers/mtd/nand/fsl_elbc_nand.c static struct fsl_elbc_ctrl *elbc_ctrl; · line 749
Quoted 5 lines
drivers/mtd/nand/fsl_elbc_nand.c +4 -0
+#ifdef CONFIG_MPC85xx
+	elbc_ctrl->regs = (void *)CFG_MPC85xx_LBC_ADDR; #else
+	immap_t *im = (immap_t *)CFG_IMMR;
 	elbc_ctrl->regs = &im->lbus;
+#endif
Did you try building this on 83xx? You'll get a type conflict warning because you duplicated the struct.

Thanks, If we still define the structure in the file, we need to change the structure name.

Jason

Anton Vorontsov

2008-10-08 14:58 UTC #6 lore raw

PATCH 2/4 Make the fsl_elbc_nand driver work for both 83xxand 85xx

On Wed, Oct 08, 2008 at 05:45:01PM +0800, Jin Zhengxiong-R64188 wrote:
[...]

Quoted 9 lines

Thanks.
I was trying to avoid too much changes to the code, which maybe result in other functions
can not work. Actually, As the different immap definition, to completly avoid the duplicating, we need to merge the lbc immap for 85xx/83xx and change the related code.
There is already a fsl_lbc.h file in include/asm but it is included by some .S file and can not move the structure into it.

You can surround it with #ifndef __ASSEMBLY__

Signature · 3 lines

Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2

Jens Gehrlein

2008-09-19 10:04 UTC #7 lore raw

PATCH 1/4 Fix the NAND size overflow issue.

In reply to Jason Jin

Hi Jason,

Quoted 22 lines

-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de]On Behalf Of Jason Jin
Sent: Friday, September 19, 2008 11:33 AM
To: scottwood at freescale.com
Cc: u-boot at lists.denx.de; Jason Jin
Subject: [U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.
When the NAND size is or large than 4G, the size will overflow, The adjustment in this patch try to fix this.
Signed-off-by Jason Jin <[email protected]>
---
 drivers/mtd/nand/nand.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/nand/nand.c +0 -0
index ebd2acd..71a0e4b 100644

drivers/mtd/nand/nand.c void nand_init(void) · line 71

Quoted 10 lines

drivers/mtd/nand/nand.c +1 -2

@@ -63,11 +63,11 @@ void nand_init(void)
 	unsigned int size = 0;
 	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
 		nand_init_chip(&nand_info[i], &nand_chip[i], 
 base_address[i]);
-		size += nand_info[i].size;
+		size += nand_info[i].size / 1024;
 		if (nand_curr_device == -1)
 			nand_curr_device = i;
 	}
-	printf("%u MiB\n", size / (1024 * 1024));

      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

According to this line I suppose, the value of nand_info[i].size is in Bytes. So, if the NAND chip is >= 4 GiB this variable has already been overflowed, when nand_init_chip returns. Indeed, I didn't check the source code of the NAND driver. Am I wrong or did you modify the driver?

Kind Regards,
Jens

Jin Zhengxiong-R64188

author

2008-09-23 02:20 UTC #8 lore raw

PATCH 1/4 Fix the NAND size overflow issue.

Quoted 45 lines

-----Original Message-----
From: Jens Gehrlein [mailto:Jens.Gehrlein at tqs.de]
Sent: Friday, September 19, 2008 6:05 PM
To: Jin Zhengxiong-R64188; Wood Scott-B07421
Cc: u-boot at lists.denx.de
Subject: RE: [U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.
Hi Jason,
Quoted 12 lines
-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de]On Behalf Of Jason Jin
Sent: Friday, September 19, 2008 11:33 AM
To: scottwood at freescale.com
Cc: u-boot at lists.denx.de; Jason Jin
Subject: [U-Boot] [PATCH 1/4] Fix the NAND size overflow issue.
When the NAND size is or large than 4G, the size will overflow, The adjustment in this patch try to fix this.
Review
Quoted 6 lines
Signed-off-by Jason Jin <[email protected]>
---
 drivers/mtd/nand/nand.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
(quoted diff) +0 -0
b/drivers/mtd/nand/nand.c index
drivers/mtd/nand/nand.c void nand_init(void) · line 65
Quoted 7 lines
ebd2acd..71a0e4b 100644
drivers/mtd/nand/nand.c +0 -0
@@ -63,11 +63,11 @@ void nand_init(void)
 	unsigned int size = 0;
 	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
 		nand_init_chip(&nand_info[i], &nand_chip[i], 
base_address[i]);
drivers/mtd/nand/nand.c void nand_init(void) · line 70
Quoted 6 lines
drivers/mtd/nand/nand.c +1 -2
-		size += nand_info[i].size;
+		size += nand_info[i].size / 1024;
 		if (nand_curr_device == -1)
 			nand_curr_device = i;
 	}
-	printf("%u MiB\n", size / (1024 * 1024));
      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Quoted 7 lines

According to this line I suppose, the value of nand_info[i].size is in Bytes. So, if the NAND chip is >= 4 GiB this variable has already been overflowed, when nand_init_chip returns.
Indeed, I didn't check the source code of the NAND driver. Am I wrong or did you modify the driver?

Hi, Jens,
You are right, the nand_info[i].size is in Bytes. and this patch just can fix those chips with memory cell less than 4GBytes.
The nand_info[i].size is widly used in u-boot, If change it to MByte, lots of tests need to do.

Thanks
Jaosn

Wolfgang Denk

2008-10-14 11:27 UTC #9 lore raw

PATCH 1/4 Fix the NAND size overflow issue.

In reply to Jason Jin

Dear Jason Jin,

Quoted 13 lines · In message <[email protected]> you…

When the NAND size is or large than 4G, the size will overflow, The adjustment in this patch try to fix this.
Signed-off-by Jason Jin <[email protected]>
---
 drivers/mtd/nand/nand.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
drivers/mtd/nand/nand.c +0 -0
index ebd2acd..71a0e4b 100644

drivers/mtd/nand/nand.c void nand_init(void) · line 70

Quoted 10 lines

drivers/mtd/nand/nand.c +2 -2

@@ -63,11 +63,11 @@ void nand_init(void)
 	unsigned int size = 0;
 	for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
 		nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]);
-		size += nand_info[i].size;
+		size += nand_info[i].size / 1024;
 		if (nand_curr_device == -1)
 			nand_curr_device = i;
 	}
-	printf("%u MiB\n", size / (1024 * 1024));
+	printf("%u MiB\n", size / 1024);

I think the comment is misleading.

Assuming we have a single NAND device that is bigger than 4 GiB, then the overflow would actually happen earlier, i. e. when storing the size in nand_info[].size, as nand_info[].size is an "u_int32_t".

So the only situation your patch can fix is when there are several NAND devices, each of them smaller than 4 GiB, but the total size exceeds this limit.

Applied after changing the comment.

Thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines

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