ppc4xx: Add AMCC Arches board support (dual 460GT)
PATCH v5 1/3 ppc4xx: Add AMCC Arches board support (dual 460GT)
The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express.
---
v2:
- Added Arches (460GT) support to the existing Canyonlands (460) board files since the Canyonlands board files support all current AMCC PPC460EX/GT boards.
v3:
- Correct tab/spaces in canyonlands.h file.
v4:
- Fix commit text (line to long)
- remove unneed timeout for ETH_PLL lock
- remove CONFIG_EXTRA_ENV_SETTINGS from "USB connectivity" section
- seperated CONFIG_CMD_xxx on a per board bases
- Use ethprime to set Arches default ethernet port to 1 v5:
- No changes.
MAKEALL | 1 + Makefile | 3 +- board/amcc/canyonlands/canyonlands.c | 140 ++++++++++++++++++++++ board/amcc/canyonlands/init.S | 17 +++ include/configs/amcc-common.h | 17 +++- include/configs/canyonlands.h | 219 +++++++++++++++++++++++++++++++--- include/ppc440.h | 3 + 7 files changed, 383 insertions(+), 17 deletions(-)
MAKEALL +1 -0
@@ -161,6 +161,7 @@ LIST_4xx=" \ alpr \ AP1000 \ AR405 \ + arches \ ASH405 \ bamboo \ bamboo_nand \
Makefile +2 -1
@@ -1206,7 +1206,8 @@ bubinga_config: unconfig CANBT_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd -# Canyonlands & Glacier use different U-Boot images +# Arches, Canyonlands & Glacier use different U-Boot images +arches_config \ canyonlands_config \ glacier_config: unconfig @mkdir -p $(obj)include
board/amcc/canyonlands/canyonlands.c +140 -0
204 lines not on this page · raw message
board/amcc/canyonlands/init.S +17 -0
@@ -77,11 +77,16 @@ tlbtab: /* PCIe UTL register */ tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) +#if !defined(CONFIG_ARCHES) /* TLB-entry for NAND */ tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) /* TLB-entry for CPLD */ tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#else + /* TLB-entry for FPGA */ + tlbentry(CFG_FPGA_BASE, SZ_16M, CFG_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#endif /* TLB-entry for OCM */ tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
@@ -92,6 +97,18 @@ tlbtab: /* AHB: Internal USB Peripherals (USB, SATA) */ tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) +#if defined(CONFIG_RAPIDIO) + /* TLB-entries for RapidIO (SRIO) */ + tlbentry(CFG_SRGPL0_REG_BAR, SZ_16M, CFG_SRGPL0_REG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_SRGPL0_CFG_BAR, SZ_16M, CFG_SRGPL0_CFG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_SRGPL0_MNT_BAR, SZ_16M, CFG_SRGPL0_MNT_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_I2ODMA_BASE, SZ_1K, 0x00100000, + 0x4, AC_R|AC_W|SA_G|SA_I) +#endif + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
include/configs/amcc-common.h +16 -1
@@ -160,6 +160,13 @@#endif /* +* Only very few boards have default netdev not set to eth0 (like Arches) +*/ +#if !defined(CONFIG_USE_NETDEV ) +#define CONFIG_USE_NETDEV eth0 +#endif + +/* * Only some 4xx PPC's are equipped with an FPU */ #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
@@ -184,7 +191,7 @@* General common environment variables shared on all AMCC eval boards */ #define CONFIG_AMCC_DEF_ENV \ - "netdev=eth0\0" \ + "netdev=" xstr(CONFIG_USE_NETDEV) "\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -197,8 +204,10 @@"initrd_high=30000000\0" \"kernel_addr_r=400000\0" \"fdt_addr_r=800000\0" \ +"ramdisk_addr_r=C00000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \CONFIG_AMCC_DEF_ENV_ROOTPATH /*
@@ -214,6 +223,12 @@"tftp ${fdt_addr_r} ${fdt_file}; " \"run nfsargs addip addtty addmisc;" \"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ +"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ +"tftp ${fdt_addr_r} ${fdt_file};" \ +"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ +"net_self=run net_self_load;" \ +"run ramargs addip addtty addmisc;" \ +"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"/*
include/configs/canyonlands.h +204 -15
324 lines not on this page · raw message
include/ppc440.h +3 -0
@@ -1349,6 +1349,9 @@#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11 +/* Ethernet Status Register */ +#define SDR0_ETH_STS 0x4104 +/* Miscealleneaous Function Reg. (SDR0_MFR) */ #define SDR0_MFR 0x4300#define SDR0_MFR_T0TxFL 0x00800000/* force parity error TAHOE0 Tx FIFO bits 0:63 */
Signature · 1 line
1.5.5
PATCH v5 1/3 ppc4xx: Add AMCC Arches board support (dual 460GT)
Quoted 7 lines · Adam Graham
The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express.
Applied (1...3) to ppc4xx/next. Thanks.
Best regards,
Stefan
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