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x86, UV: non-sparse irq based uv_setup_irq()/uv_teardown_irq() functions

PATCH In review Dean Nelson 1 participant 2 messages Oct 20, 2008 – Oct 21, 2008 x86

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Dean Nelson

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PATCH 1/1 x86, UV: non-sparse irq based uv_setup_irq()/uv_teardown_irq() functions

Provide a means for UV interrupt MMRs to be setup with the message to be sent when an MSI-like interrupt is raised.

Signed-off-by Dean Nelson <[email protected]>

---

Ingo,

A version of this patch, based on the sparse irq code, you applied to tip/x86/uv. I'm submitting this verision, which is not based on the sparse irq code, to replace that patch since the sparse irq code has been pulled from linux-next, and I'd like this functionality to get into linux 2.6.28.

The differences between the two patches are minimal. The bulk of it was to move the code that was added to io_apic.c to io_apic_64.c instead. I also made a small change to some of the comments.

Thanks,
Dean

 arch/x86/kernel/Makefile     |    2 
 arch/x86/kernel/io_apic_64.c |   67 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/uv_irq.c     |   79 +++++++++++++++++++++++++++++++++++++++
 include/asm-x86/uv/uv_irq.h  |   36 +++++++++++++++++
 4 files changed, 183 insertions(+), 1 deletion(-)
arch/x86/kernel/uv_irq.c new file +79 -0
Index: linux/arch/x86/kernel/uv_irq.c
===================================================================
@@ -0,0 +1,79 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI UV IRQ functions
+ *
+ * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+
+#include <asm/apic.h>
+#include <asm/uv/uv_irq.h>
+
+static void uv_noop(unsigned int irq)
+{
+}
+
+static unsigned int uv_noop_ret(unsigned int irq)
+{
+	return 0;
+}
+
+static void uv_ack_apic(unsigned int irq)
+{
+	ack_APIC_irq();
+}
+
+struct irq_chip uv_irq_chip = {
+	.name		= "UV-CORE",
+	.startup	= uv_noop_ret,
+	.shutdown	= uv_noop,
+	.enable		= uv_noop,
+	.disable	= uv_noop,
+	.ack		= uv_noop,
+	.mask		= uv_noop,
+	.unmask		= uv_noop,
+	.eoi		= uv_ack_apic,
+	.end		= uv_noop,
+};
+
+/*
+ * Set up a mapping of an available irq and vector, and enable the specified
+ * MMR that defines the MSI-like message that is to be sent to the specified
+ * CPU when an interrupt is raised.
+ */
+int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
+		 unsigned long mmr_offset)
+{
+	int irq;
+	int ret;
+
+	irq = create_irq();
+	if (irq <= 0)
+		return -EBUSY;
+
+	ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset);
+	if (ret != irq)
+		destroy_irq(irq);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(uv_setup_irq);
+
+/*
+ * Tear down a mapping of an irq and vector, and disable the specified MMR that
+ * defined the MSI-like message that was to be sent to the specified CPU when
+ * an interrupt was raised.
+ *
+ * Set mmr_blade and mmr_offset to what was passed in on uv_setup_irq().
+ */
+void uv_teardown_irq(unsigned int irq, int mmr_blade, unsigned long mmr_offset)
+{
+	arch_disable_uv_irq(mmr_blade, mmr_offset);
+	destroy_irq(irq);
+}
+EXPORT_SYMBOL_GPL(uv_teardown_irq);
include/asm-x86/uv/uv_irq.h new file +36 -0
Index: linux/include/asm-x86/uv/uv_irq.h
===================================================================
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI UV IRQ definitions
+ *
+ * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef ASM_X86__UV__UV_IRQ_H
+#define ASM_X86__UV__UV_IRQ_H
+
+/* If a generic version of this structure gets defined, eliminate this one. */
+struct uv_IO_APIC_route_entry {
+	__u64	vector		:  8,
+		delivery_mode	:  3,
+		dest_mode	:  1,
+		delivery_status	:  1,
+		polarity	:  1,
+		__reserved_1	:  1,
+		trigger		:  1,
+		mask		:  1,
+		__reserved_2	: 15,
+		dest		: 32;
+};
+
+extern struct irq_chip uv_irq_chip;
+
+extern int arch_enable_uv_irq(char *, unsigned int, int, int, unsigned long);
+extern void arch_disable_uv_irq(int, unsigned long);
+
+extern int uv_setup_irq(char *, int, int, unsigned long);
+extern void uv_teardown_irq(unsigned int, int, unsigned long);
+
+#endif /* ASM_X86__UV__UV_IRQ_H */
arch/x86/kernel/Makefile +1 -1
Index: linux/arch/x86/kernel/Makefile
===================================================================
@@ -109,7 +109,7 @@ obj-$(CONFIG_MICROCODE)			+= microcode.o
 # 64 bit specific files
 ifeq ($(CONFIG_X86_64),y)
         obj-y				+= genapic_64.o genapic_flat_64.o genx2apic_uv_x.o tlb_uv.o
-	obj-y				+= bios_uv.o uv_sysfs.o
+	obj-y				+= bios_uv.o uv_sysfs.o uv_irq.o
         obj-y				+= genx2apic_cluster.o
         obj-y				+= genx2apic_phys.o
         obj-$(CONFIG_X86_PM_TIMER)	+= pmtimer_64.o
arch/x86/kernel/io_apic_64.c +67 -0

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#1 lore raw
Quoted 19 lines · Dean Nelson

Provide a means for UV interrupt MMRs to be setup with the message to be sent when an MSI-like interrupt is raised.

Signed-off-by Dean Nelson <[email protected]>

---

Ingo,

A version of this patch, based on the sparse irq code, you applied to tip/x86/uv. I'm submitting this verision, which is not based on the sparse irq code, to replace that patch since the sparse irq code has been pulled from linux-next, and I'd like this functionality to get into linux 2.6.28.

The differences between the two patches are minimal. The bulk of it was to move the code that was added to io_apic.c to io_apic_64.c instead. I also made a small change to some of the comments.

Quoted 8 lines

Thanks,
Dean

 arch/x86/kernel/Makefile     |    2 
 arch/x86/kernel/io_apic_64.c |   67 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/uv_irq.c     |   79 +++++++++++++++++++++++++++++++++++++++
 include/asm-x86/uv/uv_irq.h  |   36 +++++++++++++++++
 4 files changed, 183 insertions(+), 1 deletion(-)

It turns out that the sparse irq code and the version of this patch based on that made it into 2.6.28, so...

please ignore this patch.