MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT and flush dcache upon relocation
PATCH 1/1 MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT and flush dcache upon relocation
This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This enables support for boards where the lowlevel initialization is already done when U-Boot runs (e.g. via OnChip ROM).
Also the data cache will be flushed upon relocation. This is missing in the current implementation.
All this will be used in the upcoming VCTH board support.
--- cpu/mips/start.S | 19 ++++++++++++++++++- 1 files changed, 18 insertions(+), 1 deletions(-)
cpu/mips/start.S +18 -1
@@ -243,9 +243,11 @@ reset: mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* CONFIG0 register */ li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ /* Initialize $gp. */
@@ -255,6 +257,7 @@ reset: 1: lw gp, 0(ra) +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* Initialize any external memory. */ la t9, lowlevel_init
@@ -271,6 +274,7 @@ reset: */ li t0, CONF_CM_CACHABLE_NONCOHERENT mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ /* Set up temporary stack. */
@@ -323,6 +327,14 @@ relocate_code: * t1 = target address * t2 = source end address */ + + /* + * Save destination address and size for later usage in flush_cache() + */ + move t7, a1 /* save gd in t7 */ + move a0, t1 /* a0 <-- destination addr */ + sub a1, t2, t0 /* a1 <-- size */ + /* On the purple board we copy the code earlier in a special way * in order to solve flash problems */
@@ -338,6 +350,11 @@ relocate_code: /* If caches were enabled, we would have to flush them here. */ + /* a0 & a1 are already set up for flush_cache(start, size) */ + la t9, flush_cache + jalr t9 + nop + /* Jump to where we've relocated ourselves. */ addi t0, a2, in_ram - _start
@@ -387,7 +404,7 @@ in_ram: bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */ - move a0, a1 + move a0, t7 /* a0 <-- gd */ la t9, board_init_r jr t9 move a1, a2 /* delay slot */
Signature · 1 line
1.6.0.4
PATCH 1/1 MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT and flush dcache upon relocation
Hi Stefan,
Quoted 7 lines · Stefan Roese
This patch adds the
CONFIG_SKIP_LOWLEVEL_INIToption tostart.S. This enables support for boards where the lowlevel initialization is already done when U-Boot runs (e.g. via OnChip ROM).Also the data cache will be flushed upon relocation. This is missing in the current implementation.
Quoted 6 lines
All this will be used in the upcoming VCTH board support.
Signed-off-by Stefan Roese <[email protected]>--- cpu/mips/start.S | 19 ++++++++++++++++++- 1 files changed, 18 insertions(+), 1 deletions(-)
sorry for my late reply. Please find the comments below.
Quoted 6 lines
cpu/mips/start.S +0
-0@@ -243,9 +243,11 @@ reset: mtc0 zero, CP0_COUNT
cpu/mips/start.S reset: · line 253
Quoted 10 lines
cpu/mips/start.S +2
-0mtc0 zero, CP0_COMPARE +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* CONFIG0 register */ li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ /* Initialize $gp. */
It might be preferable to remove the /* CONFIG_SKIP_LOWLEVEL_INIT */ comment for better readability, IMHO.
Quoted 28 lines
cpu/mips/start.S +13
-0@@ -323,6 +327,14 @@ relocate_code: * t1 = target address * t2 = source end address */ + + /* + * Save destination address and size for later usage in flush_cache() + */ + move t7, a1 /* save gd in t7 */ + move a0, t1 /* a0 <-- destination addr */ + sub a1, t2, t0 /* a1 <-- size */ + /* On the purple board we copy the code earlier in a special way * in order to solve flash problems */@@ -338,6 +350,11 @@ relocate_code: /* If caches were enabled, we would have to flush them here. */ + /* a0 & a1 are already set up for flush_cache(start, size) */ + la t9, flush_cache + jalr t9 + nop + /* Jump to where we've relocated ourselves. */ addi t0, a2, in_ram - _start
cpu/mips/start.S in_ram: · line 410
Quoted 8 lines
cpu/mips/start.S +1
-1@@ -387,7 +404,7 @@ in_ram: bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */ - move a0, a1 + move a0, t7 /* a0 <-- gd */ la t9, board_init_r jr t9 move a1, a2 /* delay slot */
- Could we separate this flush_cache patch from this patch?
- Please use save register, s[0-7], instead of t7, since t7 register might be overwritten with another value in flush_cache(). Furthermore, in this case, a2 should be saved as well.
Thanks,
Shinya
PATCH 1/1 MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT and flush dcache upon relocation
Quoted 14 lines · Shinya Kuribayashi
Quoted 14 lines
cpu/mips/start.S +2
-0@@ -243,9 +243,11 @@ reset: mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* CONFIG0 register */ li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
Quoted 5 lines
cpu/mips/start.S reset: · line 253
Quoted 2 lines
cpu/mips/start.S +0
-0/* Initialize $gp. */It might be preferable to remove the /*
CONFIG_SKIP_LOWLEVEL_INIT*/ comment for better readability, IMHO.
Hmmm. I usually prefer to add those comments to the #else and #endif since it makes the code better readable. Especially when the chunks of code in-between gets bigger. So I would prefer to keep this comment. OK?
Quoted 31 lines
Quoted 31 lines
cpu/mips/start.S +13
-0@@ -323,6 +327,14 @@ relocate_code: * t1 = target address * t2 = source end address */ + + /* + * Save destination address and size for later usage in flush_cache() + */ + move t7, a1 /* save gd in t7 */ + move a0, t1 /* a0 <-- destination addr */ + sub a1, t2, t0 /* a1 <-- size */ + /* On the purple board we copy the code earlier in a special way * in order to solve flash problems */@@ -338,6 +350,11 @@ relocate_code: /* If caches were enabled, we would have to flush them here. */ + /* a0 & a1 are already set up for flush_cache(start, size) */ + la t9, flush_cache + jalr t9 + nop + /* Jump to where we've relocated ourselves. */ addi t0, a2, in_ram - _start@@ -387,7 +404,7 @@ in_ram: bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */
Quoted 7 lines
cpu/mips/start.S in_ram: · line 410
Quoted 5 lines
cpu/mips/start.S +1
-1- move a0, a1 + move a0, t7 /* a0 <-- gd */ la t9, board_init_r jr t9 move a1, a2 /* delay slot */- Could we separate this
flush_cachepatch from this patch?
OK, will do.
Quoted 3 lines
- Please use save register, s[0-7], instead of t7, since t7 register might be overwritten with another value in
flush_cache(). Furthermore, in this case, a2 should be saved as well.
I'm still new to MIPS so thanks for your suggestions. I'll try to provide a fixed up patch today.
Thanks.
Best regards,
Stefan
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PATCH 1/1 MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT and flush dcache upon relocation
Quoted 10 lines · Stefan Roese
Quoted 10 lines
Quoted 10 lines
cpu/mips/start.S +2
-0@@ -243,9 +243,11 @@ reset: mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* CONFIG0 register */ li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
Quoted 7 lines
Quoted 4 lines
cpu/mips/start.S reset: · line 253
Quoted 2 lines
cpu/mips/start.S +0
-0/* Initialize $gp. */It might be preferable to remove the /*
CONFIG_SKIP_LOWLEVEL_INIT*/ comment for better readability, IMHO.Hmmm. I usually prefer to add those comments to the #else and #endif since it makes the code better readable.
We have just 3 lines within #if-endif, then it looks better without the latter comment in this case, IMHO.
Quoted 2 lines
Especially when the chunks of code in-between gets bigger. So I would prefer to keep this comment. OK?
Fully agreed, of course. Thanks for the explanation, and it's up to you.
Quoted 10 lines
Quoted 1 line
- Could we separate this
flush_cachepatch from this patch?OK, will do.
Quoted 3 lines
- Please use save register, s[0-7], instead of t7, since t7 register might be overwritten with another value in
flush_cache(). Furthermore, in this case, a2 should be saved as well.I'm still new to MIPS so thanks for your suggestions. I'll try to provide a fixed up patch today.