OMAP3: Remove BITx magic

Index: u-boot-arm/include/asm-arm/arch-omap3/bits.h
===================================================================
@@ -1,48 +0,0 @@
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software;  you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0	(1 << 0)
-#define BIT1	(1 << 1)
-#define BIT2	(1 << 2)
-#define BIT3	(1 << 3)
-#define BIT4	(1 << 4)
-#define BIT5	(1 << 5)
-#define BIT6	(1 << 6)
-#define BIT7	(1 << 7)
-#define BIT8	(1 << 8)
-#define BIT9	(1 << 9)
-#define BIT10	(1 << 10)
-#define BIT11	(1 << 11)
-#define BIT12	(1 << 12)
-#define BIT13	(1 << 13)
-#define BIT14	(1 << 14)
-#define BIT15	(1 << 15)
-#define BIT16	(1 << 16)
-#define BIT17	(1 << 17)
-#define BIT18	(1 << 18)
-#define BIT19	(1 << 19)
-#define BIT20	(1 << 20)
-#define BIT21	(1 << 21)
-#define BIT22	(1 << 22)
-#define BIT23	(1 << 23)
-#define BIT24	(1 << 24)
-#define BIT25	(1 << 25)
-#define BIT26	(1 << 26)
-#define BIT27	(1 << 27)
-#define BIT28	(1 << 28)
-#define BIT29	(1 << 29)
-#define BIT30	(1 << 30)
-#define BIT31	(1 << 31)
-
-#endif

Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h
===================================================================
@@ -39,7 +39,8 @@
 #define PRODUCTION_ID		(OMAP34XX_TAP_BASE + 0x208)
 
 /* device type */
-#define DEVICE_MASK		(BIT8 | BIT9 | BIT10)
+#define DEVICE_MASK		(0x7 << 8)
+#define SYSBOOT_MASK		0x1F
 #define TST_DEVICE		0x0
 #define EMU_DEVICE		0x1
 #define HS_DEVICE		0x2

@@ -104,7 +105,7 @@
 #define SMS_SYSCONFIG		(OMAP34XX_SMS_BASE + 0x10)
 #define SMS_RG_ATT0		(OMAP34XX_SMS_BASE + 0x48)
 #define SMS_CLASS_ARB0		(OMAP34XX_SMS_BASE + 0xD0)
-#define BURSTCOMPLETE_GROUP7	BIT31
+#define BURSTCOMPLETE_GROUP7	(0x1 << 31)
 
 /* SDRC */
 #define SDRC_SYSCONFIG		(OMAP34XX_SDRC_BASE + 0x10)

@@ -115,13 +116,13 @@
 #define SDRC_DLLA_STATUS	(OMAP34XX_SDRC_BASE + 0x64)
 #define SDRC_DLLB_CTRL		(OMAP34XX_SDRC_BASE + 0x68)
 #define SDRC_DLLB_STATUS	(OMAP34XX_SDRC_BASE + 0x6C)
-#define DLLPHASE		BIT1
-#define LOADDLL			BIT2
+#define DLLPHASE		(0x1 << 1)
+#define LOADDLL			(0x1 << 2)
 #define DLL_DELAY_MASK		0xFF00
-#define DLL_NO_FILTER_MASK	(BIT8 | BIT9)
+#define DLL_NO_FILTER_MASK	((0x1 << 9) | (0x1 << 8))
 
 #define SDRC_POWER		(OMAP34XX_SDRC_BASE + 0x70)
-#define WAKEUPPROC		BIT26
+#define WAKEUPPROC		(0x1 << 26)
 
 #define SDRC_MCFG_0		(OMAP34XX_SDRC_BASE + 0x80)
 #define SDRC_MR_0		(OMAP34XX_SDRC_BASE + 0x84)

@@ -141,7 +142,7 @@
 #define CMD_ENTR_SRFRSH		0x5
 #define CMD_CKE_HIGH		0x6
 #define CMD_CKE_LOW		0x7
-#define SOFTRESET		BIT1
+#define SOFTRESET		(0x1 << 1)
 #define SMART_IDLE		(0x2 << 3)
 #define REF_ON_IDLE		(0x1 << 6)
 

@@ -162,7 +163,7 @@
 #define TSICR			0x40	/* rw */
 #define TCAR2			0x44	/* r */
 /* enable sys_clk NO-prescale /1 */
-#define GPT_EN			((0 << 2) | BIT1 | BIT0)
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
 
 /* Watchdog */
 #define WWPS			0x34	/* r */

@@ -210,6 +211,29 @@
 #define PRM_CLKSEL		0x48306d40
 #define PRM_RSTCTRL		0x48307250
 #define PRM_CLKSRC_CTRL		0x48307270
+#define SYSCLKDIV_1		(0x1 << 6)
+#define SYSCLKDIV_2		(0x1 << 7)
+
+#define CLKSEL_GPT1		(0x1 << 0)
+
+#define EN_GPT1			(0x1 << 0)
+#define EN_32KSYNC		(0x1 << 2)
+
+#define ST_WDT2			(0x1 << 5)
+
+#define ST_MPU_CLK		(0x1 << 0)
+
+#define ST_CORE_CLK		(0x1 << 0)
+
+#define ST_PERIPH_CLK		(0x1 << 1)
+
+#define ST_IVA2_CLK		(0x1 << 0)
+
+#define RESETDONE		(0x1 << 0)
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
 
 /* SMX-APE */
 #define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)

Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c
===================================================================
@@ -27,7 +27,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/bits.h>
 #include <asm/arch/clocks.h>
 #include <asm/arch/clocks_omap3.h>
 #include <asm/arch/mem.h>

@@ -46,17 +45,17 @@ u32 get_osc_clk_speed(void)
 	val = readl(PRM_CLKSRC_CTRL);
 
 	/* If SYS_CLK is being divided by 2, remove for now */
-	val = (val & (~BIT7)) | BIT6;
+	val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
 	writel(val, PRM_CLKSRC_CTRL);
 
 	/* enable timer2 */
-	val = readl(CM_CLKSEL_WKUP) | BIT0;
+	val = readl(CM_CLKSEL_WKUP) | CLKSEL_GPT1;
 	writel(val, CM_CLKSEL_WKUP);	/* select sys_clk for GPT1 */
 
 	/* Enable I and F Clocks for GPT1 */
-	val = readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+	val = readl(CM_ICLKEN_WKUP) | EN_GPT1 | EN_32KSYNC;
 	writel(val, CM_ICLKEN_WKUP);
-	val = readl(CM_FCLKEN_WKUP) | BIT0;
+	val = readl(CM_FCLKEN_WKUP) | EN_GPT1;
 	writel(val, CM_FCLKEN_WKUP);
 
 	writel(0, OMAP34XX_GPT1 + TLDR);	/* start counting at 0 */

@@ -160,7 +159,7 @@ void prcm_init(void)
 
 	/* Unlock MPU DPLL (slows things down, and needed later) */
 	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
-	wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+	wait_on_value(ST_MPU_CLK, 0, CM_IDLEST_PLL_MPU, LDELAY);
 
 	/* Getting the base address of Core DPLL param table */
 	dpll_param_p = (dpll_param *) get_core_dpll_param();

@@ -173,7 +172,7 @@ void prcm_init(void)
 		 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
 		 */
 		sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
-		wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+		wait_on_value(ST_CORE_CLK, 0, CM_IDLEST_CKGEN, LDELAY);
 
 		/*
 		 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't

@@ -194,7 +193,7 @@ void prcm_init(void)
 		sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
 		sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);		/* lock mode */
 
-		wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+		wait_on_value(ST_CORE_CLK, 1, CM_IDLEST_CKGEN, LDELAY);
 	} else if (is_running_in_flash()) {
 		/*
 		 * if running from flash, jump to small relocated code

@@ -223,7 +222,7 @@ void prcm_init(void)
 
 	/* PER DPLL */
 	sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
-	wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+	wait_on_value(ST_PERIPH_CLK, 0, CM_IDLEST_CKGEN, LDELAY);
 
 	/* Getting the base address to PER DPLL param table */
 	/* Set N */

@@ -253,7 +252,7 @@ void prcm_init(void)
 	sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);	/* set n */
 	sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);	/* FREQSEL */
 	sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);		/* lock mode */
-	wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+	wait_on_value(ST_PERIPH_CLK, 2, CM_IDLEST_CKGEN, LDELAY);
 
 	/* Getting the base address to MPU DPLL param table */
 	dpll_param_p = (dpll_param *) get_mpu_dpll_param();

@@ -267,7 +266,7 @@ void prcm_init(void)
 	sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n);	/* Set N */
 	sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
 	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);	/* lock mode */
-	wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+	wait_on_value(ST_MPU_CLK, 1, CM_IDLEST_PLL_MPU, LDELAY);
 
 	/* Getting the base address to IVA DPLL param table */
 	dpll_param_p = (dpll_param *) get_iva_dpll_param();

@@ -277,13 +276,13 @@ void prcm_init(void)
 
 	/* IVA DPLL (set to 12*20=240MHz) */
 	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
-	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+	wait_on_value(ST_IVA2_CLK, 0, CM_IDLEST_PLL_IVA2, LDELAY);
 	sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2);	/* set M2 */
 	sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m);	/* set M */
 	sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);	/* set N */
 	sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
 	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);	/* lock mode */
-	wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+	wait_on_value(ST_IVA2_CLK, 1, CM_IDLEST_PLL_IVA2, LDELAY);
 
 	/* Set up GPTimers to sys_clk source only */
 	sr32(CM_CLKSEL_PER, 0, 8, 0xff);

Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c
===================================================================
@@ -27,7 +27,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/bits.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
 #include <command.h>

@@ -177,7 +176,7 @@ void do_sdrc_init(u32 offset, u32 early)
 	if (early) {
 		/* reset sdrc controller */
 		writel(SOFTRESET, SDRC_SYSCONFIG);
-		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+		wait_on_value(RESETDONE, RESETDONE, SDRC_STATUS, 12000000);
 		writel(0, SDRC_SYSCONFIG);
 
 		/* setup sdrc to ball mux */

Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c
===================================================================
@@ -27,7 +27,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/bits.h>
 #include <asm/arch/mem.h>	/* get mem tables */
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>

@@ -147,14 +146,6 @@ u32 get_board_type(void)
 		return sysinfo.board_type_v1;
 }
 
-/******************************************************************
- * get_sysboot_value() - get init word settings
- ******************************************************************/
-inline u32 get_sysboot_value(void)
-{
-	return 0x0000003F & readl(CONTROL_STATUS);
-}
-
 /***************************************************************************
  *  get_gpmc0_base() - Return current address hardware will be
  *     fetching from. The below effectively gives what is correct, its a bit

@@ -318,10 +309,7 @@ u32 is_running_in_sdram(void)
  ***************************************************************/
 u32 get_boot_type(void)
 {
-	u32 v;
-
-	v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
-	return v;
+	return (readl(CONTROL_STATUS) & SYSBOOT_MASK);
 }
 
 /*************************************************************

Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c
===================================================================
@@ -34,7 +34,6 @@
  */
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/bits.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 

@@ -251,7 +250,7 @@ void watchdog_init(void)
 
 	sr32(CM_FCLKEN_WKUP, 5, 1, 1);
 	sr32(CM_ICLKEN_WKUP, 5, 1, 1);
-	wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5);	/* some issue here */
+	wait_on_value(ST_WDT2, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
 
 	writel(WD_UNLOCK1, WD2_BASE + WSPR);
 	wait_for_command_complete(WD2_BASE);

Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c
===================================================================
@@ -33,8 +33,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/bits.h>
-
+#include <asm/io.h>
 #include <asm/proc-armv/ptrace.h>
 
 #define TIMER_LOAD_VAL 0

@@ -175,16 +174,11 @@ static ulong lastinc;
 /* nothing really to do with interrupts, just starts up a counter. */
 int interrupt_init(void)
 {
-	int32_t val;
-
-	/*
-	 * Start the counter ticking up
-	 * reload value on overflow
-	 */
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
-	/* mask to enable timer */
-	val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0;
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
+	/* start the counter ticking up, reload value on overflow */
+	writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TLDR);
+	/* enable timer */
+	writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+		CONFIG_SYS_TIMERBASE + TCLR);
 
 	reset_timer_masked();	/* init the timestamp and lastinc value */
 

Index: u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c
===================================================================
@@ -23,7 +23,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/bits.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/clocks.h>
 #include <asm/arch/sys_proto.h>