nand: Fix cache and memory inconsistent issue
PATCH v3 1/1 nand: Fix cache and memory inconsistent issue
we load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, not invalidate i-cache before we jump to RAM. when the system is cache enable and the TLB/page attribute of system memory is cacheable, it will cause issue.
- 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue.
The patch fix the cache issue.
---
Stefan,
I'm not familiar with ppc4xx, could you workout one patch for nand_boot.c?
Thanks,
Dave
nand_spl/board/freescale/mpc8313erdb/Makefile | 6 +++++- nand_spl/nand_boot_fsl_elbc.c | 5 +++++ 2 files changed, 10 insertions(+), 1 deletions(-)
nand_spl/board/freescale/mpc8313erdb/Makefile +5 -1
@@ -34,7 +34,8 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ + time.o cache.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -79,6 +80,9 @@ $(obj)ns16550.c: $(obj)nand_init.c: ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c +$(obj)cache.c: + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + $(obj)time.c: ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c
nand_spl/nand_boot_fsl_elbc.c +5 -0
@@ -143,6 +143,11 @@ void nand_boot(void)* Jump to U-Boot image */ puts ("transfering control\n" ); +/* +* Clean d-cache and invalidate i-cache, to +* make sure that no stale data is executed. +*/ +flush_cache (CONFIG_SYS_NAND_U_BOOT_DST ,CONFIG_SYS_NAND_U_BOOT_SIZE ); uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START ;uboot (); }
Signature · 1 line
1.5.4
PATCH v3 1/1 nand: Fix cache and memory inconsistent issue
Quoted 11 lines · Dave Liu
we load the secondary stage u-boot image from NAND to system memory by
nand_load, but we did not flush d-cache to memory, not invalidate i-cache before we jump to RAM. when the system is cache enable and the TLB/page attribute of system memory is cacheable, it will cause issue.- 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue.
Quoted 8 lines
The patch fix the cache issue.
Signed-off-by Dave Liu <[email protected]>---
Stefan,I'm not familiar with ppc4xx, could you workout one patch for
nand_boot.c?
All 4xx platforms using nand_boot.c run with D-Cache disabled at that time. So it's currently not needed here.
Best regards,
Stefan
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PATCH v3 1/1 nand: Fix cache and memory inconsistent issue
In reply to Dave LiuQuoted 6 lines · Dave Liu
we load the secondary stage u-boot image from NAND to system memory by
nand_load, but we did not flush d-cache to memory, not invalidate i-cache before we jump to RAM. when the system is cache enable and the TLB/page attribute of system memory is cacheable, it will cause issue.
Quoted 8 lines
- 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue.The patch fix the cache issue.
Signed-off-by Dave Liu <[email protected]>
Applied to u-boot-nand-flash/next
-Scott