OMAP3: Convert register access to structure style, part #2

Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c
===================================================================
@@ -167,16 +167,16 @@ void do_irq(struct pt_regs *pt_regs)
 
 static ulong timestamp;
 static ulong lastinc;
-static u32 *timer_base = (u32 *)CONFIG_SYS_TIMERBASE;
+static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
 
 /* nothing really to do with interrupts, just starts up a counter. */
 int interrupt_init(void)
 {
 	/* start the counter ticking up, reload value on overflow */
-	writel(TIMER_LOAD_VAL, timer_base + OFFS(TLDR));
+	writel(TIMER_LOAD_VAL, &timer_base->tldr);
 	/* enable timer */
 	writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
-		timer_base + OFFS(TCLR));
+		&timer_base->tclr);
 
 	reset_timer_masked();	/* init the timestamp and lastinc value */
 

@@ -232,13 +232,13 @@ void udelay(unsigned long usec)
 void reset_timer_masked(void)
 {
 	/* reset time, capture current incrementer value time */
-	lastinc = readl(timer_base + OFFS(TCRR));
+	lastinc = readl(&timer_base->tcrr);
 	timestamp = 0;		/* start "advancing" time stamp from 0 */
 }
 
 ulong get_timer_masked(void)
 {
-	ulong now = readl(timer_base + OFFS(TCRR)); /* current tick value */
+	ulong now = readl(&timer_base->tcrr); /* current tick value */
 
 	if (now >= lastinc)	/* normal mode (non roll) */
 		/* move stamp fordward with absoulte diff ticks */

123 lines not on this page · raw message

Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c
===================================================================
@@ -32,9 +32,9 @@
 #include <i2c.h>
 
 extern omap3_sysinfo sysinfo;
-static u32 *gpmc_base = (u32 *)GPMC_BASE;
-static u32 *sdrc_base = (u32 *)OMAP34XX_SDRC_BASE;
-static u32 *ctrl_base = (u32 *)OMAP34XX_CTRL_BASE;
+static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
+static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
 
 /******************************************
  * get_cpu_rev(void) - extract version info

@@ -61,8 +61,7 @@ u32 get_cpu_rev(void)
  ****************************************************/
 u32 is_mem_sdr(void)
 {
-	if (readl(sdrc_base + OFFS(SDRC_MR_0 + SDRC_CS0_OSET)) ==
-			SDP_SDRC_MR_0_SDR)
+	if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
 		return 1;
 	return 0;
 }

@@ -70,12 +69,12 @@ u32 is_mem_sdr(void)
 /***********************************************************************
  * get_cs0_size() - get size of chip select 0/1
  ************************************************************************/
-u32 get_sdr_cs_size(u32 offset)
+u32 get_sdr_cs_size(u32 cs)
 {
 	u32 size;
 
 	/* get ram size field */
-	size = readl(sdrc_base + OFFS(SDRC_MCFG_0 + offset)) >> 8;
+	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
 	size &= 0x3FF;		/* remove unwanted bits */
 	size *= SZ_2M;		/* find size in MB */
 	return size;

@@ -91,7 +90,7 @@ u32 get_sdr_cs_offset(u32 cs)
 	if (!cs)
 		return 0;
 
-	offset = readl(sdrc_base + OFFS(SDRC_CS_CFG));
+	offset = readl(&sdrc_base->cs_cfg);
 	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
 
 	return offset;

@@ -129,7 +128,7 @@ u32 get_gpmc0_base(void)
 {
 	u32 b;
 
-	b = readl(gpmc_base + OFFS(GPMC_CONFIG7));
+	b = readl(&gpmc_cs_base->config7);
 	b &= 0x1F;		/* keep base [5:0] */
 	b = b << 24;		/* ret 0x0b000000 */
 	return b;

@@ -243,7 +242,7 @@ u32 is_running_in_sdram(void)
  ***************************************************************/
 u32 get_boot_type(void)
 {
-	return (readl(ctrl_base + OFFS(CONTROL_STATUS)) & SYSBOOT_MASK);
+	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
 }
 
 /*************************************************************

@@ -251,6 +250,5 @@ u32 get_boot_type(void)
  *************************************************************/
 u32 get_device_type(void)
 {
-	return ((readl(ctrl_base + OFFS(CONTROL_STATUS)) &
-		(DEVICE_MASK)) >> 8);
+	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 }

204 lines not on this page · raw message

Index: u-boot-arm/board/omap3/evm/evm.c
===================================================================
@@ -89,38 +89,35 @@ void set_muxconf_regs(void)
  *****************************************************************************/
 static void setup_net_chip(void)
 {
-	unsigned int *gpio3_base = (unsigned int *)OMAP34XX_GPIO3_BASE;
-	unsigned int *gpmc_cs6_base = (unsigned int *)GPMC_CONFIG_CS6_BASE;
-	unsigned short *ctrl_base = (unsigned short *)OMAP34XX_CTRL_BASE;
+	gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
+	gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
+	ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
-	writel(NET_GPMC_CONFIG1, gpmc_cs6_base + OFFS(GPMC_CONFIG1));
-	writel(NET_GPMC_CONFIG2, gpmc_cs6_base + OFFS(GPMC_CONFIG2));
-	writel(NET_GPMC_CONFIG3, gpmc_cs6_base + OFFS(GPMC_CONFIG3));
-	writel(NET_GPMC_CONFIG4, gpmc_cs6_base + OFFS(GPMC_CONFIG4));
-	writel(NET_GPMC_CONFIG5, gpmc_cs6_base + OFFS(GPMC_CONFIG5));
-	writel(NET_GPMC_CONFIG6, gpmc_cs6_base + OFFS(GPMC_CONFIG6));
-	writel(NET_GPMC_CONFIG7, gpmc_cs6_base + OFFS(GPMC_CONFIG7));
+	writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
 
 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
-	writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1)) | 0x0E00,
-	       ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1));
+	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1)) | 0x0E00,
-		ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1));
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1)) | 0x0E00,
-		ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1));
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
 
 	/* Make GPIO 64 as output pin */
-	writel(readl(gpio3_base + OFFS(GPIO_OE)) & ~(GPIO0),
-		gpio3_base + OFFS(GPIO_OE));
+	writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
 
 	/* Now send a pulse on the GPIO pin */
-	writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT));
+	writel(GPIO0, &gpio3_base->setdataout);
 	udelay(1);
-	writel(GPIO0, gpio3_base + OFFS(GPIO_CLEARDATAOUT));
+	writel(GPIO0, &gpio3_base->cleardataout);
 	udelay(1);
-	writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT));
+	writel(GPIO0, &gpio3_base->setdataout);
 }
 

Index: u-boot-arm/include/configs/omap3_beagle.h
===================================================================
@@ -285,7 +285,8 @@
 #define ENV_IS_VARIABLE		1
 
 #ifndef __ASSEMBLY__
-extern unsigned int *nand_cs_base;
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

@@ -295,15 +296,17 @@ extern unsigned int boot_flash_type;
 
 
 #define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD)))
+			writel(d, &nand_cs_base->nand_cmd)
 #define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR)))
-#define WRITE_NAND(d, adr) writew(d, (nand_cs_base + OFFS(GPMC_NAND_DAT)))
-#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT)))
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
 
 /* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0)
-#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0)
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
 #define NAND_DISABLE_CE(nand)
 #define NAND_ENABLE_CE(nand)
 #define NAND_WAIT_READY(nand)	udelay(10)

Index: u-boot-arm/include/configs/omap3_evm.h
===================================================================
@@ -290,7 +290,8 @@
 #define ENV_IS_VARIABLE			1
 
 #ifndef __ASSEMBLY__
-extern unsigned int *nand_cs_base;
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

@@ -300,20 +301,21 @@ extern unsigned int boot_flash_type;
 
 
 #define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD)))
+			writel(d, &nand_cs_base->nand_cmd)
 #define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR)))
-#define WRITE_NAND(d, adr) writel(d, (nand_cs_base + OFFS(GPMC_NAND_DAT)))
-#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT)))
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
 
 /* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0)
-#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0)
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
 #define NAND_DISABLE_CE(nand)
 #define NAND_ENABLE_CE(nand)
 #define NAND_WAIT_READY(nand)	udelay(10)
 
-
 /*----------------------------------------------------------------------------
  * SMSC9115 Ethernet from SMSC9118 family
  *----------------------------------------------------------------------------

Index: u-boot-arm/include/configs/omap3_overo.h
===================================================================
@@ -277,7 +277,8 @@
 #define ENV_IS_VARIABLE			1
 
 #ifndef __ASSEMBLY__
-extern unsigned int *nand_cs_base;
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

@@ -287,15 +288,17 @@ extern unsigned int boot_flash_type;
 
 
 #define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD)))
+			writel(d, &nand_cs_base->nand_cmd)
 #define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR)))
-#define WRITE_NAND(d, adr) writel(d, (nand_cs_base + OFFS(GPMC_NAND_DAT)))
-#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT)))
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
 
 /* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0)
-#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0)
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
 #define NAND_DISABLE_CE(nand)
 #define NAND_ENABLE_CE(nand)
 #define NAND_WAIT_READY(nand)	udelay(10)

Index: u-boot-arm/include/configs/omap3_pandora.h
===================================================================
@@ -276,7 +276,8 @@
 #define ENV_IS_VARIABLE			1
 
 #ifndef __ASSEMBLY__
-extern unsigned int *nand_cs_base;
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

@@ -286,15 +287,17 @@ extern unsigned int boot_flash_type;
 
 
 #define WRITE_NAND_COMMAND(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD)))
+			writel(d, &nand_cs_base->nand_cmd)
 #define WRITE_NAND_ADDRESS(d, adr)\
-			writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR)))
-#define WRITE_NAND(d, adr) writew(d, (nand_cs_base + OFFS(GPMC_NAND_DAT)))
-#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT)))
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
 
 /* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0)
-#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0)
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
 #define NAND_DISABLE_CE(nand)
 #define NAND_ENABLE_CE(nand)
 #define NAND_WAIT_READY(nand)	udelay(10)

Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h
===================================================================
@@ -75,7 +75,15 @@
 
 /* 32KTIMER */
 #define SYNC_32KTIMER_BASE		0x48320000
-#define S32K_CR				0x10
+
+#ifndef __ASSEMBLY__
+
+typedef struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;		/* 0x10 */
+} s32ktimer_t;
+
+#endif /* __ASSEMBLY__ */
 
 /* OMAP3 GPIO registers */
 #define OMAP34XX_GPIO1_BASE		0x48310000

@@ -85,9 +93,15 @@
 #define OMAP34XX_GPIO5_BASE		0x49056000
 #define OMAP34XX_GPIO6_BASE		0x49058000
 
-#define GPIO_OE				0x34
-#define GPIO_CLEARDATAOUT		0x90
-#define GPIO_SETDATAOUT			0x94
+#ifndef __ASSEMBLY__
+typedef struct gpio {
+	unsigned char res1[0x34];
+	unsigned int oe;		/* 0x34 */
+	unsigned char res2[0x58];
+	unsigned int cleardataout;	/* 0x90 */
+	unsigned int setdataout;	/* 0x94 */
+} gpio_t;
+#endif /* __ASSEMBLY__ */
 
 #define GPIO0				(0x1 << 0)
 #define GPIO1				(0x1 << 1)

Index: u-boot-arm/include/asm-arm/arch-omap3/mem.h
===================================================================
@@ -25,18 +25,19 @@
 #ifndef _MEM_H_
 #define _MEM_H_
 
-#define SDRC_CS0_OSET	0x0
-#define SDRC_CS1_OSET	0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
+//#define SDRC_CS0_OSET	0x0
+//#define SDRC_CS1_OSET	0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
 
-#ifndef __ASSEMBLY__
+#define CS0		0x0
+#define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
 
+#ifndef __ASSEMBLY__
 typedef enum {
 	STACKED = 0,
 	IP_DDR = 1,
 	COMBO_DDR = 2,
 	IP_SDR = 3,
 } mem_t;
-
 #endif /* __ASSEMBLY__ */
 
 #define EARLY_INIT	1

Index: u-boot-arm/board/omap3/beagle/beagle.c
===================================================================
@@ -62,8 +62,8 @@ int misc_init_r(void)
 {
 
 	unsigned char byte;
-	unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE;
-	unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE;
+	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
+	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
 
 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

@@ -97,18 +97,14 @@ int misc_init_r(void)
 	i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
 
 	/* Configure GPIOs to output */
-	writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2),
-		gpio6_base + OFFS(GPIO_OE));
+	writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), &gpio6_base->oe);
 	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
-		GPIO15 | GPIO14 | GPIO13 | GPIO12),
-		gpio5_base + OFFS(GPIO_OE));
+		GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
 
 	/* Set GPIOs */
-	writel(GPIO10 | GPIO9 | GPIO3 | GPIO2,
-		gpio6_base + OFFS(GPIO_SETDATAOUT));
+	writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, &gpio6_base->setdataout);
 	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
-		GPIO15 | GPIO14 | GPIO13 | GPIO12,
-		gpio5_base + OFFS(GPIO_SETDATAOUT));
+		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
 
 	return 0;
 }

Index: u-boot-arm/board/omap3/overo/overo.c
===================================================================
@@ -61,8 +61,8 @@ int misc_init_r(void)
 {
 
 	unsigned char byte;
-	unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE;
-	unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE;
+	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
+	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
 
 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

@@ -102,18 +102,14 @@ int misc_init_r(void)
 	i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
 
 	/* Configure GPIOs to output */
-	writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2),
-		gpio6_base + OFFS(GPIO_OE));
+	writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), &gpio6_base->oe);
 	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
-		GPIO15 | GPIO14 | GPIO13 | GPIO12),
-		gpio5_base + OFFS(GPIO_OE));
+		GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
 
 	/* Set GPIOs */
-	writel(GPIO10 | GPIO9 | GPIO3 | GPIO2,
-		gpio6_base + OFFS(GPIO_SETDATAOUT));
+	writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, &gpio6_base->setdataout);
 	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
-		GPIO15 | GPIO14 | GPIO13 | GPIO12,
-		gpio5_base + OFFS(GPIO_SETDATAOUT));
+		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
 
 	return 0;
 }

Index: u-boot-arm/board/omap3/pandora/pandora.c
===================================================================
@@ -61,10 +61,10 @@ int misc_init_r(void)
 {
 
 	unsigned char byte;
-	unsigned int *gpio1_base = (unsigned int *)OMAP34XX_GPIO1_BASE;
-	unsigned int *gpio4_base = (unsigned int *)OMAP34XX_GPIO4_BASE;
-	unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE;
-	unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE;
+	gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
+	gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
+	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
+	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
 
 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

@@ -98,16 +98,15 @@ int misc_init_r(void)
 	i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
 
 	/* Configure GPIOs to output */
-	writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23),
-		gpio1_base + OFFS(GPIO_OE));
-	writel(~GPIO22, gpio4_base + OFFS(GPIO_OE));	/* 118 */
+	writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);
+	writel(~GPIO22, &gpio4_base->oe);	/* 118 */
 	writel(~(GPIO0 | GPIO1 | GPIO28 | GPIO29 | GPIO30 | GPIO31),
-		gpio5_base + OFFS(GPIO_OE));	/* 128, 129, 156-159 */
-	writel(~GPIO4, gpio6_base + OFFS(GPIO_OE));	/* 164 */
+		&gpio5_base->oe);	/* 128, 129, 156-159 */
+	writel(~GPIO4, &gpio6_base->oe);	/* 164 */
 
 	/* Set GPIOs */
-	writel(GPIO28, gpio5_base + OFFS(GPIO_SETDATAOUT));
-	writel(GPIO4, gpio6_base + OFFS(GPIO_SETDATAOUT));
+	writel(GPIO28, &gpio5_base->setdataout);
+	writel(GPIO4, &gpio6_base->setdataout);
 
 	return 0;
 }

Index: u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c
===================================================================
@@ -43,26 +43,27 @@ void sdelay(unsigned long loops)
 /*****************************************************************
  * sr32 - clear & set a value in a bit range for a 32 bit address
  *****************************************************************/
-void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
 {
 	u32 tmp, msk = 0;
 	msk = 1 << num_bits;
 	--msk;
-	tmp = readl(addr) & ~(msk << start_bit);
+	tmp = readl((u32)addr) & ~(msk << start_bit);
 	tmp |= value << start_bit;
-	writel(tmp, addr);
+	writel(tmp, (u32)addr);
 }
 
 /*********************************************************************
  * wait_on_value() - common routine to allow waiting for changes in
  *   volatile regs.
  *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+		  u32 bound)
 {
 	u32 i = 0, val;
 	do {
 		++i;
-		val = readl(read_addr) & read_bit_mask;
+		val = readl((u32)read_addr) & read_bit_mask;
 		if (val == match_value)
 			return 1;
 		if (i == bound)

Index: u-boot-arm/include/asm-arm/arch-omap3/sys_proto.h
===================================================================
@@ -61,8 +61,8 @@ void setup_auxcr(void);
 void try_unlock_memory(void);
 u32 get_boot_type(void);
 void v7_flush_dcache_all(u32);
-void sr32(u32, u32, u32, u32);
-u32 wait_on_value(u32, u32, u32, u32);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void make_cs1_contiguous(void);
 void omap_nand_switch_ecc(int);