ppc440spe-adma: ADMA driver for PPC440SP(e) systems
Subsystems (5)
PATCH 11/11 ppc440spe-adma: ADMA driver for PPC440SP(e) systems
Adds the platform device definitions and the architecture specific support
routines for the ppc440spe adma driver.
Any board equipped with PPC440SP(e) controller may utilize this driver.
Signed-off-by Yuri Tikhonov <[email protected]>
Signed-off-by Ilya Yanok <[email protected]>
--- arch/powerpc/boot/dts/katmai.dts | 30 + arch/powerpc/include/asm/async_tx.h | 76 + arch/powerpc/include/asm/dcr-regs.h | 20 + arch/powerpc/include/asm/ppc440spe_adma.h | 177 + arch/powerpc/include/asm/ppc440spe_dma.h | 259 ++ arch/powerpc/include/asm/ppc440spe_xor.h | 150 + arch/powerpc/platforms/44x/Makefile | 1 + arch/powerpc/platforms/44x/ppc440spe_dma_engines.c | 277 ++ drivers/dma/Kconfig | 13 + drivers/dma/Makefile | 1 + drivers/dma/ppc440spe-adma.c | 4142 ++++++++++++++++++++ 11 files changed, 5146 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/include/asm/async_tx.h create mode 100644 arch/powerpc/include/asm/ppc440spe_adma.h create mode 100644 arch/powerpc/include/asm/ppc440spe_dma.h create mode 100644 arch/powerpc/include/asm/ppc440spe_xor.h create mode 100644 arch/powerpc/platforms/44x/ppc440spe_dma_engines.c create mode 100644 drivers/dma/ppc440spe-adma.c
arch/powerpc/boot/dts/katmai.dts +30 -0
@@ -392,6 +392,36 @@ 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */ 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>; }; + DMA0: dma0 { + interrupt-parent = <&DMA0>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = < + 0 &UIC0 0x14 4 + 1 &UIC1 0x16 4>; + }; + DMA1: dma1 { + interrupt-parent = <&DMA1>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = < + 0 &UIC0 0x16 4 + 1 &UIC1 0x16 4>; + }; + xor { + interrupt-parent = <&UIC1>; + interrupts = <0x1f 4>; + }; + sysacecf@4fe000000 { + compatible = "xlnx,opb-sysace-1.00.b"; + interrupt-parent = <&UIC2>; + interrupts = <0x19 4>; + reg = <0x00000004 0xfe000000 0x100>; + }; }; chosen {
arch/powerpc/include/asm/async_tx.h new file +76 -0
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arch/powerpc/include/asm/dcr-regs.h +20 -0
@@ -157,4 +157,24 @@#define L2C_SNP_SSR_32G 0x0000f000#define L2C_SNP_ESR 0x00000800 +#define DCRN_SDR_CONFIG_ADDR 0xe +#define DCRN_SDR_CONFIG_DATA 0xf + +/* I2O/DMA */ +#define DCRN_I2O0_IBAL 0x066 +#define DCRN_I2O0_IBAH 0x067 +#define DCRN_SDR_SRST 0x0200 +#define DCRN_SDR_SRST_I2ODMA (0x80000000 >> 15)/* Reset I2O/DMA */ + +/* 440SP/440SPe XOR DCRs */ +#define DCRN_MQ0_XORBA 0x44 +#define DCRN_MQ0_CF2H 0x46 +#define DCRN_MQ0_CFBHL 0x4f +#define DCRN_MQ0_BAUH 0x50 + +/* HB/LL Paths Configuration Register */ +#define MQ0_CFBHL_TPLM 28 +#define MQ0_CFBHL_HBCL 23 +#define MQ0_CFBHL_POLY 15 +#endif /* __DCR_REGS_H__ */
arch/powerpc/include/asm/ppc440spe_adma.h new file +177 -0
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arch/powerpc/include/asm/ppc440spe_dma.h new file +259 -0
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arch/powerpc/include/asm/ppc440spe_xor.h new file +150 -0
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arch/powerpc/platforms/44x/Makefile +1 -0
@@ -5,3 +5,4 @@ obj-$(CONFIG_SAM440EP) += sam440ep.o obj-$(CONFIG_WARP) += warp.o obj-$(CONFIG_WARP) += warp-nand.o obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o +obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc440spe_dma_engines.o
arch/powerpc/platforms/44x/ppc440spe_dma_engines.c new file +277 -0
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drivers/dma/Kconfig +13 -0
@@ -64,6 +64,19 @@ config MV_XOR ---help--- Enable support for the Marvell XOR engine. +config AMCC_PPC440SPE_ADMA + tristate "AMCC PPC440SPe ADMA support" + depends on 440SPe || 440SP + select ASYNC_CORE + select DMA_ENGINE + select ARCH_HAS_ASYNC_TX_FIND_CHANNEL + default y + ---help--- + Enable support for the AMCC PPC440SPe RAID engines. + +config ARCH_HAS_ASYNC_TX_FIND_CHANNEL + bool + config DMA_ENGINE bool
drivers/dma/Makefile +1 -0
@@ -7,3 +7,4 @@ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_MV_XOR) += mv_xor.o obj-$(CONFIG_DW_DMAC) += dw_dmac.o +obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc440spe-adma.o
drivers/dma/ppc440spe-adma.c new file +4142 -0
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Signature · 1 line
1.5.6.1
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