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ehci-omap clock rewrite test patches

PATCH In review Paul Walmsley 2 participants 6 messages Dec 11, 2008

Subsystems (7)
Arm (32-bit) USB Arm sub-architectures OMAP2+ support +3 more subsystems
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Paul Walmsley

author maintainer
#0 lore raw

cover ehci-omap clock rewrite test patches

Hi,

This series - not for merging - is for those who are trying to get ehci-omap.c working on their hardware.

The series programs the clocks through the clock framework, rather than writing registers directly. It also adds some debugging and drops some unnecessary register writes.

Unfortunately, there is no hardware here for me to test these on, so these patches have only been compile-tested. Note also that patch 2 should be implemented differently before any final merge; it is written this way for testing purposes only.

- Paul

---

Paul Walmsley (3):
OMAP3 clock: Add debugging in omap3_noncore_dpll_enable() OMAP3 EHCI: use clock framework to program DPLL5, DPLL5_M2_CLK OMAP3 EHCI: drop unnecessary debug writes, per Vikram Pandita

 arch/arm/mach-omap2/clock34xx.c |    4 ++
 drivers/usb/host/ehci-omap.c    |   73 +++++++++++++++++++--------------------
 2 files changed, 40 insertions(+), 37 deletions(-)
author maintainer
#1 lore raw

PATCH 1/3 OMAP3 EHCI: drop unnecessary debug writes, per Vikram Pandita

Drop some PRCM-related register writes that now appear to be unnecessasry:

http://marc.info/?l=linux-omap&m=122901972412835&w=2

Cc Vikram Pandita <[email protected]>
---
 drivers/usb/host/ehci-omap.c |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)
drivers/usb/host/ehci-omap.c +0 -16
index 1b3266c..5252e75 100644
@@ -186,22 +186,6 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 			cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
 	/* End DPLL5 programming */
 
-
-	/* PRCM settings for USBHOST:
-	 * Interface clk un-related to domain transition
-	 */
-	cm_write_mod_reg(0 << OMAP3430ES2_AUTO_USBHOST_SHIFT,
-				OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
-
-	/* Disable sleep dependency with MPU and IVA */
-	cm_write_mod_reg((0 << OMAP3430ES2_EN_MPU_SHIFT) |
-				(0 << OMAP3430ES2_EN_IVA2_SHIFT),
-				OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
-
-	/* Disable Automatic transition of clock */
-	cm_write_mod_reg(0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT,
-				OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
-
 	/* Enable Clocks for USBHOST */
 	ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,
 						USBHOST_ICKL);
author maintainer
#2 lore raw

PATCH 2/3 OMAP3 EHCI: use clock framework to program DPLL5, DPLL5_M2_CLK

In reply to Paul Walmsley

For testing only, not for merging.

Use the clock framework to program DPLL5, DPLL5_M2_CLK.

---
 drivers/usb/host/ehci-omap.c |   57 +++++++++++++++++++++++++++---------------
 1 files changed, 36 insertions(+), 21 deletions(-)
drivers/usb/host/ehci-omap.c +36 -21
index 5252e75..2057f58 100644
@@ -70,6 +70,8 @@ struct ehci_omap_clock_defs {
 	struct clk	*usbhost1_48m_fck_clk;
 	struct clk	*usbtll_fck_clk;
 	struct clk	*usbtll_ick_clk;
+	struct clk	*dpll5_clk;
+	struct clk	*dpll5_m2_clk;
 };
 
 /* Clock names as per clock framework: May change so keep as #defs */

@@ -163,28 +165,29 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 				((char *)hcd_to_ehci(hcd)) +
 					sizeof(struct ehci_hcd));
 
-	/* Start DPLL5 Programming:
-	 * Clock Framework is not doing this now:
-	 * This will be done in clock framework later
+	/*
+	 * Make sure DPLL5 is programmed for 120MHz
+	 * XXX should be done at DPLL init time
+	 * XXX dpll rates should be assigned to clk->rate at init time
+	 * XXX enable DPLL autoidle
 	 */
-	/* Enable DPLL 5 : Based on Input of 13Mhz*/
-	cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)|
-			(120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT),
-			PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
-
-	cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT,
-			PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
-
-	cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) |
-			(7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT),
-			PLL_MOD, OMAP3430ES2_CM_CLKEN2);
-
-	while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) &
-				OMAP3430ES2_ST_PERIPH2_CLK_MASK))
-		dev_dbg(hcd->self.controller,
-			"idlest2 = 0x%x\n",
-			cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
-	/* End DPLL5 programming */
+	ehci_clocks->dpll5_clk = clk_get(&dev->dev, "dpll5_ck");
+	if (IS_ERR(ehci_clocks->dpll5_clk)) {
+		WARN_ON(1);
+		return PTR_ERR(ehci_clocks->dpll5_clk);
+	};
+	if (clk_get_rate(ehci_clocks->dpll5_clk) != 120000000)
+		clk_set_rate(ehci_clocks->dpll5_clk, 120000000);
+	clk_enable(ehci_clocks->dpll5_clk);
+
+	/* Program dpll5_m2_clk divider for no division */
+	ehci_clocks->dpll5_m2_clk = clk_get(&dev->dev, "dpll5_m2_ck");
+	if (IS_ERR(ehci_clocks->dpll5_m2_clk)) {
+		WARN_ON(1);
+		return PTR_ERR(ehci_clocks->dpll5_m2_clk);
+	};
+	clk_enable(ehci_clocks->dpll5_m2_clk);
+	clk_set_rate(ehci_clocks->dpll5_m2_clk, 120000000);
 
 	/* Enable Clocks for USBHOST */
 	ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,

@@ -375,6 +378,18 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 		ehci_clocks->usbtll_ick_clk = NULL;
 	}
 
+	if (ehci_clocks->dpll5_m2_clk != NULL) {
+		clk_disable(ehci_clocks->dpll5_m2_clk);
+		clk_put(ehci_clocks->dpll5_m2_clk);
+		ehci_clocks->dpll5_m2_clk = NULL;
+	}
+
+	if (ehci_clocks->dpll5_clk != NULL) {
+		clk_disable(ehci_clocks->dpll5_clk);
+		clk_put(ehci_clocks->dpll5_clk);
+		ehci_clocks->dpll5_clk = NULL;
+	}
+
 
 #ifdef EXTERNAL_PHY_RESET
 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
#3 lore raw

RE: [PATCH 2/3] OMAP3 EHCI: use clock framework to program DPLL5, DPLL5_M2_CLK

Paul

Quoted 19 lines

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of Paul Walmsley
Sent: Thursday, December 11, 2008 3:23 PM
To: [email protected]
Subject: [PATCH 2/3] OMAP3 EHCI: use clock framework to program DPLL5, DPLL5_M2_CLK

For testing only, not for merging.

Use the clock framework to program DPLL5, DPLL5_M2_CLK.
---
drivers/usb/host/ehci-omap.c | 57 +++++++++++++++++++++++++++---------------

1 files changed, 36 insertions(+), 21 deletions(-)
drivers/usb/host/ehci-omap.c +0 -0
index 5252e75..2057f58 100644

drivers/usb/host/ehci-omap.c struct ehci_omap_clock_defs { · line 75

Quoted 6 lines
drivers/usb/host/ehci-omap.c +2 -0
@@ -70,6 +70,8 @@ struct ehci_omap_clock_defs {
 	struct clk	*usbhost1_48m_fck_clk;
 	struct clk	*usbtll_fck_clk;
 	struct clk	*usbtll_ick_clk;
+	struct clk	*dpll5_clk;
+	struct clk	*dpll5_m2_clk;
 };

Can we have these clocks hidden from the driver.
USB-Host understands only :
2 fclocks
1 iclock

The DPLL5 is outside the USBHOST module in the DPLL5 part.
Ideally, the clock node for say USBHOST-iclock should internally enable all the parent clocks.

Quoted 78 lines
drivers/usb/host/ehci-omap.c +34 -22
 /* Clock names as per clock framework: May change so keep as #defs */

@@ -163,28 +165,29 @@ static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 				((char *)hcd_to_ehci(hcd)) +
 					sizeof(struct ehci_hcd));
 
-	/* Start DPLL5 Programming:
-	 * Clock Framework is not doing this now:
-	 * This will be done in clock framework later
+	/*
+	 * Make sure DPLL5 is programmed for 120MHz
+	 * XXX should be done at DPLL init time
+	 * XXX dpll rates should be assigned to clk->rate at init time
+	 * XXX enable DPLL autoidle
 	 */
-	/* Enable DPLL 5 : Based on Input of 13Mhz*/
-	cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)|
-			(120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT),
-			PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
-
-	cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT,
-			PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
-
-	cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) |
-			(7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT),
-			PLL_MOD, OMAP3430ES2_CM_CLKEN2);
-
-	while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) &
-				OMAP3430ES2_ST_PERIPH2_CLK_MASK))
-		dev_dbg(hcd->self.controller,
-			"idlest2 = 0x%x\n",
-			cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
-	/* End DPLL5 programming */
+	ehci_clocks->dpll5_clk = clk_get(&dev->dev, "dpll5_ck");
+	if (IS_ERR(ehci_clocks->dpll5_clk)) {
+		WARN_ON(1);
+		return PTR_ERR(ehci_clocks->dpll5_clk);
+	};
+	if (clk_get_rate(ehci_clocks->dpll5_clk) != 120000000)
+		clk_set_rate(ehci_clocks->dpll5_clk, 120000000);
+	clk_enable(ehci_clocks->dpll5_clk);
+
+	/* Program dpll5_m2_clk divider for no division */
+	ehci_clocks->dpll5_m2_clk = clk_get(&dev->dev, "dpll5_m2_ck");
+	if (IS_ERR(ehci_clocks->dpll5_m2_clk)) {
+		WARN_ON(1);
+		return PTR_ERR(ehci_clocks->dpll5_m2_clk);
+	};
+	clk_enable(ehci_clocks->dpll5_m2_clk);
+	clk_set_rate(ehci_clocks->dpll5_m2_clk, 120000000);
 
 	/* Enable Clocks for USBHOST */
 	ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,

@@ -375,6 +378,18 @@ static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 		ehci_clocks->usbtll_ick_clk = NULL;
 	}
 
+	if (ehci_clocks->dpll5_m2_clk != NULL) {
+		clk_disable(ehci_clocks->dpll5_m2_clk);
+		clk_put(ehci_clocks->dpll5_m2_clk);
+		ehci_clocks->dpll5_m2_clk = NULL;
+	}
+
+	if (ehci_clocks->dpll5_clk != NULL) {
+		clk_disable(ehci_clocks->dpll5_clk);
+		clk_put(ehci_clocks->dpll5_clk);
+		ehci_clocks->dpll5_clk = NULL;
+	}
+
 
 #ifdef EXTERNAL_PHY_RESET
 	gpio_free(EXT_PHY_RESET_GPIO_PORT1);
 
 
--

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author maintainer
#4 lore raw

RE: [PATCH 2/3] OMAP3 EHCI: use clock framework to program DPLL5, DPLL5_M2_CLK

Quoted 7 lines · Vikram

Can we have these clocks hidden from the driver.
USB-Host understands only :
2 fclocks
1 iclock

The DPLL5 is outside the USBHOST module in the DPLL5 part.
Ideally, the clock node for say USBHOST-iclock should internally enable all the parent clocks.

Yes, I agree, this patch is just for testing.

- Paul

author maintainer
#5 lore raw

PATCH 3/3 OMAP3 clock: Add debugging in omap3_noncore_dpll_enable()

In reply to Paul Walmsley

For testing only, not for merging.

Add some debugging in omap3_noncore_dpll_enable() to try to figure out what is wrong with ehci-omap.c.

---
 arch/arm/mach-omap2/clock34xx.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/clock34xx.c +4 -0
index 2c655be..9f7c5bf 100644
@@ -275,6 +275,10 @@ static int omap3_noncore_dpll_enable(struct clk *clk)
 	if (!dd)
 		return -EINVAL;
 
+	pr_info("clock: %s: clk->rate = %ld, hdwr rate = %d, parent "
+		"rate = %ld\n", clk->name, clk->rate,
+		omap2_get_dpll_rate(clk), dd->bypass_clk->rate);
+
 	if (clk->rate == dd->bypass_clk->rate)
 		r = _omap3_noncore_dpll_bypass(clk);
 	else