Few patches for galak/powerpc.git next
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cover Few patches for galak/powerpc.git next
Kumar, Timur,
Much thanks for the reviews and comments, here is an updated patch set.
Changes:
- BCSR GPIO bindings were split into a separate patch.
- simple_gpiochip_init() return value changed to void (the function prints errors by itself, and we don't check its return value anyway).
p.s.
Quoted 5 lines
Quoted 2 lines
+- reg : Should contain the address and the lenght of the GPIO bank + register;spelling - length
semicolon at add of register can be dropped.
Umm.. the semicolon denotes the end of the list item. Anyhow, I see that periods are used more widely, so I replaced semicolons with periods.
Signature · 3 lines
Anton Vorontsov email: [email protected] irc://irc.freenode.net/bd2
PATCH 1/4 powerpc: Add device tree bindings for BCSR GPIO banks
The patch adds bindings for BCSR GPIO banks, the bindings are used to describe particular BCSR registers that act as simple GPIO controllers. These GPIO banks might control power switches, SPI chip-selects, LEDs, etc.
While at it, also fix "length" spelling error in the PIXIS FPGA bindings.
--- Documentation/powerpc/dts-bindings/fsl/board.txt | 32 +++++++++++++++++++++- 1 files changed, 31 insertions(+), 1 deletions(-)
Documentation/powerpc/dts-bindings/fsl/board.txt +31 -1
@@ -18,7 +18,7 @@ This is the memory-mapped registers for on board FPGA. Required properities: - compatible : should be "fsl,fpga-pixis". -- reg : should contain the address and the lenght of the FPPGA register +- reg : should contain the address and the length of the FPPGA register set. Example (MPC8610HPCD):
@@ -27,3 +27,33 @@ Example (MPC8610HPCD): compatible = "fsl,fpga-pixis"; reg = <0xe8000000 32>; }; + +* Freescale BCSR GPIO banks + +Some BCSR registers act as simple GPIO controllers, each such +register can be represented by the gpio-controller node. + +Required properities: +- compatible : Should be "fsl,<board>-bcsr-gpio". +- reg : Should contain the address and the length of the GPIO bank + register. +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional paramters (currently unused). +- gpio-controller : Marks the port as GPIO controller. + +Example: + + bcsr@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8360mds-bcsr"; + reg = <1 0 0x8000>; + ranges = <0 1 0 0x8000>; + + bcsr13: gpio-controller@d { + #gpio-cells = <2>; + compatible = "fsl,mpc8360mds-bcsr-gpio"; + reg = <0xd 1>; + gpio-controller; + }; + };
Signature · 1 line
1.5.6.5
PATCH 2/4 powerpc: Implement GPIO driver for simple memory-mapped banks
In reply to Anton VorontsovThe driver supports very simple GPIO controllers, that is, when a controller provides just a 'data' register. Such controllers may be found in various BCSRs (Board's FPGAs used to control board's switches, LEDs, chip-selects, Ethernet/USB PHY power, etc).
So far we support only 1-byte GPIO banks. Support for other widths may be implemented when/if needed.
p.s.
To avoid "made up" compatible entries (like compatible = "simple-gpio"), boards must call simple_gpiochip_init() to pass the compatible string.
--- arch/powerpc/platforms/Kconfig | 11 +++ arch/powerpc/sysdev/Makefile | 1 + arch/powerpc/sysdev/simple_gpio.c | 155 +++++++++++++++++++++++++++++++++++++ arch/powerpc/sysdev/simple_gpio.h | 12 +++ 4 files changed, 179 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/sysdev/simple_gpio.c create mode 100644 arch/powerpc/sysdev/simple_gpio.h
arch/powerpc/platforms/Kconfig +11 -0
@@ -312,4 +312,15 @@ config MPC8xxx_GPIO Say Y here if you're going to use hardware that connects to the MPC831x/834x/837x/8572/8610 GPIOs. +config SIMPLE_GPIO + bool "Support for simple, memory-mapped GPIO controllers" + depends on PPC + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Say Y here to support simple, memory-mapped GPIO controllers. + These are usually BCSRs used to control board's switches, LEDs, + chip-selects, Ethernet/USB PHY's power and various other small + on-board peripherals. + endmenu
arch/powerpc/sysdev/Makefile +1 -0
@@ -17,6 +17,7 @@ obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y) obj-$(CONFIG_FSL_LBC) += fsl_lbc.o obj-$(CONFIG_FSL_GTM) += fsl_gtm.o obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o +obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o obj-$(CONFIG_RAPIDIO) += fsl_rio.o obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
arch/powerpc/sysdev/simple_gpio.c new file +155 -0
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arch/powerpc/sysdev/simple_gpio.h new file +12 -0
@@ -0,0 +1,12 @@ +#ifndef __SYSDEV_SIMPLE_GPIO_H +#define __SYSDEV_SIMPLE_GPIO_H + +#include <linux/errno.h> + +#ifdef CONFIG_SIMPLE_GPIO +extern void simple_gpiochip_init (const char *compatible); +#else +static inline void simple_gpiochip_init (const char *compatible) {} +#endif /* CONFIG_SIMPLE_GPIO */ + +#endif /* __SYSDEV_SIMPLE_GPIO_H */
Signature · 1 line
1.5.6.5
PATCH 3/4 powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards
In reply to Anton Vorontsov- Update the device tree per QE USB bindings;
- Add timer (FSL GTM) node;
- Add gpio-controller node for BCSR13 bank (GPIOs on that bank are used to control the USB transceiver);
- Set up other BCSR registers;
- Configure the QE Par IO.
The work is loosely based on Li Yang's patch[1], which was used to support peripheral mode only.
[1] http://ozlabs.org/pipermail/linuxppc-dev/2008-August/061357.html
The s-o-b line of the original patch preserved here.
--- arch/powerpc/boot/dts/mpc836x_mds.dts | 43 ++++++++++++++++- arch/powerpc/platforms/83xx/mpc836x_mds.c | 75 +++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 2 deletions(-)
arch/powerpc/boot/dts/mpc836x_mds.dts +41 -2
@@ -69,8 +69,18 @@ }; bcsr@1,0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,mpc8360mds-bcsr"; reg = <1 0 0x8000>; + ranges = <0 1 0 0x8000>; + + bcsr13: gpio-controller@d { + #gpio-cells = <2>; + compatible = "fsl,mpc8360mds-bcsr-gpio"; + reg = <0xd 1>; + gpio-controller; + }; }; };
@@ -195,10 +205,21 @@ }; par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; reg = <0x1400 0x100>; + ranges = <0 0x1400 0x100>; device_type = "par_io"; num-ports = <7>; + qe_pio_b: gpio-controller@18 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x18 0x18>; + gpio-controller; + }; + pio1: ucc_pin@01 { pio-map = < /* port pin dir open_drain assignment has_irq */
@@ -282,6 +303,15 @@ }; }; + timer@440 { + compatible = "fsl,mpc8360-qe-gtm", + "fsl,qe-gtm", "fsl,gtm"; + reg = <0x440 0x40>; + clock-frequency = <132000000>; + interrupts = <12 13 14 15>; + interrupt-parent = <&qeic>; + }; + spi@4c0 { cell-index = <0>; compatible = "fsl,spi";
@@ -301,11 +331,20 @@ }; usb@6c0 { - compatible = "qe_udc"; + compatible = "fsl,mpc8360-qe-usb", + "fsl,mpc8323-qe-usb"; reg = <0x6c0 0x40 0x8b00 0x100>; interrupts = <11>; interrupt-parent = <&qeic>; - mode = "slave"; + fsl,fullspeed-clock = "clk21"; + fsl,lowspeed-clock = "brg9"; + gpios = <&qe_pio_b 2 0 /* USBOE */ + &qe_pio_b 3 0 /* USBTP */ + &qe_pio_b 8 0 /* USBTN */ + &qe_pio_b 9 0 /* USBRP */ + &qe_pio_b 11 0 /* USBRN */ + &bcsr13 5 0 /* SPEED */ + &bcsr13 4 1>; /* POWER */ }; enet0: ucc@2000 {
arch/powerpc/platforms/83xx/mpc836x_mds.c +75 -0
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Signature · 1 line
1.5.6.5
PATCH 4/4 powerpc/83xx: Add USB Host support for MPC8360E-RDK boards
In reply to Anton VorontsovSimply add the usb node to support USB host on the MPC8360E-RDK boards.
Currently U-Boot doesn't fill the clock-frequency property for timer nodes, so for now we have to fill it manually.
--- arch/powerpc/boot/dts/mpc836x_rdk.dts | 19 +++++++++++++++++-- 1 files changed, 17 insertions(+), 2 deletions(-)
arch/powerpc/boot/dts/mpc836x_rdk.dts +17 -2
@@ -218,8 +218,23 @@ reg = <0x440 0x40>; interrupts = <12 13 14 15>; interrupt-parent = <&qeic>; - /* filled by u-boot */ - clock-frequency = <0>; + clock-frequency = <166666666>; + }; + + usb@6c0 { + compatible = "fsl,mpc8360-qe-usb", + "fsl,mpc8323-qe-usb"; + reg = <0x6c0 0x40 0x8b00 0x100>; + interrupts = <11>; + interrupt-parent = <&qeic>; + fsl,fullspeed-clock = "clk21"; + gpios = <&qe_pio_b 2 0 /* USBOE */ + &qe_pio_b 3 0 /* USBTP */ + &qe_pio_b 8 0 /* USBTN */ + &qe_pio_b 9 0 /* USBRP */ + &qe_pio_b 11 0 /* USBRN */ + &qe_pio_e 20 0 /* SPEED */ + &qe_pio_e 21 1 /* POWER */>; }; spi@4c0 {
Signature · 1 line
1.5.6.5
Quoted 13 lines · Anton Vorontsov
Kumar, Timur,
Much thanks for the reviews and comments, here is an updated patch set.
Changes:
- BCSR GPIO bindings were split into a separate patch.
-simple_gpiochip_init()return value changed to void (the function prints errors by itself, and we don't check its return value anyway).p.s.
Quoted 3 lines
Quoted 2 lines
+- reg : Should contain the address and the lenght of the GPIO bank + register;
Quoted 7 lines
Quoted 2 lines
spelling - length
semicolon at add of register can be dropped.Umm.. the semicolon denotes the end of the list item. Anyhow, I see that periods are used more widely, so I replaced semicolons with periods.
all applied
- k