U-Boot Firetux board support (PNX8181)

 cpu/arm926ejs/pnx8181/Makefile     |   45 +++
 cpu/arm926ejs/pnx8181/timer.c      |  141 ++++++++
 drivers/i2c/Makefile               |    1 +
 drivers/i2c/pnx8181_i2c.c          |  304 +++++++++++++++++

cpu/arm926ejs/pnx8181/Makefile new file +45 -0

new file mode 100644
index 0000000..b34d9e8
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm926ejs/pnx8181/timer.c new file +38 -0

new file mode 100644
index 0000000..585aede
@@ -0,0 +1,141 @@
+/*
+ * pnx8181 SOC timer routines
+ *
+ * (C) Copyright 2007-2009, emlix GmbH, Germany
+ * Juergen Schoew <[email protected]>
+ *
+ * (C) Copyright 2008, DSPG Technologies GmbH, Germany
+ * (C) Copyright 2007, NXP Semiconductors Germany GmbH
+ * Matthias Wenzel, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/*
+ * timer without interrupts
+ */
+/* timer */
+#define PNX8181_SCTU1_BASE	0xC2102000
+#define PNX8181_SCTU2_BASE	0xC2103000

cpu/arm926ejs/pnx8181/timer.c new file +93 -0

+
+/*
+ * U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ
+ * Keep total timer count to avoid losing decrements < div_timer
+ */
+
+/* U-Boot ticks since startup */
+static ulong timestamp;
+static ulong last_timer_read;
+
+/*
+ * starts up a counter
+ */
+void timer_init(void)
+{
+	/* set prescaler to have timer run at 64 kHz */
+	writeb(0x00, (void *)(PNX8181_SCTU1_BASE + PNX8181_SCTU_TIMxPR));
+
+	/* timer reload value = 0xffff - 13824, overflow @ 1kHz */
+	writew(0xca00, (void *)(PNX8181_SCTU1_BASE + PNX8181_SCTU_TIMxRR));
+
+	/* timer has no interrupt, run */
+	writew(0x0001, (void *)(PNX8181_SCTU1_BASE + PNX8181_SCTU_TIMxCR));
+
+	/* init the timestamp */
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base_ticks)
+{
+	return get_timer_masked() - base_ticks;
+}
+
+/*
+ * converts the timer reading to U-Boot ticks
+ * the timestamp is the number of ticks since reset
+ */
+ulong get_timer_masked(void)
+{
+	/* get current count */
+	ulong now = readw((void *)(PNX8181_SCTU1_BASE + PNX8181_SCTU_TIMxWR));
+
+	if (now < last_timer_read)
+		timestamp += 13824;
+	last_timer_read = now;
+
+	/*
+	 * FIXME	this value is empirical!
+	 *		for some reason the calculated values are way to fast
+	 */
+	return (timestamp + now) / 64;
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+
+/* busy-loop spin-delay */
+void sdelay(unsigned long usec)
+{
+	ulong i, tmp;
+	tmp = 42;
+	for (i = 0 ; i < usec*3 ; i++)
+		/* avoid compiler optimisation */
+		tmp = -tmp;
+}
+
+/* delay usec useconds */
+void udelay(unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* Convert to U-Boot ticks */
+	tmo  = usec / 1500;
+
+	tmp  = get_timer_masked();	/* get current timestamp */
+	tmo += tmp;			/* form target timestamp */
+
+	/* loop till event */
+	while (get_timer_masked() < tmo)
+		;
+}
+
+void reset_timer_masked(void)
+{
+	/* start "advancing" time stamp from 0 */
+	timestamp = 0L;
+}

drivers/i2c/Makefile +0 -0

index 6079c05..ef457a5 100644

drivers/i2c/Makefile +0 -0

 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)

drivers/i2c/pnx8181_i2c.c new file +24 -0

new file mode 100644
index 0000000..75a76a4
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2008-2009, emlix GmbH, Germany
+ * Juergen Schoew <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+

drivers/i2c/pnx8181_i2c.c new file +17 -0

+
+#define SCON_BASE_ADDR		(ARM_VPB3_BASE_ADDR + (4<<ARM_VPB_SIZE_SHIFT))
+#define SCON_BASE		SCON_BASE_ADDR
+#define SCON_SYSMUX1_OFFSET	(0x010)
+#define SCON_SYSMUX1_REG	(void *)(SCON_BASE + SCON_SYSMUX1_OFFSET)
+#define SCON_GPIOA27_MUX_SHIFT	22
+#define SCON_GPIOA27_MUX_FIELD	(0xFFFFFFFF-(3<<SCON_GPIOA27_MUX_SHIFT))
+#define SCON_GPIOA27_SCL	(1<<SCON_GPIOA27_MUX_SHIFT)
+#define SCON_GPIOA28_MUX_SHIFT	24
+#define SCON_GPIOA28_MUX_FIELD	(0xFFFFFFFF-(3<<SCON_GPIOA28_MUX_SHIFT))
+#define SCON_GPIOA28_SDA	(1<<SCON_GPIOA28_MUX_SHIFT)
+
+#define CGU_BASE_ADDR		(ARM_VPB3_BASE_ADDR + (0<<ARM_VPB_SIZE_SHIFT))
+#define CGU_BASE		(CGU_BASE_ADDR)
+#define CGU_GATESC_OFFSET	(0x008)
+#define CGU_GATESC_REG		(void *)(CGU_BASE + CGU_GATESC_OFFSET)
+#define CGU_I2C1EN		0x00000020

Quoted 5 lines · J?rgen Sch?w

 cpu/arm926ejs/pnx8181/Makefile     |   45 +++
 cpu/arm926ejs/pnx8181/timer.c      |  141 ++++++++
 drivers/i2c/Makefile               |    1 +
 drivers/i2c/pnx8181_i2c.c          |  304 +++++++++++++++++

cpu/arm926ejs/pnx8181/timer.c line 48

Quoted 13 lines

(quoted diff) +0 -0

b/cpu/arm926ejs/pnx8181/timer.c new file mode 100644 index 0000000..585aede

cpu/arm926ejs/pnx8181/timer.c new file +8 -0

+#define PNX8181_SCTU_TIMxRR	0x04
+#define PNX8181_SCTU_TIMxWR	0x08
+#define PNX8181_SCTU_TIMxC0	0x0c
+#define PNX8181_SCTU_TIMxC1	0x10
+#define PNX8181_SCTU_TIMxC2	0x14
+#define PNX8181_SCTU_TIMxC3	0x18
+#define PNX8181_SCTU_TIMxSR	0x1c
+#define PNX8181_SCTU_TIMxPR	0x20

please moce this to a header

Quoted 9 lines

drivers/i2c/Makefile +0 -0

index 6079c05..ef457a5 100644
@@ -31,6 +31,7 @@ COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) +=

omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
+COBJS-$(CONFIG_PNX8181_I2C) += pnx8181_i2c.o

please keep list sorted

drivers/i2c/pnx8181_i2c.c line 3

Quoted 9 lines

drivers/i2c/pnx8181_i2c.c new file +3 -0

new file mode 100644
index 0000000..75a76a4
@@ -0,0 +1,304 @@
+#define ARM_VPB1_BASE_ADDR	0xC2000000
+#define ARM_VPB3_BASE_ADDR	0xC2200000
+#define ARM_VPB_SIZE_SHIFT	12

please move define to a header

Quoted 1 line

drivers/i2c/pnx8181_i2c.c new file +1 -0

+

drivers/i2c/pnx8181_i2c.c line 61

Quoted 1 line

drivers/i2c/pnx8181_i2c.c new file +1 -0

+#define I2C_ADR_REG             (void *)(I2C_BASE + I2C_ADR_OFFSET)

		      ^^^^^^^^^^^^^

whitespace please fix

drivers/i2c/pnx8181_i2c.c line 62

Quoted 1 line

drivers/i2c/pnx8181_i2c.c new file +1 -0

+#define I2C_SADDR_FIELD         0xFFFFFF80

		          ^^^^^^^^^

whitespace please fix
and other in the code please fix

Quoted 9 lines · J?rgen Sch?w

 drivers/net/Makefile               |    1 +
 drivers/net/ip3912.c               |  659 ++++++++++++++++++++++++++++++++++++
 drivers/net/ip3912.h               |  174 ++++++++++

drivers/net/Makefile +0 -0

index 631336a..7c82880 100644

drivers/net/Makefile COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o · line 73

Quoted 5 lines

drivers/net/Makefile +1 -0

@@ -69,6 +69,7 @@ COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
 COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
 COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
+COBJS-$(CONFIG_IP3912_ETHER) += ip3912.o
 

please keep list sorted

Ben could you take a look please

Best Regards,
J.

Quoted 5 lines

 drivers/net/Makefile               |    1 +
 drivers/net/ip3912.c               |  659

++++++++++++++++++++++++++++++++++++
drivers/net/ip3912.h | 174 ++++++++++

drivers/net/Makefile COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o · line 72

Quoted 9 lines

drivers/net/Makefile +1 -0

index 631336a..7c82880 100644
@@ -69,6 +69,7 @@ COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
 COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
 COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
+COBJS-$(CONFIG_IP3912_ETHER) += ip3912.o

please keep list sorted

Ben could you take a look please

 drivers/net/Makefile               |    1 +
 drivers/net/ip3912.c               |  659 ++++++++++++++++++++++++++++++++++++
 drivers/net/ip3912.h               |  174 ++++++++++

drivers/net/Makefile +0 -0

index 631336a..7c82880 100644

drivers/net/Makefile +0 -0

 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)

drivers/net/ip3912.c new file +44 -0

new file mode 100644
index 0000000..399f0b7
@@ -0,0 +1,659 @@
+/*
+ * ip3912 ethernet driver (PNX8181 / firetux)
+ *
+ * (C) Copyright 2007-2009, emlix GmbH, Germany
+ * Juergen Schoew <[email protected]>
+ *
+ * (C) Copyright 2008, DSPG Technologies GmbH, Germany
+ * (C) Copyright 2007, NXP Semiconductors Germany GmbH
+ * Matthias Wenzel, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include <asm/io.h>
+
+#include "ip3912.h"
+#include <miiphy.h>
+
+#define ALIGN8	__attribute__ ((aligned(8)))
+#define ALIGN4	__attribute__ ((aligned(4)))
+
+/* globals */
+/* ETN rx */
+ALIGN8 rx_descriptor_t	etn_rxdescriptor[CONFIG_SYS_ETN_RX_DESCRIPTOR_NUMBER];

drivers/net/ip3912.c new file +17 -0

+	unsigned char		phy_addr;
+	unsigned char		autonegotiate;
+	unsigned char		speed;
+	unsigned char		duplex;
+	unsigned char		rmii;
+
+	const struct device	*dev;
+	struct eth_device	*netdev;
+};
+
+int ip3912_miiphy_write(char *devname, unsigned char addr,
+				unsigned char reg, unsigned short value)
+{
+	int status = 1;
+	int i = 0;
+	struct eth_device *netdev;
+	struct ip3912_device *ip3912;

drivers/net/ip3912.c new file +58 -0

+		return -1;
+	} else {
+		debug("### ip3912_miiphy_write(%2.d, 0x%4.4x) success after"
+			" %d cycles [phy_addr=%x]###\n", reg, value, i, addr);
+	}
+
+	return 0;
+}
+
+int ip3912_miiphy_read(char *devname, unsigned char addr,
+				unsigned char reg, unsigned short *value)
+{
+	int i = 0, status = 1;
+	struct eth_device *netdev;
+	struct ip3912_device *ip3912;
+
+	netdev = eth_get_dev();
+	ip3912 = netdev->priv;
+
+	reg &= 0x001f; /* 5 bit PHY register address */
+	writel(PHYADDR_TO_REG(addr) | reg, (void *)(ip3912->phy_base
+								+ ETN_MADR));
+	writel(0x00000001, (void *)(ip3912->phy_base + ETN_MCMD));
+
+	/* poll for done, max 100ms */
+	while (status && i < 100000) {
+		status = readl((void *)(ip3912->phy_base + ETN_MIND)) & 0x7;
+		udelay(1);
+		i++;
+	}
+
+	*value = (unsigned short)readl((void *)(ip3912->phy_base + ETN_MRDD));
+
+	writel(0, (void *)(ip3912->phy_base + ETN_MCMD));	/* stop MII */
+
+	if (status) {
+		printf("ERROR: ip3912_miiphy_read(%d) = 0x%x after %d cycles "
+			"[phy_addr=%x]\n", reg, *value, i, ip3912->phy_addr);
+		return -1;
+	} else {
+		debug("### ip3912_phy_read(%2.d)=0x%4.4x success after %d "
+					"cycles [phy_addr=%x]###\n",
+				reg, *value, i, ip3912->phy_addr);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+int ip3912_mii_negotiate_phy(void)
+{
+	char *mode;
+	int i;
+	unsigned short value;
+	struct eth_device *netdev;
+	struct ip3912_device *ip3912;
+
+	netdev = eth_get_dev();

drivers/net/ip3912.c new file +20 -0

+	if (mode  != NULL) {
+		if (0 == strcmp(mode, "auto")) {
+			ip3912->autonegotiate = 1;
+			ip3912->speed = 100;
+			ip3912->duplex = 1;
+		} else {
+			if (0 == strcmp(mode, "100FD")) {
+				ip3912->speed = 100;
+				ip3912->duplex = 1;
+			}
+			if (0 == strcmp(mode, "100HD")) {
+				ip3912->speed = 100;
+				ip3912->duplex = 0;
+			}
+			if (0 == strcmp(mode, "10FD")) {
+				ip3912->speed = 10;
+				ip3912->duplex = 1;
+			}
+			if (0 == strcmp(mode, "10HD")) {
+				ip3912->speed = 10;

drivers/net/ip3912.c new file +11 -0

+
+	/* do autonegotiation */
+	if (ip3912->autonegotiate) {
+		/* 10/100 and FD/HD mode supported, ieee802.3 */
+		ip3912_miiphy_write(netdev->name, ip3912->phy_addr,
+				ETN_PHY_AUTONEG_ADV, ((0xf << 5) | 1));
+		/* force autorenegotiation */
+		ip3912_miiphy_write(netdev->name, ip3912->phy_addr,
+				ETN_PHY_BASIC_CONTROL, ((1 << 13) | (1 << 12) |
+							 (1 << 9) | (1 << 8)));
+	} else {

drivers/net/ip3912.c new file +28 -0

+		/* set advertise mode */
+		ip3912_miiphy_write(netdev->name, ip3912->phy_addr,
+						ETN_PHY_AUTONEG_ADV, (i|1));
+		/* we set the phy parameter */
+		ip3912_miiphy_write(netdev->name, ip3912->phy_addr,
+			ETN_PHY_BASIC_CONTROL, ((ip3912->duplex ? (1<<8) : 0)
+			| (1 << 9) | ((ip3912->speed == 100) ? (1 << 13) : 0)));
+	}
+
+	/* wait for negotiation finished (max 3.5s) */
+	i = 0;
+	ip3912_miiphy_read(netdev->name, ip3912->phy_addr, ETN_PHY_BASIC_STATUS,
+									&value);
+	while (((value & (1 << 5)) == 0) && (i < 350)) {
+		udelay(10000);
+		i++;
+		ip3912_miiphy_read(netdev->name, ip3912->phy_addr,
+						 ETN_PHY_BASIC_STATUS, &value);
+	}
+	if (i == 350)
+		puts("link negotiation timed out\n");
+
+
+	/* check for link */
+	if (value & (1 << 2)) {
+		/* OK link present */
+		ip3912_miiphy_read(netdev->name, ip3912->phy_addr,
+				ETN_PHY_SPECIAL_MODE_CONTROL_STATUS, &value);

;

drivers/net/ip3912.c new file +151 -0

+	/*
+	 * release rx-path, tx-path, host registers reset
+	 * set Duplex, enable RMII, enable rx+tx
+	 * no flow control, no frames<64b
+	 */
+	writel(0x00000283 | (ip3912->duplex ? (1 << 10) : 0),
+				(void *)(ip3912->etn_base + ETN_COMMAND));
+
+	udelay(100000);	/* the mac still needs some time to settle 100ms */
+	ip3912_miiphy_read(netdev->name, ip3912->phy_addr,
+				ETN_PHY_SPECIAL_MODE_CONTROL_STATUS, &value);
+	printf(" %s %s negotiation", netdev->name,
+				(value & (1 << 12)) ? "Auto" : "Manual");
+	printf(" (10%s Mbit", (value & (1 << 3)) ? "0" : "");
+	printf(" %sD", (value & (1 << 4)) ? "F" : "H");
+	ip3912_miiphy_read(netdev->name, ip3912->phy_addr, ETN_PHY_BASIC_STATUS,
+									&value);
+	printf(" (%s)\n", (value & 1<<2)
+			? "Link detected" : "No Link detected, trying anyway");
+
+	return 0;
+}
+
+#if defined(CONFIG_DISCOVER_PHY)
+int mii_discover_phy(void)
+{
+	unsigned short id1, id2;
+	int phytype, phyno;
+	struct eth_device *netdev;
+	struct ip3912_device *ip3912;
+
+	netdev = eth_get_dev();
+	ip3912 = netdev->priv;
+
+	for (phyno = 0; phyno <= 31 ; ++phyno) {
+		ip3912_miiphy_read(netdev->name, phyno, PHY_PHYIDR1, &id1);
+		if (id1 != 0xffff) {
+			ip3912_miiphy_read(netdev->name, phyno, PHY_PHYIDR2,
+								&id2);
+			phytype = ((id1 << 16) | id2);
+			puts("Using Transceiver: ");
+			switch (phytype & 0xfffffff0) {
+			case PHY_ID_LXT970:
+						puts("LXT970");
+						break;
+			case PHY_ID_LXT971:
+						puts("LXT971");
+						break;
+			case PHY_ID_82555:
+						puts("82555");
+						break;
+			case PHY_ID_QS6612:
+						puts("QS6612");
+						break;
+			case PHY_ID_AMD79C784:
+						puts("AMD79C784");
+						break;
+			case PHY_ID_LSI80225:
+						puts("LSI L80225");
+						break;
+			case PHY_ID_LSI80225B:
+						puts("LSI L80225/B");
+						break;
+			case PHY_ID_DM9161:
+						puts("Davicom DM9161");
+						break;
+			case PHY_ID_KSM8995M:
+						puts("MICREL KS8995M");
+						break;
+			case PHY_ID_SMSC8700:
+						puts("SMSC Lan 8700");
+						break;
+			default:
+						printf("0x%08x", phytype);
+						break;
+		}
+	    }
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DISCOVER_PHY */
+
+#endif /* defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
+
+int ip3912_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+	miiphy_register("ip3912", ip3912_miiphy_read, ip3912_miiphy_write);
+#endif
+	return 0;
+}
+
+static int ip3912_init_descriptors(struct eth_device *netdev)
+{
+	struct ip3912_device *ip3912;
+	static void *rxbuf;
+	int i;
+
+	ip3912 = netdev->priv;
+
+	/* fill in pointer in regs */
+	writel((unsigned long)etn_rxdescriptor, (void *)(ip3912->etn_base
+							+ ETN_RXDESCRIPTOR));
+	writel((unsigned long)etn_rxstatus, (void *)(ip3912->etn_base
+							+ ETN_RXSTATUS));
+	writel(0x00000000, (void *)(ip3912->etn_base + ETN_RXCONSUMEINDEX));
+	writel(CONFIG_SYS_ETN_RX_DESCRIPTOR_NUMBER - 1,
+				(void *)(ip3912->etn_base
+						+ ETN_RXDESCRIPTORNUMBER));
+
+	writel((unsigned long)etn_txdescriptor,	(void *)(ip3912->etn_base
+							+ ETN_TXDESCRIPTOR));
+	writel((unsigned long)etn_txstatus, (void *)(ip3912->etn_base
+							+ ETN_TXSTATUS));
+	writel(0x00000000, (void *)(ip3912->etn_base + ETN_TXPRODUCEINDEX));
+	writel(CONFIG_SYS_ETN_TX_DESCRIPTOR_NUMBER - 1,
+			(void *)(ip3912->etn_base + ETN_TXDESCRIPTORNUMBER));
+
+	/* allocate rx-buffers, but only once, we're called multiple times! */
+	if (!rxbuf)
+		rxbuf = malloc(MAX_ETH_FRAME_SIZE
+					* CONFIG_SYS_ETN_RX_DESCRIPTOR_NUMBER);
+	if (!rxbuf) {
+		puts("ERROR: couldn't allocate rx buffers!\n");
+		return -1;
+	}
+
+	for (i = 0; i < CONFIG_SYS_ETN_RX_DESCRIPTOR_NUMBER; i++) {
+		etn_rxdescriptor[i].packet = rxbuf + i * MAX_ETH_FRAME_SIZE;
+		etn_rxdescriptor[i].control = MAX_ETH_FRAME_SIZE
+						- sizeof(unsigned long);
+		etn_rxstatus[i].info = 0;
+		etn_rxstatus[i].hashCRC = 0;
+	}
+
+	for (i = 0; i < CONFIG_SYS_ETN_TX_DESCRIPTOR_NUMBER; i++) {
+		etn_txdescriptor[i].packet = 0;
+		etn_txdescriptor[i].control = 0;
+		etn_txstatus[i].info = 0;
+	}
+	return 0;
+}
+
+void ip3912_setmac(struct eth_device *netdev)
+{
+	struct ip3912_device *ip3912;
+	unsigned char i, use_etn1addr = 0;
+	char *mac_string, *pmac, *end;
+	char tmp[18];
+

drivers/net/ip3912.c new file +8 -0

+			use_etn1addr = 1;
+		}
+	}
+
+	pmac = mac_string;
+	for (i = 0; i < 6; i++) {
+		netdev->enetaddr[i] = pmac ? simple_strtoul(pmac, &end, 16) : 0;
+		if (pmac)

drivers/net/ip3912.c new file +180 -0

+		sprintf(tmp, "%02X:%02X:%02X:%02X:%02X:%02X",
+			 netdev->enetaddr[0], netdev->enetaddr[1],
+			 netdev->enetaddr[2], netdev->enetaddr[3],
+			 netdev->enetaddr[4], netdev->enetaddr[5]);
+		setenv("eth1addr", tmp);
+		mac_string = tmp;
+	}
+
+	debug("ip3912_setmac set %s to address %s\n", netdev->name, mac_string);
+
+	writel((netdev->enetaddr[5] << 8) | netdev->enetaddr[4],
+					(void *)(ip3912->etn_base + ETN_SA0));
+	writel((netdev->enetaddr[3] << 8) | netdev->enetaddr[2],
+					(void *)(ip3912->etn_base + ETN_SA1));
+	writel((netdev->enetaddr[1] << 8) | netdev->enetaddr[0],
+					(void *)(ip3912->etn_base + ETN_SA2));
+}
+
+int ip3912_macreset(void)
+{
+	struct eth_device *netdev;
+	struct ip3912_device *ip3912;
+
+	netdev = eth_get_dev();
+	ip3912 = netdev->priv;
+
+	debug("ip3912_macreset resetting %s\n", netdev->name);
+
+	/* reset MAC layer */
+	writel(0x0000cf00, (void *)(ip3912->etn_base + ETN_MAC1));
+	/* release MAC soft reset */
+	writel(0x00000000, (void *)(ip3912->etn_base + ETN_MAC1));
+	/* reset rx-path, tx-path, host registers */
+	writel(0x00000038, (void *)(ip3912->etn_base + ETN_COMMAND));
+	/* reset RMII, 100Mbps MAC, 10Mbps MAC */
+	writel(0x1888, (void *)(ip3912->etn_base + ETN_SUPP));
+	writel(0x1000, (void *)(ip3912->etn_base + ETN_SUPP));
+
+	return 0;
+}
+
+static int ip3912_init(struct eth_device *netdev, bd_t *bd)
+{
+	unsigned char i;
+	struct ip3912_device *ip3912 = netdev->priv;
+
+	/* update mac address in boardinfo */
+	ip3912_setmac(netdev);
+	for (i = 0; i < 6 ; i++)
+		bd->bi_enetaddr[i] = netdev->enetaddr[i];
+
+	/* before enabling the rx-path we need to set up rx-descriptors */
+	if (ip3912_init_descriptors(netdev))
+		return -1;
+
+	/* set max packet length to 1536 bytes */
+	writel(MAX_ETH_FRAME_SIZE, (void *)(ip3912->etn_base + ETN_MAXF));
+	/* full duplex */
+	writel(0x00000023, (void *)(ip3912->etn_base + ETN_MAC2));
+	/* inter packet gap register */
+	writel(0x15, (void *)(ip3912->etn_base + ETN_IPGT));
+	writel(0x12, (void *)(ip3912->etn_base + ETN_IPGR));
+	/* enable rx, receive all frames */
+	writel(0x00000003, (void *)(ip3912->etn_base + ETN_MAC1));
+	/* accept all multicast, broadcast and station packets */
+	writel(0x00000026, (void *)(ip3912->etn_base + ETN_RXFILTERCTRL));
+
+	/* reset MII mgmt, set MII clock */
+	writel(0x0000801c, (void *)(ip3912->etn_base + ETN_MCFG));
+	writel(0x0000001c, (void *)(ip3912->etn_base + ETN_MCFG));
+
+	/* release rx-path, tx-path, host registers reset
+	 * set FullDuplex, enable RMMI, enable rx+tx
+	 * no flow control, no frames<64b
+	 */
+	writel(0x00000683, (void *)(ip3912->etn_base + ETN_COMMAND));
+	ip3912_init_descriptors(netdev);
+
+#ifdef CONFIG_DISCOVER_PHY
+	mii_discover_phy();
+#endif
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+	/* check autonegotiation */
+	ip3912_mii_negotiate_phy();
+#endif
+	return 0;
+}
+
+/* Send a packet */
+static int ip3912_send(struct eth_device *netdev, volatile void *packet,
+								int length)
+{
+	struct ip3912_device *ip3912 = netdev->priv;
+	uint32_t next_packet;
+	uint32_t this_packet;
+	uint32_t last_packet;
+
+	if ((length > MAX_ETH_FRAME_SIZE) || (length <= 0)) {
+		printf("ERROR: cannot transmit a %d bytes frame!\n", length);
+		return -1;
+	}
+
+	this_packet = readl((void *)(ip3912->etn_base + ETN_TXPRODUCEINDEX));
+	next_packet = (this_packet + 1) % CONFIG_SYS_ETN_TX_DESCRIPTOR_NUMBER;
+	last_packet = readl((void *)(ip3912->etn_base + ETN_TXCONSUMEINDEX));
+
+#define ETN_TX_MAX_RETRY	1000000
+	int i = 0;
+	/* wait until the FIFO is ready to accept a new packet */
+
+	while ((this_packet == ((last_packet +
+					CONFIG_SYS_ETN_TX_DESCRIPTOR_NUMBER - 1)
+					% CONFIG_SYS_ETN_TX_DESCRIPTOR_NUMBER))
+						&& (i < ETN_TX_MAX_RETRY)) {
+#ifdef ET_DEBUG
+		/* debug print when FIFO full*/
+		if ((i > 50000) && (!(i % 50000))) {
+			this_packet =
+				readl((void *)(ip3912->etn_base
+							+ ETN_TXPRODUCEINDEX));
+			last_packet =
+				readl((void *)(ip3912->etn_base
+							+ ETN_TXCONSUMEINDEX));
+			printf("this=%3.d, last=%3.d, i=%d\n",
+						this_packet, last_packet, i);
+		}
+#endif
+		i++;
+		last_packet = readl((void *)(ip3912->etn_base
+							+ ETN_TXCONSUMEINDEX));
+	}
+	if (i == ETN_TX_MAX_RETRY) {
+		printf("tx FAILED after %d cycles\n", i);
+		return -1;
+	}
+	if (i)
+		printf("tx after %d cycles\n", i);
+
+	etn_txdescriptor[this_packet].packet  = packet;
+	etn_txdescriptor[this_packet].control = (length - 1) |
+		ETN_CONTROL_INTERRUPT | ETN_CONTROL_LAST;
+
+	/* let the HW know a new packet is ready */
+	writel(next_packet, (void *)(ip3912->etn_base + ETN_TXPRODUCEINDEX));
+
+	return 0;
+}
+
+/* Check for received packets */
+static int ip3912_recv(struct eth_device *netdev)
+{
+	struct ip3912_device *ip3912 = netdev->priv;
+
+	unsigned short rxconsume = (unsigned short)
+		(readl((void *)(ip3912->etn_base + ETN_RXCONSUMEINDEX)));
+	unsigned short rxproduce = (unsigned short)
+		(readl((void *)(ip3912->etn_base + ETN_RXPRODUCEINDEX)));
+	unsigned short psize = 0;
+
+	debug("eth_rx: receive_rsv 0x%08x\n",
+				readl((void *)(ip3912->etn_base + ETN_RSV)));
+	debug("eth_rx: consume 0x%04x produce 0x%04x\n",
+							rxconsume, rxproduce);
+	while (rxconsume != rxproduce) {
+		rxproduce = (unsigned short)(readl((void *)
+				(ip3912->etn_base + ETN_RXPRODUCEINDEX)));
+		psize = (etn_rxstatus[rxconsume].info & 0x07ff) + 1;
+		if (psize > MAX_ETH_FRAME_SIZE) {
+			printf("dropping %d bytes frame (too large)!\n",
+									psize);
+		} else {
+			NetReceive(etn_rxdescriptor[rxconsume].packet, psize);
+		}
+		rxconsume = (rxconsume + 1)
+					% CONFIG_SYS_ETN_RX_DESCRIPTOR_NUMBER;
+		writel(rxconsume,
+			(void *)(ip3912->etn_base + ETN_RXCONSUMEINDEX));
+	}
+	return psize;
+}

drivers/net/ip3912.c new file +43 -0

+}
+
+int ip3912_eth_initialize(unsigned char nr, unsigned int etn_base,
+	unsigned int phy_base, unsigned char phy_addr, unsigned char rmii)
+{
+	struct ip3912_device *ip3912;
+	struct eth_device *netdev;
+
+	netdev = malloc(sizeof(struct eth_device));
+	ip3912 = malloc(sizeof(struct ip3912_device));
+	if ((!ip3912) || (!netdev)) {
+		printf("Error: Failed to allocate memory for ETN%d\n", nr + 1);
+		return -1;
+	}
+
+	memset(ip3912, 0, sizeof(struct ip3912_device));
+	memset(netdev, 0, sizeof(struct eth_device));
+
+	ip3912->nr = nr;
+	ip3912->etn_base = etn_base;
+	ip3912->phy_base = phy_base;
+	ip3912->phy_addr = phy_addr;
+	ip3912->autonegotiate = 0;
+	ip3912->rmii = rmii;
+	ip3912->speed = 0;
+	ip3912->duplex = 0;
+	ip3912->netdev = netdev;
+
+	sprintf(netdev->name, "ETN%d", nr + 1);
+	netdev->init = ip3912_init;
+	netdev->send = ip3912_send;
+	netdev->recv = ip3912_recv;
+	netdev->halt = ip3912_halt;
+	netdev->priv = (void *)ip3912;
+
+
+	eth_register(netdev);
+	ip3912_macreset();
+	/* we have to set the mac address, because we have no SROM */
+	ip3912_setmac(netdev);
+
+	return 0;
+}

drivers/net/ip3912.h new file +164 -0

new file mode 100644
index 0000000..f6343a0
@@ -0,0 +1,174 @@
+/*
+ * ip3912 ethernet driver interface (PNX8181 / firetux)
+ *
+ * (C) Copyright 2007-2009, emlix GmbH, Germany
+ * Juergen Schoew <[email protected]>
+ *
+ * (C) Copyright 2008, DSPG Technologies GmbH, Germany
+ * (C) Copyright 2007, NXP Semiconductors Germany GmbH
+ * Matthias Wenzel, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* exported ethernet functions */
+int mii_discover_phy(void);
+
+#define PHYADDR_TO_REG(x)			(x << 8)
+
+/* data types */
+
+/* rx */
+typedef struct{
+	volatile void *packet;
+	volatile unsigned long control;
+} rx_descriptor_t;
+
+typedef struct{
+	volatile unsigned long info;		/* RO */
+	volatile unsigned long hashCRC;		/* RO */
+} rx_status_t;
+
+/* tx */
+typedef struct{
+	volatile void *packet;
+	volatile unsigned long control;
+} tx_descriptor_t;
+
+typedef struct{
+	volatile unsigned long info;		/* RO */
+} tx_status_t;
+
+/* NXP's OUI registered @ IEEE  */
+#define NXP_ETN_OUI			0x006037
+
+/* ip3912 ETN registers */
+#define ETN1_BASE			CONFIG_IP3912_ETN1_BASE
+#define ETN2_BASE			CONFIG_IP3912_ETN2_BASE
+
+/* offsets to base address */
+#define ETN_MAC1			0x0000
+#define ETN_MAC2			0x0004
+#define ETN_IPGT			0x0008
+#define ETN_IPGR			0x000c
+#define ETN_CLRT			0x0010
+#define ETN_MAXF			0x0014
+#define ETN_SUPP			0x0018
+#define ETN_TEST			0x001c
+#define ETN_MCFG			0x0020
+#define ETN_MCMD			0x0024
+#define ETN_MADR			0x0028
+#define ETN_MWTD			0x002c
+#define ETN_MRDD			0x0030
+#define ETN_MIND			0x0034
+#define ETN_SA0				0x0040
+#define ETN_SA1				0x0044
+#define ETN_SA2				0x0048
+#define ETN_COMMAND			0x0100
+#define ETN_STATUS			0x0104
+#define ETN_RXDESCRIPTOR		0x0108
+#define ETN_RXSTATUS			0x010c
+#define ETN_RXDESCRIPTORNUMBER		0x0110
+#define ETN_RXPRODUCEINDEX		0x0114
+#define ETN_RXCONSUMEINDEX		0x0118
+#define ETN_TXDESCRIPTOR		0x011c
+#define ETN_TXSTATUS			0x0120
+#define ETN_TXDESCRIPTORNUMBER		0x0124
+#define ETN_TXPRODUCEINDEX		0x0128
+#define ETN_TXCONSUMEINDEX		0x012c
+#define ETN_TXRTDESCRIPTOR		0x0130
+#define ETN_TXRTSTATUS			0x0134
+#define ETN_TXRTDESCRIPTORNUMBER	0x0138
+#define ETN_TXRTPRODUCEINDEX		0x013c
+#define ETN_TXRTCONSUMEINDEX		0x0140
+#define ETN_QOSTIMEOUT			0x0148
+#define ETN_TSV0			0x0158
+#define ETN_TSV1			0x015c
+#define ETN_RSV				0x0160
+#define ETN_FLOWCONTROLCOUNTER		0x0170
+#define ETN_FLOWCONTROLSTATUS		0x0174
+#define ETN_RXFILTERCTRL		0x0200
+#define ETN_RXFILTERWOLSTATUS		0x0204
+#define ETN_RXFILTERWOLCLEAR		0x0208
+#define ETN_HASHFILTERL			0x0210
+#define ETN_HASHFILTERH			0x0214
+#define ETN_INTSTATUS			0x0fe0
+#define ETN_INTENABLE			0x0fe4
+#define ETN_INTCLEAR			0x0fe8
+#define ETN_INTSET			0x0fec
+#define ETN_POWERDOWN			0x0ff4
+#define ETN_MODULEID			0x0ffc
+
+/* values for control */
+#define ETN_CONTROL_INTERRUPT	0x80000000
+#define ETN_CONTROL_LAST	0x40000000
+#define ETN_CONTROL_CRC		0x20000000
+#define ETN_CONTROL_PAD		0x10000000
+#define ETN_CONTROL_HUGE	0x08000000
+#define ETN_CONTROL_OVERRIDE	0x04000000
+
+/* registers in the SMSC LAN8700 PHY */
+/*
+00 Basic Control Register				Basic
+01 Basic Status Register				Basic
+02 PHY Identifier 1					Extended
+03 PHY Identifier 2					Extended
+04 Auto-Negotiation Advertisement Register		Extended
+05 Auto-Negotiation Link Partner Ability Register	Extended
+06 Auto-Negotiation Expansion Register			Extended
+16 Silicon Revision Register				Vendor-specific
+17 Mode Control/Status Register				Vendor-specific
+18 Special Modes					Vendor-specific
+20 Reserved						Vendor-specific
+21 Reserved						Vendor-specific
+22 Reserved						Vendor-specific
+23 Reserved						Vendor-specific
+27 Control / Status Indication Register			Vendor-specific
+28 Special internal testability controls		Vendor-specific
+29 Interrupt Source Register				Vendor-specific
+30 Interrupt Mask Register				Vendor-specific
+31 PHY Special Control/Status Register			Vendor-specific
+*/
+#define ETN_PHY_BASIC_CONTROL			0x00
+#define ETN_PHY_BASIC_STATUS			0x01
+#define ETN_PHY_ID1				0x02
+#define ETN_PHY_ID2				0x03
+#define ETN_PHY_AUTONEG_ADV			0x04
+#define ETN_PHY_AUTONEG_LINK			0x05
+#define ETN_PHY_AUTONEG_EXP			0x06
+#define ETN_PHY_SILICON				0x10
+#define ETN_PHY_MODE_CONTROL_STATUS		0x11
+#define ETN_PHY_SPECIAL_MODES			0x12
+#define ETN_PHY_CONTROL_STATUS_INDICATION	0x1b
+#define ETN_PHY_INTERNAL_TESTABILITY		0x1c
+#define ETN_PHY_INTERRUPT_SOURCE		0x1d
+#define ETN_PHY_INTERRUPT_MASK			0x1e
+#define ETN_PHY_SPECIAL_MODE_CONTROL_STATUS	0x1f
+
+/* PHY identification */

--===============0063675513==
Content-Type: multipart/signed; boundary="Sig_/p.d_N5rCt+xwh6DxRb9e5B9";
protocol="application/pgp-signature"; micalg=PGP-SHA1

--Sig_/p.d_N5rCt+xwh6DxRb9e5B9
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

 drivers/net/Makefile               |    1 +
 drivers/net/ip3912.c               |  659 ++++++++++++++++++++++++++++++++> ++++
 drivers/net/ip3912.h               |  174 ++++++++++

board/dspg/firetux/Makefile new file +4 -0

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License

board/dspg/firetux/Makefile new file +24 -0

+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/dspg/firetux/boardrevision.c new file +49 -0

new file mode 100644
index 0000000..3119090
@@ -0,0 +1,299 @@
+/*
+ * firetux board detection
+ *
+ * (C) Copyright 2007-2009, emlix GmbH, Germany
+ * Juergen Schoew <[email protected]>
+ * (C) Copyright 2008, Sebastian Hess, emlix GmbH <[email protected]>
+ *
+ * (C) Copyright 2008, DSPG Technologies GmbH, Germany
+ * (C) Copyright 2007, NXP Semiconductors Germany GmbH
+ * Matthias Wenzel, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * These VEGA boards are very similair to each other. The main difference
+ * is the phy address of the network, CPU revision, number of leds and keys.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "firetux.h"
+
+#ifndef CONFIG_IP3912_ETN1_BASE
+#define CONFIG_IP3912_ETN1_BASE		0xC1600000
+#endif
+#ifndef CONFIG_IP3912_ETN2_BASE
+#define CONFIG_IP3912_ETN2_BASE		0xC1700000
+#endif
+
+/* ip3912 / pnx8181 ETN registers */
+#define ETN1_BASE			CONFIG_IP3912_ETN1_BASE
+#define ETN2_BASE			CONFIG_IP3912_ETN2_BASE

board/dspg/firetux/boardrevision.c new file +19 -0

+
+static char firetux_boardrevision = UNKNOWN_PNX8181;
+
+char get_boardrevision(void)
+{
+	return firetux_boardrevision;
+}
+
+static void detect_etn_start(void)
+{
+	debug("board detect: initialize ETN\n");
+	/* reset MII mgmt, set MII clock */
+	writel(0x0000801c, (void *)(ETN1_BASE + ETN_MCFG));
+	writel(0x0000001c, (void *)(ETN1_BASE + ETN_MCFG));
+
+	/* enable RMMI */
+	writel(0x00000600, (void *)(ETN1_BASE + ETN_COMMAND));
+
+	/* reset MAC layer */

board/dspg/firetux/boardrevision.c new file +11 -0

+	for (i = 0; i < 1000; i++) {
+		status = readl((void *)(ETN1_BASE + ETN_MIND)) & 0x7;
+		if (!status)
+			return;
+		udelay(1);
+	}
+	debug("board detect: wait PHY timed out!\n");
+}
+
+/* write to phy */
+static void detect_phy_write(u8 address, u8 reg, u16 data)

board/dspg/firetux/boardrevision.c new file +45 -0

+	writel((address << 8) | reg, (void *)(ETN1_BASE + ETN_MADR));
+	writel(0x00000001, (void *)(ETN1_BASE + ETN_MCMD));
+	detect_phy_wait();
+
+	value = readl((void *)(ETN1_BASE + ETN_MRDD));
+	writel(0x00000000, (void *)(ETN1_BASE + ETN_MCMD));
+	return value;
+}
+
+/* do a software reset on the phy */
+static int detect_phy_softreset(u8 phyaddr)
+{
+	int i, rc;
+
+	debug("board detect: softreset PHY @0x%02x ", phyaddr);
+
+	/*
+	 *  reset power down bit and set autonegotiation in
+	 *  phy basic control register 0
+	 */
+	detect_phy_write(phyaddr, 0x00, 0x1200);
+
+	/* set reset bit in phy basic control register */
+	detect_phy_write(phyaddr, 0x00, detect_phy_read(phyaddr, 0x00)
+								| (1 << 15));
+	udelay(260); /* HW ref (pg. 51): 256us, IEEE <= 500ms */
+
+	/* Check for bit reset */
+	for (i = 0; i < 1000; i++) {
+		rc = detect_phy_read(phyaddr, 0x00);
+		if (!(rc & (1 < 11))) {
+			debug("OK\n");
+			return 0;
+		}
+	}
+
+	debug("timed out!\n");
+	return -1;
+}
+
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+

board/dspg/firetux/boardrevision.c new file +6 -0

+
+ifneq ($(OBJTREE),$(SRCTREE))
+# We are building u-boot in a separate directory, use generated
+# .lds script from OBJTREE directory.
+LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
+endif

board/dspg/firetux/firetux.c new file +47 -0

new file mode 100644
index 0000000..52f0ad1
@@ -0,0 +1,413 @@
+/*
+ * firetux board specific setup
+ *
+ * (C) Copyright 2007-2009, emlix GmbH, Germany
+ * Juergen Schoew <[email protected]>
+ *
+ * (C) Copyright 2008, DSPG Technologies GmbH, Germany
+ * (C) Copyright 2007, NXP Semiconductors Germany GmbH
+ * Matthias Wenzel, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <status_led.h>
+#include "firetux.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* functions for ethernet initialization */
+extern int ip3912_eth_initialize(unsigned char nr, unsigned int etn_base,
+	unsigned int phy_base, unsigned char phy_addr, unsigned char rmii);
+extern int ip3912_miiphy_initialize(bd_t *bis);
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif

board/dspg/firetux/firetux.c new file +177 -0

+{
+	int rc = 0;
+
+/*
+ * priority setting for ETN over CPU for SDRAM access
+ * enable port-aging with priority for ETN
+ */
+#ifdef CONFIG_SYS_ETHER_FAIR_SCHEDULE
+	/*
+	 * be fair: ETN and CPU are both high priority, but ETN gets
+	 * higher priority and a much lower ageing penatly to get
+	 * much more accesses to RAM
+	 */
+	writel(0x80000121, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED0));
+	writel(0xffff0100, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED1));
+	writel(0x00030131, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED2));
+#else
+	/*
+	 * highly prioritise the ETN engine and lower CPU priority
+	 * to archive a better network thoughput
+	 */
+	writel(0xffff0020, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED0));
+	writel(0xffff0000, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED1));
+	writel(0xffff0031, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED2));
+#endif
+
+	/* increase priority for SCRAM access at AHB of descriptors */
+	writew(7, (void *)(PNX8181_SC_ARB_BASE + PNX8181_SC_ARB_CFG2));
+	writew(7, (void *)(PNX8181_SC_ARB_BASE + PNX8181_SC_ARB_CFG3));
+
+	/*
+	 * init ETN clocks
+	 *
+	 * set ETNREFCLK to internal CGU clock, assuming a 13.824MHz crystal
+	 * for other xtals see NXP's validation tests,
+	 * lib/tools/source/swift_tools.c
+	 */
+	writel((15 << 9) | (62 << 3) | 3, (void *)PNX8181_CGU_PER2CON);
+
+	/* turn on PLL */
+	writel(readl((void *)PNX8181_CGU_PER2CON) | 0x00010000,
+						(void *)PNX8181_CGU_PER2CON);
+	/* wait for PLL lock */
+	while (!(readl((void *)PNX8181_CGU_PER2CON) & 0x00020000))
+		;
+
+	/* ungate ETN clocks */
+	writel(readl((void *)PNX8181_CGU_PER2CON) | 0x00802000,
+						(void *)PNX8181_CGU_PER2CON);
+
+	/* register ip3912 mii interface */
+	ip3912_miiphy_initialize(gd->bd);
+
+	/* register ethernet devices */
+	switch (get_boardrevision()) {
+	case 1:
+	case 2:
+		firetux_sysmux_config_rmii();
+		firetux_sysmux_config_etn1();
+		firetux_sysmux_config_etn2();
+		/* phys are at addr 0x1 & 0x2 at RMII phybus */
+		rc |= ip3912_eth_initialize(0, CONFIG_IP3912_ETN1_BASE,
+					CONFIG_IP3912_ETN1_BASE, 0x01, 1);
+		rc |= ip3912_eth_initialize(1, CONFIG_IP3912_ETN2_BASE,
+					CONFIG_IP3912_ETN1_BASE, 0x02, 1);
+		break;
+	case 3:
+	case 4:
+		firetux_sysmux_config_rmii();
+		firetux_sysmux_config_etn1();
+		firetux_sysmux_config_etn2();
+		/* phys are at addr 0x1e & 0x1d at RMII phybus */
+		rc |= ip3912_eth_initialize(0, CONFIG_IP3912_ETN1_BASE,
+					CONFIG_IP3912_ETN1_BASE, 0x1e, 1);
+		rc |= ip3912_eth_initialize(1, CONFIG_IP3912_ETN2_BASE,
+					CONFIG_IP3912_ETN1_BASE, 0x1d, 1);
+		break;
+	default:
+		return -1;
+	}
+	return rc;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	/* arch number of Firetux Platform Boards */
+	gd->bd->bi_arch_number = MACH_TYPE_PNX8181;
+
+	/* adress of boot parameters / atags */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	/* release the RSTAPU and RSTEXT signal which keeps the PHYs in reset */
+	writel(readw((void *)PNX8181_WDRUCON) | 0x0009,
+						(void *)PNX8181_WDRUCON);
+	/* lower VDDIO to Vbgp * 2.44 (typ. 3.05V) */
+	writel(0x0079, (void *)PNX8181_DAIF_RVDDC);
+
+	/* select TXD2 for GPIOa11 and select RXD2 for GPIOa1 */
+	writel(((readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX0))
+						& 0xff3ffff3) | 0x00400004),
+				(void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX0));
+	/* select ETN for GPIOc0-16 */
+	writel(readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX5))
+								& 0xfffffffc,
+				(void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX5));
+	writel(readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4))
+								& 0x30000000,
+				(void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4));
+
+	/* use clk26m and fract-n for UART2 */
+	writew(((1 << 7) | (1 << 1)),
+			(void *)(PNX8181_UART2_BASE + PNX8181_UART_FDIV_CTRL));
+	writew(0x5F37, (void *)(PNX8181_UART2_BASE + PNX8181_UART_FDIV_M));
+	writew(0x32C8, (void *)(PNX8181_UART2_BASE + PNX8181_UART_FDIV_N));
+
+	board_detect();
+
+	firetux_gpio_init();
+
+	icache_enable();
+	dcache_enable();
+
+#ifdef CONFIG_CMD_NAND
+	firetux_nandflash_init();
+#else
+	firetux_norflash_init();
+#endif
+
+	firetux_irq_disable();
+
+	return 0;
+}
+
+int firetux_keystatus(int key)
+{
+	int ret = 0;
+
+	switch (key) {
+	case 1:	/* GPIOA2 */
+		ret = get_gpioa(2);
+		break;
+	case 2:	/* GPIOA10 */
+		ret = get_gpioa(10);
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+void firetux_check_bootkey(void)
+{
+	int i = 0, abort = 0;
+
+	while ((abort == 0) && (i < 500)) {
+		if (firetux_keystatus(2) == 1) {
+			setenv("bootcmd", "run bootcmd1");
+			firetux_set_led(2, 0);
+			abort = 1;
+		}
+		i++;
+		udelay(10000);
+	}
+	if (abort == 0) {
+		setenv("bootcmd", "run bootcmd2");
+		puts("using alternative bootcmd\n");
+		firetux_set_led(2, 1);
+	}
+}
+
+int misc_init_r(void)

board/dspg/firetux/firetux.c new file +65 -0

+{
+	unsigned int sysver, cgu_sccon, armclk, hclk;
+
+	puts("CPU: ");
+	sysver = readw((void *)PNX8181_REG_SC_SYSVER);
+	printf("PNX8181-%d%c %s-ARM926EJ-S(ARMv5TEJ) ",
+		((sysver >> 4) & 0xf), ((sysver & 0xf) + 64),
+		(((sysver >> 8) & 0xf) == 1) ? "OM6xxx" : "unknown");
+
+	cgu_sccon = readw((void *)PNX8181_CGU_SCCON);
+
+	/* armclk = bbcki * nsc / msc / ksc */
+	armclk = 13824 * (((cgu_sccon >> 3) & 0x3f) + 1)
+		/ ((cgu_sccon & 0x7) + 1)
+		/ (((cgu_sccon >> 10) & 0x3) + 1);
+	hclk = armclk / (((cgu_sccon >> 12) & 0xf) + 1);
+
+	printf("@ %dMHz(armclk), %dMHz(hclk)\n",
+		(armclk / 1000), (hclk / 1000));
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+int checkboard(void)
+{
+	puts("Board: ");
+
+	switch (get_boardrevision()) {
+	case 1:
+		puts("EZ_MCP_PNX8181\n");
+		break;
+	case 2:
+		puts("Vega_PNX8181_BaseStation Platform III-a\n");
+		break;
+	case 3:
+		puts("Vega_PNX8181_BaseStation Platform III-b\n");
+		break;
+	case 4:
+		puts("Vega_PNX8181_BaseStation Platform III-c\n");
+		break;
+	case 0:
+	default:
+		puts("unknown PNX8181 board\n");
+		break;
+	}
+
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	int reg;
+
+	reg = readl((void *)PNX8181_SDI_CFG_1);
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = 1 << (
+		(reg & 0x3) +			/* dram width 8, 16, 32, 64 */
+		(((reg & 0x30) >> 4) + 8) +	/* columns 8, 9, 10, 11 */
+		(((reg & 0x700) >> 8) + 9) +	/* rows 9 .. 16 */
+		((reg & 0x3000) >> 12));	/* nr banks 1, 2, 4 */
+
+	return 0;
+}

board/dspg/firetux/firetux.h new file +39 -0

new file mode 100644
index 0000000..0196197
@@ -0,0 +1,144 @@
+/*
+ * firetux board specific defines
+ *
+ * (C) Copyright 2007-2009, emlix GmbH, Germany
+ * Juergen Schoew <[email protected]>
+ *
+ * (C) Copyright 2008, DSPG Technologies GmbH, Germany
+ * (C) Copyright 2007, NXP Semiconductors Germany GmbH
+ * Matthias Wenzel, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Boardrevisions:
+ * 0: unknown PNX8181 board
+ * 1: EZ_MCP_PNX8181
+ * 2: Vega_PNX8181_BaseStation Platform III-a
+ * 3: Vega_PNX8181_BaseStation Platform III-b
+ * 4: Vega_PNX8181_BaseStation Platform III-c
+ */
+#define CONFIG_MAX_BOARDREVISIONS       4
+enum firetux_revisions {

--===============1974869777==
Content-Type: multipart/signed; boundary="Sig_/7=Xl+9NRIJIvmVYW4MQsT9k";
protocol="application/pgp-signature"; micalg=PGP-SHA1

--Sig_/7=Xl+9NRIJIvmVYW4MQsT9k
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

 MAINTAINERS                        |    4 +
 MAKEALL                            |    1 +
 Makefile                           |    7 +
 board/dspg/firetux/Makefile        |   59 ++++
 board/dspg/firetux/boardrevision.c |  299 ++++++++++++++++
 board/dspg/firetux/config.mk       |   44 +++
 board/dspg/firetux/firetux.c       |  413 ++++++++++++++++++++++
 board/dspg/firetux/firetux.h       |  144 ++++++++
 board/dspg/firetux/gpio.c          |  134 ++++++++
 board/dspg/firetux/led.c           |  169 +++++++++
 board/dspg/firetux/lowlevel_init.S |  404 ++++++++++++++++++++++
 board/dspg/firetux/memsetup.S      |  381 +++++++++++++++++++++
 board/dspg/firetux/nand.c          |   68 ++++
 board/dspg/firetux/relocate.S      |  252 ++++++++++++++
 board/dspg/firetux/u-boot.lds      |   57 +++
 include/configs/firetux.h          |  454 +++++++++++++++++++++++++

Dear =?UTF-8?B?SsO8cmdlbiBTY2jDtnc=?=,

Quoted 9 lines · In message <[email protected]> you wrote:

--===============1974869777==
Content-Type: multipart/signed; boundary="Sig_/7=Xl+9NRIJIvmVYW4MQsT9k"; protocol="application/pgp-signature"; micalg=PGP-SHA1

--Sig_/7=Xl+9NRIJIvmVYW4MQsT9k
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Quoted 16 lines

 MAINTAINERS                        |    4 +
 MAKEALL                            |    1 +
 Makefile                           |    7 +
 board/dspg/firetux/Makefile        |   59 ++++
 board/dspg/firetux/boardrevision.c |  299 ++++++++++++++++
 board/dspg/firetux/config.mk       |   44 +++
 board/dspg/firetux/firetux.c       |  413 ++++++++++++++++++++++
 board/dspg/firetux/firetux.h       |  144 ++++++++
 board/dspg/firetux/gpio.c          |  134 ++++++++
 board/dspg/firetux/led.c           |  169 +++++++++
 board/dspg/firetux/lowlevel_init.S |  404 ++++++++++++++++++++++
 board/dspg/firetux/memsetup.S      |  381 +++++++++++++++++++++
 board/dspg/firetux/nand.c          |   68 ++++
 board/dspg/firetux/relocate.S      |  252 ++++++++++++++
 board/dspg/firetux/u-boot.lds      |   57 +++
 include/configs/firetux.h          |  454 +++++++++++++++++++++++++

Here, like it seems in all your patches, there is no signed-off-by line.

We cannot accept patches that are missing the SoB.

I sure can understand that you cannot accept messages without SoB. Isn't it sufficient to have them in the first mail ( [0/3] ) of the patchset? There have been the following lines:

Will try to improve the next mails.