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forcedeth: add clock gating feature

PATCH In review Ayaz Abdulla 4 participants 4 messages Apr 27, 2009 – Apr 28, 2009

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Ayaz Abdulla

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#0 lore raw

PATCH 1/1 forcedeth: add clock gating feature

This patch adds support for clock gating the tx/rx engines which is available on certain chipsets.

Signed-off-by Ayaz Abdulla <[email protected]>
drivers/net/forcedeth.c +23 -0
@@ -343,6 +343,7 @@
 #define NVREG_POWERSTATE2_POWERUP_MASK		0x0F15
 #define NVREG_POWERSTATE2_POWERUP_REV_A3	0x0001
 #define NVREG_POWERSTATE2_PHY_RESET		0x0004
+#define NVREG_POWERSTATE2_GATE_CLOCKS		0x0F00
 };
 
 /* Big endian: should work, but is untested */

@@ -1017,6 +1018,23 @@
 		return 1;
 }
 
+static void nv_txrx_gate(struct net_device *dev, bool gate)
+{
+	struct fe_priv *np = get_nvpriv(dev);
+	u8 __iomem *base = get_hwbase(dev);
+	u32 powerstate;
+
+	if (!np->mac_in_use &&
+	    (np->driver_data & DEV_HAS_POWER_CNTRL)) {
+		powerstate = readl(base + NvRegPowerState2);
+		if (gate)
+			powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
+		else
+			powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
+		writel(powerstate,base + NvRegPowerState2);
+	}
+}
+
 static void nv_enable_irq(struct net_device *dev)
 {
 	struct fe_priv *np = get_nvpriv(dev);

@@ -3394,12 +3412,14 @@
 		if (!netif_carrier_ok(dev)) {
 			netif_carrier_on(dev);
 			printk(KERN_INFO "%s: link up.\n", dev->name);
+			nv_txrx_gate(dev, false);
 			nv_start_rx(dev);
 		}
 	} else {
 		if (netif_carrier_ok(dev)) {
 			netif_carrier_off(dev);
 			printk(KERN_INFO "%s: link down.\n", dev->name);
+			nv_txrx_gate(dev, true);
 			nv_stop_rx(dev);
 		}
 	}

@@ -5327,6 +5347,7 @@
 	mii_rw(dev, np->phyaddr, MII_BMCR,
 	       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
 
+	nv_txrx_gate(dev, false);
 	/* erase previous misconfiguration */
 	if (np->driver_data & DEV_HAS_POWER_CNTRL)
 		nv_mac_reset(dev);

@@ -5514,12 +5535,14 @@
 	nv_drain_rxtx(dev);
 
 	if (np->wolenabled) {
+		nv_txrx_gate(dev, false);
 		writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
 		nv_start_rx(dev);
 	} else {
 		/* power down phy */
 		mii_rw(dev, np->phyaddr, MII_BMCR,
 		       mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
+		nv_txrx_gate(dev, true);
 	}
 
 	/* FIXME: power down nic */
#1 lore raw
Quoted 2 lines · On Mon, 27 Apr 2009 08:31:35 -0400 Ayaz Abdulla <[email protected]> wrote:

This patch adds support for clock gating the tx/rx engines which is available on certain chipsets.

What are the effects of this patch? Improved power management? Fixes a user-visible bug? Something else?

#2 lore raw

Hi,

Le Monday 27 April 2009 21:24:47 Andrew Morton, vous avez écrit :

Quoted 8 lines

On Mon, 27 Apr 2009 08:31:35 -0400

Quoted 2 lines · Ayaz Abdulla

This patch adds support for clock gating the tx/rx engines which is available on certain chipsets.

What are the effects of this patch? Improved power management? Fixes a user-visible bug? Something else?

Clock gating is a design technique which improves power consumption by only clocking the necessary parts of the chip.

Ayaz do you have any figures on how this patch reduces consumption ?

Signature · 4 lines
Best regards, Florian Fainelli
Email : [email protected]
http://openwrt.org
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