Omap fixes for 2.6.31

---
 arch/arm/mach-omap1/mailbox.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/mach-omap1/mailbox.c +1 -1

index 0af4d6c..6810b4a 100644
@@ -203,5 +203,5 @@ module_exit(omap1_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU" <[email protected]>);
+MODULE_AUTHOR("Hiroshi DOYU <[email protected]>");
 MODULE_ALIAS("platform:omap1-mailbox");

Tony Lindgren

author maintainer

2009-06-22 11:39 UTC #2 lore raw

PATCH 2/12 OMAP1: Fix N770 MMC support

From: Andrew de Quincey <[email protected]>

Some of the N770's MMC configuration options seem to have been dropped. This patch adds them back in again.

Note that only the .ocr_mask change was /critical/, but I've added the .max_freq setting back as well, as the original sources had it. Can anyone confirm if this is unnecessary?

Secondly, there is support in the original code for a 4wire/higher speed mode. As I don't have the requisite N770 hardware (I think it was a rev2 N770?) to test this, I can't really add it back.

Signed-off-by Andrew de Quincey <[email protected]>

---
 arch/arm/mach-omap1/board-nokia770.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

arch/arm/mach-omap1/board-nokia770.c +2 -0

index e70fc7c..d9ebba0 100644
@@ -205,9 +205,11 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot)
 static struct omap_mmc_platform_data nokia770_mmc2_data = {
 	.nr_slots                       = 1,
 	.dma_mask			= 0xffffffff,
+	.max_freq                       = 12000000,
 	.slots[0]       = {
 		.set_power		= nokia770_mmc_set_power,
 		.get_cover_state	= nokia770_mmc_get_cover_state,
+		.ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
 		.name                   = "mmcblk",
 	},
 };

Tony Lindgren

author maintainer

2009-06-22 11:40 UTC #3 lore raw

PATCH 3/12 OMAP1: remove duplicated #include

From: Huang Weiyi <[email protected]>

Remove duplicated #include in arch/arm/mach-omap1/board-nokia770.c.

Signed-off-by Huang Weiyi <[email protected]>

---
 arch/arm/mach-omap1/board-nokia770.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

arch/arm/mach-omap1/board-nokia770.c +0 -1

index d9ebba0..ed2a48a 100644
@@ -36,7 +36,6 @@
 #include <mach/hwa742.h>
 #include <mach/lcd_mipid.h>
 #include <mach/mmc.h>
-#include <mach/usb.h>
 #include <mach/clock.h>
 
 #define ADS7846_PENDOWN_GPIO	15

Tony Lindgren

author maintainer

2009-06-22 11:42 UTC #4 lore raw

PATCH 4/12 OMAP2/3: mmc-twl4030: use correct controller in twl_mmc23_set_power

From: Grazvydas Ignotas <[email protected]>

twl_mmc23_set_power() has MMC2 twl_mmc_controller hardcoded in it, which breaks MMC3. Find the right controller to use instead.

Signed-off-by Grazvydas Ignotas <[email protected]>

Cc David Brownell <[email protected]>

---
 arch/arm/mach-omap2/mmc-twl4030.c |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)

arch/arm/mach-omap2/mmc-twl4030.c +12 -1

index 9756a87..1541fd4 100644
@@ -263,8 +263,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
 static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd)
 {
 	int ret = 0;
-	struct twl_mmc_controller *c = &hsmmc[1];
+	struct twl_mmc_controller *c = NULL;
 	struct omap_mmc_platform_data *mmc = dev->platform_data;
+	int i;
+
+	for (i = 1; i < ARRAY_SIZE(hsmmc); i++) {
+		if (mmc == hsmmc[i].mmc) {
+			c = &hsmmc[i];
+			break;
+		}
+	}
+
+	if (c == NULL)
+		return -ENODEV;
 
 	/* If we don't see a Vcc regulator, assume it's a fixed
 	 * voltage always-on regulator.

Tony Lindgren

author maintainer

2009-06-22 11:43 UTC #5 lore raw

PATCH 5/12 OMAP2/3: omap mailbox: platform_get_irq() error ignored

From: Roel Kluin <[email protected]>

platform_get_irq may return -ENXIO. but struct omap_mbox mbox_dsp_info.irq is unsigned, so the error was not noticed.

Signed-off-by Roel Kluin <[email protected]>

Signed-off-by Hiroshi DOYU <[email protected]>

---
 arch/arm/mach-omap2/mailbox.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

arch/arm/mach-omap2/mailbox.c +3 -3

index fd5b8a5..6f71f37 100644
@@ -282,12 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	/* DSP or IVA2 IRQ */
-	mbox_dsp_info.irq = platform_get_irq(pdev, 0);
-	if (mbox_dsp_info.irq < 0) {
+	ret = platform_get_irq(pdev, 0);
+	if (ret < 0) {
 		dev_err(&pdev->dev, "invalid irq resource\n");
-		ret = -ENODEV;
 		goto err_dsp;
 	}
+	mbox_dsp_info.irq = ret;
 
 	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
 	if (ret)

Tony Lindgren

author maintainer

2009-06-22 11:45 UTC #6 lore raw

PATCH 6/12 OMAP2/3: Add omap_type() for determining GP/EMU/HS

From: Kevin Hilman <[email protected]>

The omap_type() function is added and returns the DEVICETYPE field of the CONTROL_STATUS register. The result can be used for conditional code based on whether device is GP (general purpose), EMU or HS (high security). Also move the type defines so omap1 code compile does not require ifdefs for sections using these defines.

This code is needed for the following fix to set the SRAM size correctly for HS omaps. Also at least PM and watchdog code will need this function.

---
 arch/arm/mach-omap2/id.c              |   22 ++++++++++++++++++++++
 arch/arm/plat-omap/include/mach/cpu.h |   22 +++++++++++-----------
 2 files changed, 33 insertions(+), 11 deletions(-)

arch/arm/mach-omap2/id.c +22 -0

index 458990e..a98201c 100644
@@ -48,6 +48,28 @@ int omap_chip_is(struct omap_chip_id oci)
 }
 EXPORT_SYMBOL(omap_chip_is);
 
+int omap_type(void)
+{
+	u32 val = 0;
+
+	if (cpu_is_omap24xx())
+		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
+	else if (cpu_is_omap34xx())
+		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
+	else {
+		pr_err("Cannot detect omap type!\n");
+		goto out;
+	}
+
+	val &= OMAP2_DEVICETYPE_MASK;
+	val >>= 8;
+
+out:
+	return val;
+}
+EXPORT_SYMBOL(omap_type);
+
+
 /*----------------------------------------------------------------------------*/
 
 #define OMAP_TAP_IDCODE		0x0204

arch/arm/plat-omap/include/mach/cpu.h +11 ~~-11~~

index fc60c4e..285eaa3 100644
@@ -30,6 +30,17 @@
 #ifndef __ASM_ARCH_OMAP_CPU_H
 #define __ASM_ARCH_OMAP_CPU_H
 
+/*
+ * Omap device type i.e. EMU/HS/TST/GP/BAD
+ */
+#define OMAP2_DEVICE_TYPE_TEST		0
+#define OMAP2_DEVICE_TYPE_EMU		1
+#define OMAP2_DEVICE_TYPE_SEC		2
+#define OMAP2_DEVICE_TYPE_GP		3
+#define OMAP2_DEVICE_TYPE_BAD		4
+
+int omap_type(void);
+
 struct omap_chip_id {
 	u8 oc;
 	u8 type;

@@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 
 int omap_chip_is(struct omap_chip_id oci);
-int omap_type(void);
-
-/*
- * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
- */
-#define OMAP2_DEVICE_TYPE_TEST		0
-#define OMAP2_DEVICE_TYPE_EMU		1
-#define OMAP2_DEVICE_TYPE_SEC		2
-#define OMAP2_DEVICE_TYPE_GP		3
-#define OMAP2_DEVICE_TYPE_BAD		4
-
 void omap2_check_revision(void);
 
 #endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */

Tony Lindgren

author maintainer

2009-06-22 11:46 UTC #7 lore raw

PATCH 7/12 OMAP3: SRAM size fix for HS/EMU devices

From: Tero Kristo <[email protected]>

SRAM size fix for HS/EMU devices

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/plat-omap/sram.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

arch/arm/plat-omap/sram.c +6 -1

index a5b9bcd..1c18de9 100644
@@ -133,7 +133,12 @@ void __init omap_detect_sram(void)
 			if (cpu_is_omap34xx()) {
 				omap_sram_base = OMAP3_SRAM_PUB_VA;
 				omap_sram_start = OMAP3_SRAM_PUB_PA;
-				omap_sram_size = 0x8000; /* 32K */
+				if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
+				    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
+					omap_sram_size = 0x7000; /* 28K */
+				} else {
+					omap_sram_size = 0x8000; /* 32K */
+				}
 			} else {
 				omap_sram_base = OMAP2_SRAM_PUB_VA;
 				omap_sram_start = OMAP2_SRAM_PUB_PA;

Tony Lindgren

author maintainer

2009-06-22 11:47 UTC #8 lore raw

PATCH 8/12 OMAP3: DMA: Enable idlemodes for DMA OCP

From: Kalle Jokiniemi <[email protected]>

This patch enables MStandby smart-idle mode, autoidle smartidle mode, and the autoidle bit for DMA4_OCP_SYSCONFIG.

Signed-off-by Kalle Jokiniemi <[email protected]>

---
 arch/arm/plat-omap/dma.c              |   13 +++++++++++++
 arch/arm/plat-omap/include/mach/dma.h |   15 +++++++++++++++
 2 files changed, 28 insertions(+), 0 deletions(-)

arch/arm/plat-omap/dma.c +13 -0

index def14ec..7677a4a 100644
@@ -2457,6 +2457,19 @@ static int __init omap_init_dma(void)
 		setup_irq(irq, &omap24xx_dma_irq);
 	}
 
+	/* Enable smartidle idlemodes and autoidle */
+	if (cpu_is_omap34xx()) {
+		u32 v = dma_read(OCP_SYSCONFIG);
+		v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
+				DMA_SYSCONFIG_SIDLEMODE_MASK |
+				DMA_SYSCONFIG_AUTOIDLE);
+		v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+			DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+			DMA_SYSCONFIG_AUTOIDLE);
+		dma_write(v , OCP_SYSCONFIG);
+	}
+
+
 	/* FIXME: Update LCD DMA to work on 24xx */
 	if (cpu_class_is_omap1()) {
 		r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,

arch/arm/plat-omap/include/mach/dma.h +15 -0

index 8c1eae8..7b939cc 100644
@@ -389,6 +389,21 @@
 #define DMA_THREAD_FIFO_25		(0x02 << 14)
 #define DMA_THREAD_FIFO_50		(0x03 << 14)
 
+/* DMA4_OCP_SYSCONFIG bits */
+#define DMA_SYSCONFIG_MIDLEMODE_MASK		(3 << 12)
+#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK	(3 << 8)
+#define DMA_SYSCONFIG_EMUFREE			(1 << 5)
+#define DMA_SYSCONFIG_SIDLEMODE_MASK		(3 << 3)
+#define DMA_SYSCONFIG_SOFTRESET			(1 << 2)
+#define DMA_SYSCONFIG_AUTOIDLE			(1 << 0)
+
+#define DMA_SYSCONFIG_MIDLEMODE(n)		((n) << 12)
+#define DMA_SYSCONFIG_SIDLEMODE(n)		((n) << 3)
+
+#define DMA_IDLEMODE_SMARTIDLE			0x2
+#define DMA_IDLEMODE_NO_IDLE			0x1
+#define DMA_IDLEMODE_FORCE_IDLE			0x0
+
 /* Chaining modes*/
 #ifndef CONFIG_ARCH_OMAP1
 #define OMAP_DMA_STATIC_CHAIN		0x1

Tony Lindgren

author maintainer

2009-06-22 11:49 UTC #9 lore raw

PATCH 9/12 OMAP2/3: gpmc-onenand: correct use of async timings

From: Adrian Hunter <[email protected]>

Use async timings when sync timings are not requested.

Also ensure that OneNAND is in async mode when async timings are used.

Signed-off-by Adrian Hunter <[email protected]>

---
 arch/arm/mach-omap2/gpmc-onenand.c |   21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/gpmc-onenand.c +19 -2

index 2fd22f9..54fec53 100644
@@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = {
 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 {
 	struct gpmc_timings t;
+	u32 reg;
+	int err;
 
 	const int t_cer = 15;
 	const int t_avdp = 12;

@@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 	const int t_wpl = 40;
 	const int t_wph = 30;
 
+	/* Ensure sync read and sync write are disabled */
+	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
+	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
+	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+
 	memset(&t, 0, sizeof(t));
 	t.sync_clk = 0;
 	t.cs_on = 0;

@@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 			  GPMC_CONFIG1_DEVICESIZE_16 |
 			  GPMC_CONFIG1_MUXADDDATA);
 
-	return gpmc_cs_set_timings(cs, &t);
+	err = gpmc_cs_set_timings(cs, &t);
+	if (err)
+		return err;
+
+	/* Ensure sync read and sync write are disabled */
+	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
+	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
+	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+
+	return 0;
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,

@@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
 		sync_read = 1;
 		sync_write = 1;
-	}
+	} else
+		return omap2_onenand_set_async_mode(cs, onenand_base);
 
 	if (!freq) {
 		/* Very first call freq is not known */

Tony Lindgren

author maintainer

2009-06-22 11:50 UTC #10 lore raw

PATCH 10/12 OMAP3: RX51: Use OneNAND sync read / write

From: Adrian Hunter <[email protected]>

Use OneNAND sync read / write

Signed-off-by Adrian Hunter <[email protected]>

---
 arch/arm/mach-omap2/board-rx51-peripherals.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/board-rx51-peripherals.c +1 -0

index da93b86..9a0bf67 100644
@@ -362,6 +362,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
 	.gpio_irq	= 65,
 	.parts		= onenand_partitions,
 	.nr_parts	= ARRAY_SIZE(onenand_partitions),
+	.flags		= ONENAND_SYNC_READWRITE,
 };
 
 static void __init board_onenand_init(void)

Tony Lindgren

author maintainer

2009-06-22 11:51 UTC #11 lore raw

PATCH 11/12 OMAP: IOMMU: function flush_iotlb_page is not flushing correct entry

From: Fernando Guzman Lugo <[email protected]>

The function flush_iotlb_page is not loading the CAM register with the correct entry to be flushed, so it is flushing other entry

Signed-off-by Fernando Guzman Lugo <[email protected]>

Signed-off-by Hiroshi DOYU <[email protected]>

---
 arch/arm/plat-omap/iommu.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/plat-omap/iommu.c +1 -1

index 4cf449f..4a03013 100644
@@ -298,7 +298,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da)
 		if ((start <= da) && (da < start + bytes)) {
 			dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
 				__func__, start, da, bytes);
-
+			iotlb_load_cr(obj, &cr);
 			iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
 		}
 	}

Tony Lindgren

author maintainer

2009-06-22 11:53 UTC #12 lore raw

PATCH 12/12 OMAP2/3: Initialize gpio debounce register

From: janboe <[email protected]>

Some bootloader may initialize debounce register and this will make dbclk not consist with the debounce register after linux kernel boot up.

Signed-off-by janboe <[email protected]>

---
 arch/arm/plat-omap/gpio.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

arch/arm/plat-omap/gpio.c +1 -0

index 7fd89ba..26b387c 100644
@@ -1585,6 +1585,7 @@ static int __init _omap_gpio_init(void)
 			__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
 			__raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
 			__raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
+			__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
 
 			/* Initialize interface clock ungated, module enabled */
 			__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);

Tony Lindgren

author maintainer

2009-06-23 13:58 UTC #13 lore raw

[PATCH 13/12] OMAP: Fix IOMEM macro for assembly

Here's one more fix.

Tony

Quoted 1 line

From 503dcbeba50fd3545283594bc391b4a400fa6c48 Mon Sep 17 00:00:00 2001

From: Tony Lindgren <[email protected]>
Date: Tue, 23 Jun 2009 16:55:30 +0300
Subject: [PATCH] OMAP: Fix IOMEM macro for assembly

Otherwise IOMEM calculations can fail.

arch/arm/plat-omap/include/mach/io.h +1 -1

index 3b28147..73f483d 100644
@@ -201,7 +201,7 @@
 #define OMAP2_IO_ADDRESS(pa)	IOMEM(__OMAP2_IO_ADDRESS(pa))
 
 #ifdef __ASSEMBLER__
-#define IOMEM(x)		x
+#define IOMEM(x)		(x)
 #else
 #define IOMEM(x)		((void __force __iomem *)(x))

Russell King - ARM Linux

2009-06-25 12:27 UTC #14 lore raw