Add support for Raidsonic ICYBOX NAS4220 board

RFC PATCH New Darius Augulis 4 participants 9 messages Jun 30, 2009 – Aug 5, 2009

Subsystems (2)

Kbuild Arm/actions semi architecture

lore

Share & tools

lore

Darius Augulis

author

2009-06-30 19:03 UTC #0 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name.

Signed-off-by Darius Augulis <[email protected]>

---

 MAINTAINERS                          |    4 +
 MAKEALL                              |    1 
 Makefile                             |    3 
 board/nas4220/Makefile               |   43 +++++
 board/nas4220/config.mk              |   14 ++
 board/nas4220/lowlevel_init.S        |   96 ++++++++++++
 board/nas4220/nas4220.c              |   75 +++++++++
 board/nas4220/u-boot.lds             |   48 ++++++
 cpu/arm920t/gemini/Makefile          |   38 +++++
 cpu/arm920t/gemini/timer.c           |   93 ++++++++++++
 cpu/arm920t/start.S                  |   11 +
 include/asm-arm/arch-gemini/gemini.h |  271 ++++++++++++++++++++++++++++++++++
 include/configs/nas4220.h            |  116 +++++++++++++++
 13 files changed, 811 insertions(+), 2 deletions(-)
 create mode 100644 board/nas4220/Makefile
 create mode 100644 board/nas4220/config.mk
 create mode 100644 board/nas4220/lowlevel_init.S
 create mode 100644 board/nas4220/nas4220.c
 create mode 100644 board/nas4220/u-boot.lds
 create mode 100644 cpu/arm920t/gemini/Makefile
 create mode 100644 cpu/arm920t/gemini/timer.c
 create mode 100644 include/asm-arm/arch-gemini/gemini.h
 create mode 100644 include/configs/nas4220.h

MAINTAINERS +4 -0

index 9379c7e..ade43ed 100644
@@ -671,6 +671,10 @@ Sergey Lapin <[email protected]>
 
 	afeb9260	ARM926EJS (AT91SAM9260 SoC)
 
+Darius Augulis <[email protected]>
+
+	nas4220		CS3516
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

MAKEALL +1 -0

index f4599d6..8d28e36 100755
@@ -511,6 +511,7 @@ LIST_ARM9="			\
 	lpd7a400		\
 	mx1ads			\
 	mx1fs2			\
+	nas4220			\
 	netstar			\
 	nmdk8815		\
 	omap1510inn		\

Makefile +3 -0

index bcc81c9..99c59c3 100644
@@ -2836,6 +2836,9 @@ mx1ads_config	:	unconfig
 mx1fs2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
 
+nas4220_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm920t nas4220 NULL gemini
+
 netstar_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm925t netstar

board/nas4220/Makefile new file +43 -0

43 lines not on this page · raw message

board/nas4220/config.mk new file +14 -0

new file mode 100644
index 0000000..5b418ba
@@ -0,0 +1,14 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Author: Darius Augulis <[email protected]> <[email protected]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+
+TEXT_BASE = 0x10400000
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds

board/nas4220/lowlevel_init.S new file +96 -0

96 lines not on this page · raw message

board/nas4220/nas4220.c new file +75 -0

75 lines not on this page · raw message

board/nas4220/u-boot.lds new file +48 -0

48 lines not on this page · raw message

cpu/arm920t/gemini/Makefile new file +38 -0

new file mode 100644
index 0000000..ca262e3
@@ -0,0 +1,38 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Author: Darius Augulis <[email protected]> <[email protected]>
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	+= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

cpu/arm920t/gemini/timer.c new file +93 -0

93 lines not on this page · raw message

cpu/arm920t/start.S +9 -2

index 475cdaf..761753e 100644
@@ -115,8 +115,10 @@ start_code:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-	bl coloured_LED_init
-	bl red_LED_on
+#ifndef CONFIG_GEMINI
+	bl	coloured_LED_init
+	bl	red_LED_on
+#endif
 
 #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
 	/*

@@ -189,6 +191,11 @@ relocate:				/* relocate U-Boot to RAM	    */
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
+#ifdef CONFIG_GEMINI
+	orr	r0, r0, #CONFIG_SYS_FLASH_BASE
+	orr	r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif
+
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */

include/asm-arm/arch-gemini/gemini.h new file +271 -0

271 lines not on this page · raw message

include/configs/nas4220.h new file +116 -0

116 lines not on this page · raw message

Po-Yu Chuang

2009-07-03 04:38 UTC #1 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

Dear Darius Augulis,

2009/7/1 Darius Augulis <[email protected]>:

Quoted 18 lines

This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name.
Signed-off-by Darius Augulis <[email protected]>
---
cpu/arm920t/start.S +0 -0
index 475cdaf..761753e 100644
@@ -115,8 +115,10 @@ start_code:
? ? ? ?orr ? ? r0,r0,#0xd3
? ? ? ?msr ? ? cpsr,r0
- ? ? ? bl coloured_LED_init
- ? ? ? bl red_LED_on

cpu/arm920t/start.S start_code: · line 121

Quoted 4 lines

cpu/arm920t/start.S +4 -0

+#ifndef CONFIG_GEMINI
+ ? ? ? bl ? ? ?coloured_LED_init
+ ? ? ? bl ? ? ?red_LED_on
+#endif

This is unnecessary.

cpu/arm920t/start.S relocate: /* relocate U-Boot to RAM */ · line 197

Quoted 10 lines

?#if ? ?defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) ? ? ? ?/*
cpu/arm920t/start.S +0 -0
@@ -189,6 +191,11 @@ relocate: ? ? ? ? ? ? ? ? ? ? ? ? ?/* relocate U-Boot to RAM ? ? ? ? ? */
? ? ? ?sub ? ? r2, r3, r2 ? ? ? ? ? ? ?/* r2 <- size of armboot ? ? ? ? ? ?*/ ? ? ? ?add ? ? r2, r0, r2 ? ? ? ? ? ? ?/* r2 <- source end address ? ? ? ? */
cpu/arm920t/start.S +4 -0
+#ifdef CONFIG_GEMINI
+ ? ? ? orr ? ? r0, r0, #CONFIG_SYS_FLASH_BASE
+ ? ? ? orr ? ? r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif

How about put a jump to the Flash at the very beginning of "start_code"?

start_code:
ldr r0, _start_from_flash
orr pc, r0, #CONFIG_SYS_FLASH_BASE

_start_from_flash: .word start_from_flash

start_from_flash:

    /* original start code here*/

Then maybe you don't need a customized linker script?

regards,
Po-Yu Chuang

Jean-Christophe PLAGNIOL-VILLARD

2009-07-07 22:29 UTC #2 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

In reply to Darius Augulis

Quoted 5 lines · Darius Augulis

This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name.

do you boot linux?

Quoted 40 lines

Signed-off-by Darius Augulis <[email protected]>

---

 MAINTAINERS                          |    4 +
 MAKEALL                              |    1 
 Makefile                             |    3 
 board/nas4220/Makefile               |   43 +++++
 board/nas4220/config.mk              |   14 ++
 board/nas4220/lowlevel_init.S        |   96 ++++++++++++
 board/nas4220/nas4220.c              |   75 +++++++++
 board/nas4220/u-boot.lds             |   48 ++++++
 cpu/arm920t/gemini/Makefile          |   38 +++++
 cpu/arm920t/gemini/timer.c           |   93 ++++++++++++
 cpu/arm920t/start.S                  |   11 +
 include/asm-arm/arch-gemini/gemini.h |  271 ++++++++++++++++++++++++++++++++++
 include/configs/nas4220.h            |  116 +++++++++++++++
 13 files changed, 811 insertions(+), 2 deletions(-)
 create mode 100644 board/nas4220/Makefile
 create mode 100644 board/nas4220/config.mk
 create mode 100644 board/nas4220/lowlevel_init.S
 create mode 100644 board/nas4220/nas4220.c
 create mode 100644 board/nas4220/u-boot.lds
 create mode 100644 cpu/arm920t/gemini/Makefile
 create mode 100644 cpu/arm920t/gemini/timer.c
 create mode 100644 include/asm-arm/arch-gemini/gemini.h
 create mode 100644 include/configs/nas4220.h

MAINTAINERS +4 -0

index 9379c7e..ade43ed 100644
@@ -671,6 +671,10 @@ Sergey Lapin <[email protected]>
 
 	afeb9260	ARM926EJS (AT91SAM9260 SoC)
 
+Darius Augulis <[email protected]>
+
+	nas4220		CS3516
+

<snip>

Quoted 47 lines

board/nas4220/config.mk new file +14 -0

new file mode 100644
index 0000000..5b418ba
@@ -0,0 +1,14 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Author: Darius Augulis <[email protected]> <[email protected]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+
+TEXT_BASE = 0x10400000
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds

board/nas4220/lowlevel_init.S new file +21 -0

new file mode 100644
index 0000000..d51a5a2
@@ -0,0 +1,96 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <[email protected]> <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/gemini.h>
+
+#define DRAM_SET_MODE	GEMINI_SET_MODE | GEMINI_MODE_DDRAM | \
+			GEMINI_CAS_3 | GEMINI_BL_4
+#define DRAM_SET_TYPE	GEMINI_BUS_32b | GEMINI_RAM_15x10_16x10
+

board/nas4220/lowlevel_init.S line 31

Quoted 10 lines

board/nas4220/lowlevel_init.S new file +10 -0

+#define DRAM_IOCAP	GEMINI_IOCAP_DRAM_CLOCK | GEMINI_IOCAP_DRAM_DATA | \
+			GEMINI_IOCAP_DRAM_CTRL
+#define DRAM_TIMING	GEMINI_RRATE_AREF8 | GEMINI_RTIMER(195) | \
+			GEMINI_TRFC(11) | GEMINI_TRAS(6) | GEMINI_TWR(3) | \
+			GEMINI_TRP(3) |	GEMINI_TRCD(3) | GEMINI_TCAS(3)
+#define DRAM_READ_DLL	GEMINI_RDLL_BYTE3(8) | GEMINI_RDLL_BYTE2(8) | \
+			GEMINI_RDLL_BYTE1(8) | GEMINI_RDLL_BYTE0(8)
+#define DRAM_WRITE_DLL	GEMINI_WDLL(26)
+#define DRAM_MEM_CTRL	GEMINI_TRAINING_MODE | GEMINI_DQS_N_FALLING | \
+			GEMINI_BUF_IN_4rd | (1 << 6)

please move this to config header and add CONFIG_SYS_ in the name

board/nas4220/lowlevel_init.S line 39

Quoted 8 lines

board/nas4220/lowlevel_init.S new file +8 -0

+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* DRAM init */
+	ldr	r0, =GEMINI_DRAM_TYPE		/* DRAM set type */
+	ldr	r1, =DRAM_SET_TYPE		/* 32bit, 64 Mbytes total */
+	str	r1, [r0]

please use write32

board/nas4220/lowlevel_init.S line 43

Quoted 4 lines

board/nas4220/lowlevel_init.S new file +4 -0

+
+	ldr	r0, =GEMINI_DRAM_MODE		/* DRAM set mode */
+	ldr	r1, =DRAM_SET_MODE		/* DDRAM, CAS 3, Burst 4 */
+	str	r1, [r0]

ditto etc...

board/nas4220/lowlevel_init.S line 48

Quoted 5 lines

board/nas4220/lowlevel_init.S new file +5 -0

+
+	ldr	r3, =GEMINI_GLOBAL_ID		/* Global ID reg */
+	ldr	r4, [r3]
+	ldr	r5, =0xFF			/* Chip revision mask */
+	and	r4, r4, r5

please create a function for this and call it

Quoted 8 lines

board/nas4220/lowlevel_init.S new file +8 -0

+	cmp	r4, #0xc0			/* Test if chip rev. is 'c0' */
+	bne	end_prefetch
+
+	/* Fix for rev. 'c0' chip */
+	ldr	r0, =GEMINI_DRAM_AHB_CTRL	/* AHB control */
+	ldr	r5, =GEMINI_WRITE_FLUSH_READ
+	str	r5, [r0]
+

<snip>

board/nas4220/lowlevel_init.S line 93

Quoted 10 lines

board/nas4220/lowlevel_init.S new file +10 -0

+
+	ldr	r2, =GEMINI_DRAM_BASE
+	mov	r4, #0xa0
+
+read_loop:
+	ldr	r3, [r2]			/* Read data */
+	subs	r4, r4, #1			/* Decrement loop count */
+	bge	read_loop
+
+	bic	r1, r1, #GEMINI_TRAINING_MODE	/* Disable train mode */

what is train mode?

Quoted 30 lines

board/nas4220/lowlevel_init.S new file +3 -0

+	str	r1, [r0]
+
+	mov	pc, lr

board/nas4220/nas4220.c new file +21 -0

new file mode 100644
index 0000000..784a249
@@ -0,0 +1,75 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <[email protected]> <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/gemini.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PINS	(GEMINI_PIN_UART_RX | GEMINI_PIN_UART_TX)
+#define MISC_CTRL	(GEMINI_PAD_SFLASH_DIS | GEMINI_PAD_NAND_DIS)
+

board/nas4220/nas4220.c line 31

Quoted 10 lines

board/nas4220/nas4220.c new file +10 -0

+int board_init(void)
+{
+	/* Bypass UART pins */
+	GEMINI_GPIO_BYPASS(0) |= UART_PINS;
+
+	/* Enable: parallel flash pins, disable: serial, nand pins */
+	GEMINI_GLOBAL_MISC = MISC_CTRL;
+
+	/* Enable parallel flash direct write mode */
+	GEMINI_FLASH_PAR_ACCESS |= GEMINI_PFLASH_DWR;

please use proper acess : writex

please create an api such as at91, davinci and other to manage this kind of config

Quoted 19 lines

board/nas4220/nas4220.c new file +19 -0

+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int cpu_id, cpu_rev, cpu_clk, ahb_clk;
+
+	cpu_id = GEMINI_CHIP_ID;
+	cpu_rev = GEMINI_CHIP_REV;
+	ahb_clk = GEMINI_AHB_CLK;
+
+	switch (GEMINI_CPU_AHB_RATIO) {
+	case 0:
+		cpu_clk = ahb_clk;
+		break;
+	case 1:
+		cpu_clk = (ahb_clk * 3) / 2;
+		break;

board/nas4220/nas4220.c line 60

Quoted 10 lines

board/nas4220/nas4220.c new file +10 -0

+	case 2:
+		cpu_clk = (ahb_clk * 24) / 13;
+		break;
+	case 3:
+		cpu_clk = ahb_clk * 2;
+		break;
+	default:
+		cpu_clk = 0;
+		break;
+	}

please create a clk api such as at91
please take a look on
cpu/arm926ejs/at91/clock.c
include/asm-arm/arch-at91/clk.h

board/nas4220/nas4220.c line 64

Quoted 4 lines

board/nas4220/nas4220.c new file +4 -0

+
+	printf("\nRaidsonic ICYBOX NAS4220 board\n");
+	printf("CPU: Gemini CS%X, REV: %X\n", cpu_id, cpu_rev);
+	printf("CPU Speed: %d MHz, AHB Speed: %d MHz, APB Speed: %d MHz\n\n", cpu_clk / 1000000, ahb_clk / 1000000, ahb_clk / 6000000);

please implement print_cpuinfo
and checkboard
and for clock string conversion please use strmhz

board/nas4220/u-boot.lds

Quoted 16 lines

board/nas4220/nas4220.c new file +11 -0

+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}

board/nas4220/u-boot.lds new file +0 -0

new file mode 100644
index 0000000..7d249c3

I do not understand why you need a specific lds?

Quoted 49 lines

board/nas4220/u-boot.lds new file +48 -0

@@ -0,0 +1,48 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <[email protected]> <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		cpu/arm920t/start.o		(.text)
+		board/nas4220/libnas4220.a	(.text)
+		lib_arm/libarm.a		(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}

<snip>

Quoted 8 lines

+++ b/cpu/arm920t/gemini/timer.c

board/nas4220/u-boot.lds new file +6 -0

@@ -0,0 +1,93 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <[email protected]> <[email protected]>

board/nas4220/u-boot.lds line 16

Quoted 10 lines

board/nas4220/u-boot.lds new file +10 -0

+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_GEMINI

no need please remove

board/nas4220/u-boot.lds line 26

Quoted 10 lines

board/nas4220/u-boot.lds new file +10 -0

+
+#include <asm/arch/gemini.h>
+
+static ulong gemini_usec;
+static ulong timestamp;
+static ulong extraticks;
+
+int timer_init(void)
+{
+	gemini_usec = GEMINI_APB_CLK / 1000000;

please clk framework as at91

board/nas4220/u-boot.lds line 29

Quoted 3 lines

board/nas4220/u-boot.lds new file +3 -0
+	timestamp = extraticks = 0;
+
+	GEMINI_TIMER_COUNT(0) = 0;

please use proprer accessor : writex/readx
etc...

Quoted 46 lines

board/nas4220/u-boot.lds new file +46 -0

+	GEMINI_TIMER_LOAD(0) = 0;
+	GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	GEMINI_TIMER_CR &= ~TIMER_CR_ENABLE(0);
+	GEMINI_TIMER_COUNT(0) = 0x0;
+	GEMINI_TIMER_LOAD(0) = 0x0;
+	GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+	timestamp = extraticks = 0;
+}
+
+unsigned long long get_usecs(void)
+{
+	ulong timenow = GEMINI_TIMER_COUNT(0);
+
+	if (timenow >= timestamp)
+		timestamp += timenow - extraticks;
+	else
+		timestamp += 0xFFFFFFFF - extraticks + timenow;
+	extraticks = timenow;
+
+	return timestamp / gemini_usec;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_usecs() / 1000) - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+void udelay(unsigned long usec)
+{
+	signed long elapsed;
+	ulong timestart = get_usecs();
+
+	do {
+		ulong timenow = get_usecs();
+		elapsed = timenow - timestart;

board/nas4220/u-boot.lds line 85

Quoted 10 lines

board/nas4220/u-boot.lds new file +10 -0

+	} while (elapsed < usec);
+}
+
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;

please retunr CONFIG_SYS_HZ directly

board/nas4220/u-boot.lds line 91

Quoted 6 lines

board/nas4220/u-boot.lds new file +6 -0

+}
+
+void reset_cpu(ulong ignored)
+{
+	GEMINI_GLOBAL_RESET = GEMINI_SOFT_RESET | GEMINI_CPU1_RESET;
+}

please move in reset.c or cpu.c

Quoted 7 lines

board/nas4220/u-boot.lds new file +2 -0
+
+#endif /* defined (CONFIG_GEMINI) */
cpu/arm920t/start.S +0 -0
index 475cdaf..761753e 100644

cpu/arm920t/start.S start_code: · line 121

Quoted 9 lines

cpu/arm920t/start.S +4 -2

@@ -115,8 +115,10 @@ start_code:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-	bl coloured_LED_init
-	bl red_LED_on
+#ifndef CONFIG_GEMINI
+	bl	coloured_LED_init
+	bl	red_LED_on
+#endif

no need please remove

cpu/arm920t/start.S relocate: /* relocate U-Boot to RAM */ · line 197

Quoted 11 lines

cpu/arm920t/start.S +4 -0

 #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
 	/*

@@ -189,6 +191,11 @@ relocate:				/* relocate U-Boot to RAM	    */
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
 	add	r2, r0, r2		/* r2 <- source end address         */
 
+#ifdef CONFIG_GEMINI
+	orr	r0, r0, #CONFIG_SYS_FLASH_BASE
+	orr	r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif

why?
and NACK the start.S MUST be generic
I'll rework the RM9200 code for this too

Quoted 21 lines

cpu/arm920t/start.S +1 -0

+
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */

include/asm-arm/arch-gemini/gemini.h new file +11 -0

new file mode 100644
index 0000000..e4fa91a
@@ -0,0 +1,271 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <[email protected]> <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.

include/asm-arm/arch-gemini/gemini.h line 21

Quoted 10 lines

include/asm-arm/arch-gemini/gemini.h new file +10 -0

+ */
+
+#ifndef __ASSEMBLY__
+# define REG8(x)	(*(volatile u8 *)(x))
+# define REG16(x)	(*(volatile u16 *)(x))
+# define REG32(x)	(*(volatile u32 *)(x))
+#else
+# define REG8(x)	(x)
+# define REG16(x)	(x)
+# define REG32(x)	(x)

NACK please use propoer accessor
and please split this file by functionnality such as usb, timer etc... and keep it here only global information

Quoted 39 lines

include/configs/nas4220.h new file +33 -0

new file mode 100644
index 0000000..7f089c6
@@ -0,0 +1,116 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis <[email protected]> <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/* This is U-boot configuration for Raidsonic ICYBOX NAS4220 board.
+ * More information about this device is available on websites:
+ * http://en.nas-4220.org
+ * http://wiki.gpl-devices.org/wiki/Raidsonic_ICY-BOX_IB-NAS4220-B
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/gemini.h>
+#include <asm-arm/sizes.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM920T			1
+#define CONFIG_GEMINI			1
+#define CONFIG_NAS4220			1
+#undef CONFIG_USE_IRQ
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550		1

include/configs/nas4220.h line 43

Quoted 10 lines

include/configs/nas4220.h new file +10 -0

+#define CONFIG_SYS_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		GEMINI_UART_CLK
+#define CONFIG_SYS_NS16550_COM1		GEMINI_UART_BASE
+#define CONFIG_CONS_INDEX		1
+
+/* Select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+

please include config_cmd_default

Quoted 7 lines

include/configs/nas4220.h new file +7 -0

+/* Command line configuration */
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/

include/configs/nas4220.h line 60

Quoted 10 lines

include/configs/nas4220.h new file +10 -0

+#define CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc */
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+

Best Regards,
J.

Darius Augulis

author

2009-08-03 08:02 UTC #3 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

Quoted 7 lines · Jean-Christophe PLAGNIOL-VILLARD

Quoted 5 lines · Darius Augulis
This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name.
do you boot linux?

yes.

Quoted 33 lines

Quoted 33 lines
Signed-off-by Darius Augulis<[email protected]>
---
  MAINTAINERS                          |    4 +
  MAKEALL                              |    1
  Makefile                             |    3
  board/nas4220/Makefile               |   43 +++++
  board/nas4220/config.mk              |   14 ++
  board/nas4220/lowlevel_init.S        |   96 ++++++++++++
  board/nas4220/nas4220.c              |   75 +++++++++
  board/nas4220/u-boot.lds             |   48 ++++++
  cpu/arm920t/gemini/Makefile          |   38 +++++
  cpu/arm920t/gemini/timer.c           |   93 ++++++++++++
  cpu/arm920t/start.S                  |   11 +
  include/asm-arm/arch-gemini/gemini.h |  271 ++++++++++++++++++++++++++++++++++
  include/configs/nas4220.h            |  116 +++++++++++++++
  13 files changed, 811 insertions(+), 2 deletions(-)
create mode 100644 board/nas4220/Makefile create mode 100644 board/nas4220/config.mk create mode 100644 board/nas4220/lowlevel_init.S create mode 100644 board/nas4220/nas4220.c create mode 100644 board/nas4220/u-boot.lds create mode 100644 cpu/arm920t/gemini/Makefile create mode 100644 cpu/arm920t/gemini/timer.c create mode 100644 include/asm-arm/arch-gemini/gemini.h create mode 100644 include/configs/nas4220.h
MAINTAINERS +0 -0
index 9379c7e..ade43ed 100644
@@ -671,6 +671,10 @@ Sergey Lapin<[email protected]>
 

Quoted 7 lines

Quoted 6 lines

MAINTAINERS +4 -0

  	afeb9260	ARM926EJS (AT91SAM9260 SoC)
 
+Darius Augulis<[email protected]>
+
+	nas4220		CS3516
+

<snip>

fixed alphabetical order.

Quoted 50 lines

board/nas4220/config.mk new file +14 -0

new file mode 100644
index 0000000..5b418ba
@@ -0,0 +1,14 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Author: Darius Augulis<[email protected]>  <[email protected]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+
+TEXT_BASE = 0x10400000
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds

board/nas4220/lowlevel_init.S new file +24 -0

new file mode 100644
index 0000000..d51a5a2
@@ -0,0 +1,96 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include<config.h>
+#include<version.h>
+#include<asm/arch/gemini.h>
+
+#define DRAM_SET_MODE	GEMINI_SET_MODE | GEMINI_MODE_DDRAM | \
+			GEMINI_CAS_3 | GEMINI_BL_4
+#define DRAM_SET_TYPE	GEMINI_BUS_32b | GEMINI_RAM_15x10_16x10
+
+#define DRAM_IOCAP	GEMINI_IOCAP_DRAM_CLOCK | GEMINI_IOCAP_DRAM_DATA | \
+			GEMINI_IOCAP_DRAM_CTRL
+#define DRAM_TIMING	GEMINI_RRATE_AREF8 | GEMINI_RTIMER(195) | \

Quoted 8 lines

board/nas4220/lowlevel_init.S

Quoted 7 lines

board/nas4220/lowlevel_init.S new file +7 -0

+			GEMINI_TRFC(11) | GEMINI_TRAS(6) | GEMINI_TWR(3) | \
+			GEMINI_TRP(3) |	GEMINI_TRCD(3) | GEMINI_TCAS(3)
+#define DRAM_READ_DLL	GEMINI_RDLL_BYTE3(8) | GEMINI_RDLL_BYTE2(8) | \
+			GEMINI_RDLL_BYTE1(8) | GEMINI_RDLL_BYTE0(8)
+#define DRAM_WRITE_DLL	GEMINI_WDLL(26)
+#define DRAM_MEM_CTRL	GEMINI_TRAINING_MODE | GEMINI_DQS_N_FALLING | \
+			GEMINI_BUF_IN_4rd | (1<<  6)

please move this to config header and add CONFIG_SYS_ in the name

ok.

Quoted 9 lines

board/nas4220/lowlevel_init.S line 39
Quoted 8 lines
board/nas4220/lowlevel_init.S new file +8 -0
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* DRAM init */
+	ldr	r0, =GEMINI_DRAM_TYPE		/* DRAM set type */
+	ldr	r1, =DRAM_SET_TYPE		/* 32bit, 64 Mbytes total */
+	str	r1, [r0]
please use write32

ok.

Quoted 11 lines

board/nas4220/lowlevel_init.S line 43
Quoted 4 lines
board/nas4220/lowlevel_init.S new file +4 -0
+
+	ldr	r0, =GEMINI_DRAM_MODE		/* DRAM set mode */
+	ldr	r1, =DRAM_SET_MODE		/* DDRAM, CAS 3, Burst 4 */
+	str	r1, [r0]
ditto etc...
board/nas4220/lowlevel_init.S line 48
Quoted 5 lines
board/nas4220/lowlevel_init.S new file +5 -0
+
+	ldr	r3, =GEMINI_GLOBAL_ID		/* Global ID reg */
+	ldr	r4, [r3]
+	ldr	r5, =0xFF			/* Chip revision mask */
+	and	r4, r4, r5
please create a function for this and call it

it is used only single time. why do you recommend to create function?

Quoted 9 lines

Quoted 8 lines

board/nas4220/lowlevel_init.S new file +8 -0

+	cmp	r4, #0xc0			/* Test if chip rev. is 'c0' */
+	bne	end_prefetch
+
+	/* Fix for rev. 'c0' chip */
+	ldr	r0, =GEMINI_DRAM_AHB_CTRL	/* AHB control */
+	ldr	r5, =GEMINI_WRITE_FLUSH_READ
+	str	r5, [r0]
+

<snip>

Quoted 11 lines

board/nas4220/lowlevel_init.S line 93
Quoted 10 lines
board/nas4220/lowlevel_init.S new file +10 -0
+
+	ldr	r2, =GEMINI_DRAM_BASE
+	mov	r4, #0xa0
+
+read_loop:
+	ldr	r3, [r2]			/* Read data */
+	subs	r4, r4, #1			/* Decrement loop count */
+	bge	read_loop
+
+	bic	r1, r1, #GEMINI_TRAINING_MODE	/* Disable train mode */
what is train mode?

this is not documented. This piece of code is revers-engineered proprietary Storlink boot loader.

Quoted 33 lines

board/nas4220/lowlevel_init.S new file +3 -0

+	str	r1, [r0]
+
+	mov	pc, lr

board/nas4220/nas4220.c new file +24 -0

new file mode 100644
index 0000000..784a249
@@ -0,0 +1,75 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include<common.h>
+#include<asm/arch/gemini.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PINS	(GEMINI_PIN_UART_RX | GEMINI_PIN_UART_TX)
+#define MISC_CTRL	(GEMINI_PAD_SFLASH_DIS | GEMINI_PAD_NAND_DIS)
+
+int board_init(void)
+{
+	/* Bypass UART pins */

Quoted 8 lines

board/nas4220/nas4220.c line 31

Quoted 7 lines

board/nas4220/nas4220.c new file +7 -0

+	GEMINI_GPIO_BYPASS(0) |= UART_PINS;
+
+	/* Enable: parallel flash pins, disable: serial, nand pins */
+	GEMINI_GLOBAL_MISC = MISC_CTRL;
+
+	/* Enable parallel flash direct write mode */
+	GEMINI_FLASH_PAR_ACCESS |= GEMINI_PFLASH_DWR;

please use proper acess : writex

ok.

Quoted 3 lines

please create an api such as at91, davinci and other to manage this kind of config

what api are you talking about? please give some reference.

Quoted 25 lines

board/nas4220/nas4220.c new file +25 -0

+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int cpu_id, cpu_rev, cpu_clk, ahb_clk;
+
+	cpu_id = GEMINI_CHIP_ID;
+	cpu_rev = GEMINI_CHIP_REV;
+	ahb_clk = GEMINI_AHB_CLK;
+
+	switch (GEMINI_CPU_AHB_RATIO) {
+	case 0:
+		cpu_clk = ahb_clk;
+		break;
+	case 1:
+		cpu_clk = (ahb_clk * 3) / 2;
+		break;
+	case 2:
+		cpu_clk = (ahb_clk * 24) / 13;
+		break;
+	case 3:
+		cpu_clk = ahb_clk * 2;
+		break;

Quoted 8 lines

board/nas4220/nas4220.c line 60
Quoted 4 lines
board/nas4220/nas4220.c new file +4 -0
+	default:
+		cpu_clk = 0;
+		break;
+	}
please create a clk api such as at91
please take a look on
cpu/arm926ejs/at91/clock.c
include/asm-arm/arch-at91/clk.h

ok.

Quoted 16 lines

board/nas4220/nas4220.c line 64
Quoted 4 lines
board/nas4220/nas4220.c new file +4 -0
+
+	printf("\nRaidsonic ICYBOX NAS4220 board\n");
+	printf("CPU: Gemini CS%X, REV: %X\n", cpu_id, cpu_rev);
+	printf("CPU Speed: %d MHz, AHB Speed: %d MHz, APB Speed: %d MHz\n\n", cpu_clk / 1000000, ahb_clk / 1000000, ahb_clk / 6000000);
please implement print_cpuinfo
and checkboard
and for clock string conversion please use strmhz
Quoted 9 lines
board/nas4220/nas4220.c new file +9 -0
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+

Quoted 8 lines

board/nas4220/u-boot.lds
Quoted 7 lines
board/nas4220/nas4220.c new file +2 -0
+	return 0;
+}
board/nas4220/u-boot.lds new file +0 -0
new file mode 100644
index 0000000..7d249c3
I do not understand why you need a specific lds?

because of specific and not software controlled boot procedure of Gemini. Please read my comments below.

Quoted 80 lines

Quoted 49 lines

board/nas4220/u-boot.lds new file +48 -0

@@ -0,0 +1,48 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		cpu/arm920t/start.o		(.text)
+		board/nas4220/libnas4220.a	(.text)
+		lib_arm/libarm.a		(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}

<snip>

Quoted 8 lines

+++ b/cpu/arm920t/gemini/timer.c

board/nas4220/u-boot.lds new file +6 -0

@@ -0,0 +1,93 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>

board/nas4220/u-boot.lds line 16

Quoted 10 lines

board/nas4220/u-boot.lds new file +10 -0

+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include<common.h>
+
+#ifdef CONFIG_GEMINI

no need please remove

board/nas4220/u-boot.lds line 26

Quoted 10 lines

board/nas4220/u-boot.lds new file +10 -0

+
+#include<asm/arch/gemini.h>
+
+static ulong gemini_usec;
+static ulong timestamp;
+static ulong extraticks;
+
+int timer_init(void)
+{
+	gemini_usec = GEMINI_APB_CLK / 1000000;

please clk framework as at91

Quoted 5 lines

board/nas4220/u-boot.lds line 29
Quoted 3 lines
board/nas4220/u-boot.lds new file +3 -0
+	timestamp = extraticks = 0;
+
+	GEMINI_TIMER_COUNT(0) = 0;
please use proprer accessor : writex/readx
etc...

ok.

Quoted 49 lines

board/nas4220/u-boot.lds new file +49 -0

+	GEMINI_TIMER_LOAD(0) = 0;
+	GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	GEMINI_TIMER_CR&= ~TIMER_CR_ENABLE(0);
+	GEMINI_TIMER_COUNT(0) = 0x0;
+	GEMINI_TIMER_LOAD(0) = 0x0;
+	GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+	timestamp = extraticks = 0;
+}
+
+unsigned long long get_usecs(void)
+{
+	ulong timenow = GEMINI_TIMER_COUNT(0);
+
+	if (timenow>= timestamp)
+		timestamp += timenow - extraticks;
+	else
+		timestamp += 0xFFFFFFFF - extraticks + timenow;
+	extraticks = timenow;
+
+	return timestamp / gemini_usec;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_usecs() / 1000) - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+void udelay(unsigned long usec)
+{
+	signed long elapsed;
+	ulong timestart = get_usecs();
+
+	do {
+		ulong timenow = get_usecs();
+		elapsed = timenow - timestart;
+	} while (elapsed<  usec);
+}
+

Quoted 8 lines

board/nas4220/u-boot.lds line 85
Quoted 7 lines
board/nas4220/u-boot.lds new file +7 -0
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
please retunr CONFIG_SYS_HZ directly

ok.

Quoted 7 lines

board/nas4220/u-boot.lds line 91
Quoted 6 lines
board/nas4220/u-boot.lds new file +6 -0
+}
+
+void reset_cpu(ulong ignored)
+{
+	GEMINI_GLOBAL_RESET = GEMINI_SOFT_RESET | GEMINI_CPU1_RESET;
+}
please move in reset.c or cpu.c

ok.

Quoted 10 lines

Quoted 10 lines
board/nas4220/u-boot.lds new file +2 -0
+
+#endif /* defined (CONFIG_GEMINI) */
cpu/arm920t/start.S +0 -0
index 475cdaf..761753e 100644
@@ -115,8 +115,10 @@ start_code:
  	orr	r0,r0,#0xd3
  	msr	cpsr,r0
 

Quoted 7 lines

cpu/arm920t/start.S start_code: · line 121
Quoted 6 lines
cpu/arm920t/start.S +4 -2
-	bl coloured_LED_init
-	bl red_LED_on
+#ifndef CONFIG_GEMINI
+	bl	coloured_LED_init
+	bl	red_LED_on
+#endif
no need please remove

these are linked below (TEXT_BASE + 0x800) address. if called before reallocation, they are not accessible because of Gemini specific boot features.

Quoted 7 lines

cpu/arm920t/start.S +0 -0

  #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  	/*

@@ -189,6 +191,11 @@ relocate:				/* relocate U-Boot to RAM	    */
  	sub	r2, r3, r2		/* r2<- size of armboot            */
  	add	r2, r0, r2		/* r2<- source end address         */

Quoted 7 lines

cpu/arm920t/start.S relocate: /* relocate U-Boot to RAM */ · line 197
Quoted 4 lines
cpu/arm920t/start.S +4 -0
+#ifdef CONFIG_GEMINI
+	orr	r0, r0, #CONFIG_SYS_FLASH_BASE
+	orr	r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif
why?
and NACK the start.S MUST be generic
I'll rework the RM9200 code for this too

start.S is not generic already.
and answer is: Gemini does NOT execute code from flash after start up. Some hardware copies 2048 bytes of code from flash to internal SRAM memory. After that it starts execute code from SRAM. We must use position independent code before reallocation. But start.S calls some functions, linked below (TEXT_BASE + 0x800) address.
This copy loop copies code from 0x0 base address, which in case of Gemini is not Flash, but SRAM. I must add additional offset to copy code from Flash. Flash physical base is 0x30000000.
Because of this specific Gemini feature, I must change start.S and create custom linker script.
NOTE: this is not Faraday FA526 core specific, this is Gemini SoC specific. Other SoCs with FA526 core may use different boot approach.

Quoted 26 lines

cpu/arm920t/start.S +1 -0

+
  copy_loop:
  	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
  	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */

include/asm-arm/arch-gemini/gemini.h new file +16 -0

new file mode 100644
index 0000000..e4fa91a
@@ -0,0 +1,271 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASSEMBLY__
+# define REG8(x)	(*(volatile u8 *)(x))
+# define REG16(x)	(*(volatile u16 *)(x))

Quoted 8 lines

include/asm-arm/arch-gemini/gemini.h line 21
Quoted 5 lines
include/asm-arm/arch-gemini/gemini.h new file +5 -0
+# define REG32(x)	(*(volatile u32 *)(x))
+#else
+# define REG8(x)	(x)
+# define REG16(x)	(x)
+# define REG32(x)	(x)
NACK please use propoer accessor
and please split this file by functionnality such as usb, timer etc... and keep it here only global information

ok.

Quoted 43 lines

include/configs/nas4220.h new file +36 -0

new file mode 100644
index 0000000..7f089c6
@@ -0,0 +1,116 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/* This is U-boot configuration for Raidsonic ICYBOX NAS4220 board.
+ * More information about this device is available on websites:
+ * http://en.nas-4220.org
+ * http://wiki.gpl-devices.org/wiki/Raidsonic_ICY-BOX_IB-NAS4220-B
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include<asm/arch/gemini.h>
+#include<asm-arm/sizes.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM920T			1
+#define CONFIG_GEMINI			1
+#define CONFIG_NAS4220			1
+#undef CONFIG_USE_IRQ
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		GEMINI_UART_CLK

Quoted 8 lines

include/configs/nas4220.h line 43

Quoted 7 lines

include/configs/nas4220.h new file +7 -0

+#define CONFIG_SYS_NS16550_COM1		GEMINI_UART_BASE
+#define CONFIG_CONS_INDEX		1
+
+/* Select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+

please include config_cmd_default

I don't have networking implemented yet and some of these commands need it.

Quoted 11 lines

include/configs/nas4220.h new file +11 -0

+/* Command line configuration */
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
+#define CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/

Quoted 8 lines

include/configs/nas4220.h line 60

Quoted 6 lines

include/configs/nas4220.h new file +6 -0

+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc */
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+

Best Regards,
J.

Thanks for review.

Best regards,
Darius A.

Darius Augulis

author

2009-08-03 16:55 UTC #4 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

In reply to Jean-Christophe PLAGNIOL-VILLARD

Quoted 7 lines · Jean-Christophe PLAGNIOL-VILLARD

Quoted 5 lines · Darius Augulis
This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name.
do you boot linux?

yes.

Quoted 33 lines

Quoted 33 lines
Signed-off-by Darius Augulis<[email protected]>
---
  MAINTAINERS                          |    4 +
  MAKEALL                              |    1
  Makefile                             |    3
  board/nas4220/Makefile               |   43 +++++
  board/nas4220/config.mk              |   14 ++
  board/nas4220/lowlevel_init.S        |   96 ++++++++++++
  board/nas4220/nas4220.c              |   75 +++++++++
  board/nas4220/u-boot.lds             |   48 ++++++
  cpu/arm920t/gemini/Makefile          |   38 +++++
  cpu/arm920t/gemini/timer.c           |   93 ++++++++++++
  cpu/arm920t/start.S                  |   11 +
  include/asm-arm/arch-gemini/gemini.h |  271 ++++++++++++++++++++++++++++++++++
  include/configs/nas4220.h            |  116 +++++++++++++++
  13 files changed, 811 insertions(+), 2 deletions(-)
create mode 100644 board/nas4220/Makefile create mode 100644 board/nas4220/config.mk create mode 100644 board/nas4220/lowlevel_init.S create mode 100644 board/nas4220/nas4220.c create mode 100644 board/nas4220/u-boot.lds create mode 100644 cpu/arm920t/gemini/Makefile create mode 100644 cpu/arm920t/gemini/timer.c create mode 100644 include/asm-arm/arch-gemini/gemini.h create mode 100644 include/configs/nas4220.h
MAINTAINERS +0 -0
index 9379c7e..ade43ed 100644
@@ -671,6 +671,10 @@ Sergey Lapin<[email protected]>
 

Quoted 7 lines

Quoted 6 lines

MAINTAINERS +4 -0

  	afeb9260	ARM926EJS (AT91SAM9260 SoC)
 
+Darius Augulis<[email protected]>
+
+	nas4220		CS3516
+

<snip>

fixed alphabetical order.

Quoted 50 lines

board/nas4220/config.mk new file +14 -0

new file mode 100644
index 0000000..5b418ba
@@ -0,0 +1,14 @@
+#
+# (c) Copyright 2009
+# Linkodas, Inc.
+# http://www.linkodas.com
+#
+# Author: Darius Augulis<[email protected]>  <[email protected]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+
+TEXT_BASE = 0x10400000
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds

board/nas4220/lowlevel_init.S new file +24 -0

new file mode 100644
index 0000000..d51a5a2
@@ -0,0 +1,96 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include<config.h>
+#include<version.h>
+#include<asm/arch/gemini.h>
+
+#define DRAM_SET_MODE	GEMINI_SET_MODE | GEMINI_MODE_DDRAM | \
+			GEMINI_CAS_3 | GEMINI_BL_4
+#define DRAM_SET_TYPE	GEMINI_BUS_32b | GEMINI_RAM_15x10_16x10
+
+#define DRAM_IOCAP	GEMINI_IOCAP_DRAM_CLOCK | GEMINI_IOCAP_DRAM_DATA | \
+			GEMINI_IOCAP_DRAM_CTRL
+#define DRAM_TIMING	GEMINI_RRATE_AREF8 | GEMINI_RTIMER(195) | \

Quoted 8 lines

board/nas4220/lowlevel_init.S

Quoted 7 lines

board/nas4220/lowlevel_init.S new file +7 -0

+			GEMINI_TRFC(11) | GEMINI_TRAS(6) | GEMINI_TWR(3) | \
+			GEMINI_TRP(3) |	GEMINI_TRCD(3) | GEMINI_TCAS(3)
+#define DRAM_READ_DLL	GEMINI_RDLL_BYTE3(8) | GEMINI_RDLL_BYTE2(8) | \
+			GEMINI_RDLL_BYTE1(8) | GEMINI_RDLL_BYTE0(8)
+#define DRAM_WRITE_DLL	GEMINI_WDLL(26)
+#define DRAM_MEM_CTRL	GEMINI_TRAINING_MODE | GEMINI_DQS_N_FALLING | \
+			GEMINI_BUF_IN_4rd | (1<<  6)

please move this to config header and add CONFIG_SYS_ in the name

ok.

Quoted 9 lines

board/nas4220/lowlevel_init.S line 39
Quoted 8 lines
board/nas4220/lowlevel_init.S new file +8 -0
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* DRAM init */
+	ldr	r0, =GEMINI_DRAM_TYPE		/* DRAM set type */
+	ldr	r1, =DRAM_SET_TYPE		/* 32bit, 64 Mbytes total */
+	str	r1, [r0]
please use write32

ok.

Quoted 11 lines

board/nas4220/lowlevel_init.S line 43
Quoted 4 lines
board/nas4220/lowlevel_init.S new file +4 -0
+
+	ldr	r0, =GEMINI_DRAM_MODE		/* DRAM set mode */
+	ldr	r1, =DRAM_SET_MODE		/* DDRAM, CAS 3, Burst 4 */
+	str	r1, [r0]
ditto etc...
board/nas4220/lowlevel_init.S line 48
Quoted 5 lines
board/nas4220/lowlevel_init.S new file +5 -0
+
+	ldr	r3, =GEMINI_GLOBAL_ID		/* Global ID reg */
+	ldr	r4, [r3]
+	ldr	r5, =0xFF			/* Chip revision mask */
+	and	r4, r4, r5
please create a function for this and call it

it is used only single time. why do you recommend to create function?

Quoted 9 lines

Quoted 8 lines

board/nas4220/lowlevel_init.S new file +8 -0

+	cmp	r4, #0xc0			/* Test if chip rev. is 'c0' */
+	bne	end_prefetch
+
+	/* Fix for rev. 'c0' chip */
+	ldr	r0, =GEMINI_DRAM_AHB_CTRL	/* AHB control */
+	ldr	r5, =GEMINI_WRITE_FLUSH_READ
+	str	r5, [r0]
+

<snip>

Quoted 11 lines

board/nas4220/lowlevel_init.S line 93
Quoted 10 lines
board/nas4220/lowlevel_init.S new file +10 -0
+
+	ldr	r2, =GEMINI_DRAM_BASE
+	mov	r4, #0xa0
+
+read_loop:
+	ldr	r3, [r2]			/* Read data */
+	subs	r4, r4, #1			/* Decrement loop count */
+	bge	read_loop
+
+	bic	r1, r1, #GEMINI_TRAINING_MODE	/* Disable train mode */
what is train mode?

this is not documented. This piece of code is revers-engineered proprietary Storlink boot loader.

Quoted 33 lines

board/nas4220/lowlevel_init.S new file +3 -0

+	str	r1, [r0]
+
+	mov	pc, lr

board/nas4220/nas4220.c new file +24 -0

new file mode 100644
index 0000000..784a249
@@ -0,0 +1,75 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include<common.h>
+#include<asm/arch/gemini.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PINS	(GEMINI_PIN_UART_RX | GEMINI_PIN_UART_TX)
+#define MISC_CTRL	(GEMINI_PAD_SFLASH_DIS | GEMINI_PAD_NAND_DIS)
+
+int board_init(void)
+{
+	/* Bypass UART pins */

Quoted 8 lines

board/nas4220/nas4220.c line 31

Quoted 7 lines

board/nas4220/nas4220.c new file +7 -0

+	GEMINI_GPIO_BYPASS(0) |= UART_PINS;
+
+	/* Enable: parallel flash pins, disable: serial, nand pins */
+	GEMINI_GLOBAL_MISC = MISC_CTRL;
+
+	/* Enable parallel flash direct write mode */
+	GEMINI_FLASH_PAR_ACCESS |= GEMINI_PFLASH_DWR;

please use proper acess : writex

ok.

Quoted 3 lines

please create an api such as at91, davinci and other to manage this kind of config

what api are you talking about? please give some reference.

Quoted 25 lines

board/nas4220/nas4220.c new file +25 -0

+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int cpu_id, cpu_rev, cpu_clk, ahb_clk;
+
+	cpu_id = GEMINI_CHIP_ID;
+	cpu_rev = GEMINI_CHIP_REV;
+	ahb_clk = GEMINI_AHB_CLK;
+
+	switch (GEMINI_CPU_AHB_RATIO) {
+	case 0:
+		cpu_clk = ahb_clk;
+		break;
+	case 1:
+		cpu_clk = (ahb_clk * 3) / 2;
+		break;
+	case 2:
+		cpu_clk = (ahb_clk * 24) / 13;
+		break;
+	case 3:
+		cpu_clk = ahb_clk * 2;
+		break;

Quoted 8 lines

board/nas4220/nas4220.c line 60
Quoted 4 lines
board/nas4220/nas4220.c new file +4 -0
+	default:
+		cpu_clk = 0;
+		break;
+	}
please create a clk api such as at91
please take a look on
cpu/arm926ejs/at91/clock.c
include/asm-arm/arch-at91/clk.h

ok.

Quoted 16 lines

board/nas4220/nas4220.c line 64
Quoted 4 lines
board/nas4220/nas4220.c new file +4 -0
+
+	printf("\nRaidsonic ICYBOX NAS4220 board\n");
+	printf("CPU: Gemini CS%X, REV: %X\n", cpu_id, cpu_rev);
+	printf("CPU Speed: %d MHz, AHB Speed: %d MHz, APB Speed: %d MHz\n\n", cpu_clk / 1000000, ahb_clk / 1000000, ahb_clk / 6000000);
please implement print_cpuinfo
and checkboard
and for clock string conversion please use strmhz
Quoted 9 lines
board/nas4220/nas4220.c new file +9 -0
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+

Quoted 8 lines

board/nas4220/u-boot.lds
Quoted 7 lines
board/nas4220/nas4220.c new file +2 -0
+	return 0;
+}
board/nas4220/u-boot.lds new file +0 -0
new file mode 100644
index 0000000..7d249c3
I do not understand why you need a specific lds?

because of specific and not software controlled boot procedure of Gemini. Please read my comments below.

Quoted 80 lines

Quoted 49 lines

board/nas4220/u-boot.lds new file +48 -0

@@ -0,0 +1,48 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		cpu/arm920t/start.o		(.text)
+		board/nas4220/libnas4220.a	(.text)
+		lib_arm/libarm.a		(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}

<snip>

Quoted 8 lines

+++ b/cpu/arm920t/gemini/timer.c

board/nas4220/u-boot.lds new file +6 -0

@@ -0,0 +1,93 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>

board/nas4220/u-boot.lds line 16

Quoted 10 lines

board/nas4220/u-boot.lds new file +10 -0

+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include<common.h>
+
+#ifdef CONFIG_GEMINI

no need please remove

board/nas4220/u-boot.lds line 26

Quoted 10 lines

board/nas4220/u-boot.lds new file +10 -0

+
+#include<asm/arch/gemini.h>
+
+static ulong gemini_usec;
+static ulong timestamp;
+static ulong extraticks;
+
+int timer_init(void)
+{
+	gemini_usec = GEMINI_APB_CLK / 1000000;

please clk framework as at91

Quoted 5 lines

board/nas4220/u-boot.lds line 29
Quoted 3 lines
board/nas4220/u-boot.lds new file +3 -0
+	timestamp = extraticks = 0;
+
+	GEMINI_TIMER_COUNT(0) = 0;
please use proprer accessor : writex/readx
etc...

ok.

Quoted 49 lines

board/nas4220/u-boot.lds new file +49 -0

+	GEMINI_TIMER_LOAD(0) = 0;
+	GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	GEMINI_TIMER_CR&= ~TIMER_CR_ENABLE(0);
+	GEMINI_TIMER_COUNT(0) = 0x0;
+	GEMINI_TIMER_LOAD(0) = 0x0;
+	GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0);
+
+	timestamp = extraticks = 0;
+}
+
+unsigned long long get_usecs(void)
+{
+	ulong timenow = GEMINI_TIMER_COUNT(0);
+
+	if (timenow>= timestamp)
+		timestamp += timenow - extraticks;
+	else
+		timestamp += 0xFFFFFFFF - extraticks + timenow;
+	extraticks = timenow;
+
+	return timestamp / gemini_usec;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_usecs() / 1000) - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+void udelay(unsigned long usec)
+{
+	signed long elapsed;
+	ulong timestart = get_usecs();
+
+	do {
+		ulong timenow = get_usecs();
+		elapsed = timenow - timestart;
+	} while (elapsed<  usec);
+}
+

Quoted 8 lines

board/nas4220/u-boot.lds line 85
Quoted 7 lines
board/nas4220/u-boot.lds new file +7 -0
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
please retunr CONFIG_SYS_HZ directly

ok.

Quoted 7 lines

board/nas4220/u-boot.lds line 91
Quoted 6 lines
board/nas4220/u-boot.lds new file +6 -0
+}
+
+void reset_cpu(ulong ignored)
+{
+	GEMINI_GLOBAL_RESET = GEMINI_SOFT_RESET | GEMINI_CPU1_RESET;
+}
please move in reset.c or cpu.c

ok.

Quoted 10 lines

Quoted 10 lines
board/nas4220/u-boot.lds new file +2 -0
+
+#endif /* defined (CONFIG_GEMINI) */
cpu/arm920t/start.S +0 -0
index 475cdaf..761753e 100644
@@ -115,8 +115,10 @@ start_code:
  	orr	r0,r0,#0xd3
  	msr	cpsr,r0
 

Quoted 7 lines

cpu/arm920t/start.S start_code: · line 121
Quoted 6 lines
cpu/arm920t/start.S +4 -2
-	bl coloured_LED_init
-	bl red_LED_on
+#ifndef CONFIG_GEMINI
+	bl	coloured_LED_init
+	bl	red_LED_on
+#endif
no need please remove

these are linked below (TEXT_BASE + 0x800) address. if called before reallocation, they are not accessible because of Gemini specific boot features.

Quoted 7 lines

cpu/arm920t/start.S +0 -0

  #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  	/*

@@ -189,6 +191,11 @@ relocate:				/* relocate U-Boot to RAM	    */
  	sub	r2, r3, r2		/* r2<- size of armboot            */
  	add	r2, r0, r2		/* r2<- source end address         */

Quoted 7 lines

cpu/arm920t/start.S relocate: /* relocate U-Boot to RAM */ · line 197
Quoted 4 lines
cpu/arm920t/start.S +4 -0
+#ifdef CONFIG_GEMINI
+	orr	r0, r0, #CONFIG_SYS_FLASH_BASE
+	orr	r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif
why?
and NACK the start.S MUST be generic
I'll rework the RM9200 code for this too

Quoted 26 lines

cpu/arm920t/start.S +1 -0

+
  copy_loop:
  	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
  	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */

include/asm-arm/arch-gemini/gemini.h new file +16 -0

new file mode 100644
index 0000000..e4fa91a
@@ -0,0 +1,271 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASSEMBLY__
+# define REG8(x)	(*(volatile u8 *)(x))
+# define REG16(x)	(*(volatile u16 *)(x))

Quoted 8 lines

include/asm-arm/arch-gemini/gemini.h line 21
Quoted 5 lines
include/asm-arm/arch-gemini/gemini.h new file +5 -0
+# define REG32(x)	(*(volatile u32 *)(x))
+#else
+# define REG8(x)	(x)
+# define REG16(x)	(x)
+# define REG32(x)	(x)
NACK please use propoer accessor
and please split this file by functionnality such as usb, timer etc... and keep it here only global information

ok.

Quoted 43 lines

include/configs/nas4220.h new file +36 -0

new file mode 100644
index 0000000..7f089c6
@@ -0,0 +1,116 @@
+/*
+ * (c) Copyright 2009
+ * Linkodas, Inc.
+ * http://www.linkodas.com
+ *
+ * Author: Darius Augulis<[email protected]>  <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/* This is U-boot configuration for Raidsonic ICYBOX NAS4220 board.
+ * More information about this device is available on websites:
+ * http://en.nas-4220.org
+ * http://wiki.gpl-devices.org/wiki/Raidsonic_ICY-BOX_IB-NAS4220-B
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include<asm/arch/gemini.h>
+#include<asm-arm/sizes.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM920T			1
+#define CONFIG_GEMINI			1
+#define CONFIG_NAS4220			1
+#undef CONFIG_USE_IRQ
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		GEMINI_UART_CLK

Quoted 8 lines

include/configs/nas4220.h line 43

Quoted 7 lines

include/configs/nas4220.h new file +7 -0

+#define CONFIG_SYS_NS16550_COM1		GEMINI_UART_BASE
+#define CONFIG_CONS_INDEX		1
+
+/* Select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+

please include config_cmd_default

I don't have networking implemented yet and some of these commands need it.

Quoted 11 lines

include/configs/nas4220.h new file +11 -0

+/* Command line configuration */
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
+#define CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/

Quoted 8 lines

include/configs/nas4220.h line 60

Quoted 6 lines

include/configs/nas4220.h new file +6 -0

+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc */
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+

Best Regards,
J.

Thanks for review.

Best regards,
Darius A.

Jean-Christophe PLAGNIOL-VILLARD

2009-08-04 19:41 UTC #5 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

Quoted 10 lines · Darius Augulis

Quoted 7 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines · Darius Augulis
This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name.
do you boot linux?
yes.

so why don't you define a machine id?
on arm you need to pass it to linux

Quoted 29 lines

Quoted 29 lines
Quoted 18 lines
Signed-off-by Darius Augulis<[email protected]>
---
  MAINTAINERS                          |    4 +
  MAKEALL                              |    1
  Makefile                             |    3
  board/nas4220/Makefile               |   43 +++++
  board/nas4220/config.mk              |   14 ++
  board/nas4220/lowlevel_init.S        |   96 ++++++++++++
  board/nas4220/nas4220.c              |   75 +++++++++
  board/nas4220/u-boot.lds             |   48 ++++++
  cpu/arm920t/gemini/Makefile          |   38 +++++
  cpu/arm920t/gemini/timer.c           |   93 ++++++++++++
  cpu/arm920t/start.S                  |   11 +
  include/asm-arm/arch-gemini/gemini.h |  271 ++++++++++++++++++++++++++++++++++
  include/configs/nas4220.h            |  116 +++++++++++++++
  13 files changed, 811 insertions(+), 2 deletions(-)
Quoted 10 lines
create mode 100644 board/nas4220/Makefile create mode 100644 board/nas4220/config.mk create mode 100644 board/nas4220/lowlevel_init.S create mode 100644 board/nas4220/nas4220.c create mode 100644 board/nas4220/u-boot.lds create mode 100644 cpu/arm920t/gemini/Makefile create mode 100644 cpu/arm920t/gemini/timer.c create mode 100644 include/asm-arm/arch-gemini/gemini.h create mode 100644 include/configs/nas4220.h
ditto etc...

Quoted 8 lines

Quoted 6 lines
board/nas4220/lowlevel_init.S line 48
Quoted 5 lines
board/nas4220/lowlevel_init.S new file +5 -0
+
+	ldr	r3, =GEMINI_GLOBAL_ID		/* Global ID reg */
+	ldr	r4, [r3]
+	ldr	r5, =0xFF			/* Chip revision mask */
+	and	r4, r4, r5
please create a function for this and call it
it is used only single time. why do you recommend to create function?

because it will interesting to have it in the board info and a lot's of time you will need it in drivers

Quoted 22 lines

Quoted 10 lines
Quoted 9 lines
board/nas4220/lowlevel_init.S new file +8 -0
+	cmp	r4, #0xc0			/* Test if chip rev. is 'c0' */
+	bne	end_prefetch
+
+	/* Fix for rev. 'c0' chip */
+	ldr	r0, =GEMINI_DRAM_AHB_CTRL	/* AHB control */
+	ldr	r5, =GEMINI_WRITE_FLUSH_READ
+	str	r5, [r0]
+
<snip>
Quoted 11 lines
board/nas4220/lowlevel_init.S line 93
Quoted 10 lines
board/nas4220/lowlevel_init.S new file +10 -0
+
+	ldr	r2, =GEMINI_DRAM_BASE
+	mov	r4, #0xa0
+
+read_loop:
+	ldr	r3, [r2]			/* Read data */
+	subs	r4, r4, #1			/* Decrement loop count */
+	bge	read_loop
+
+	bic	r1, r1, #GEMINI_TRAINING_MODE	/* Disable train mode */
what is train mode?

Quoted 2 lines

this is not documented. This piece of code is revers-engineered proprietary Storlink boot loader.

so please put a comment in the code

Quoted 10 lines

Quoted 8 lines
board/nas4220/lowlevel_init.S line 96
Quoted 4 lines
board/nas4220/lowlevel_init.S new file +3 -0
+	str	r1, [r0]
+
+	mov	pc, lr
please create an api such as at91, davinci and other to manage this kind of config
what api are you talking about? please give some reference.

take a look an at91 in cpu/arm926ejs/at91/
for each soc you have hw init

Quoted 11 lines

Quoted 8 lines
board/nas4220/u-boot.lds
Quoted 7 lines
board/nas4220/u-boot.lds new file +0 -0
new file mode 100644
index 0000000..7d249c3
I do not understand why you need a specific lds?
because of specific and not software controlled boot procedure of Gemini. Please read my comments below.

this is steal not clear why you need
this

Quoted 6 lines

Quoted 6 lines
board/nas4220/u-boot.lds line 28
Quoted 6 lines
board/nas4220/u-boot.lds new file +6 -0
+	{
+		cpu/arm920t/start.o		(.text)
+		board/nas4220/libnas4220.a	(.text)
+		lib_arm/libarm.a		(.text)
+		*(.text)
+	}

and not

	{
		cpu/arm926ejs/start.o	(.text)
		*(.text)
	}

Quoted 4 lines

Quoted 4 lines
Quoted 4 lines
board/nas4220/u-boot.lds new file +4 -0
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+

<snip>

Quoted 38 lines

Quoted 11 lines
Quoted 11 lines
board/nas4220/u-boot.lds new file +2 -0
+
+#endif /* defined (CONFIG_GEMINI) */
cpu/arm920t/start.S +0 -0
index 475cdaf..761753e 100644
@@ -115,8 +115,10 @@ start_code:
  	orr	r0,r0,#0xd3
  	msr	cpsr,r0
 
Quoted 7 lines
cpu/arm920t/start.S start_code: · line 121
Quoted 6 lines
cpu/arm920t/start.S +4 -2
-	bl coloured_LED_init
-	bl red_LED_on
+#ifndef CONFIG_GEMINI
+	bl	coloured_LED_init
+	bl	red_LED_on
+#endif
no need please remove
these are linked below (TEXT_BASE + 0x800) address. if called before reallocation, they are not accessible because of Gemini specific boot features.
Quoted 7 lines
Quoted 7 lines
cpu/arm920t/start.S +0 -0
  #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  	/*
@@ -189,6 +191,11 @@ relocate:				/* relocate U-Boot to RAM	    */
  	sub	r2, r3, r2		/* r2<- size of armboot            */
  	add	r2, r0, r2		/* r2<- source end address         */
 
Quoted 7 lines
cpu/arm920t/start.S relocate: /* relocate U-Boot to RAM */ · line 197
Quoted 4 lines
cpu/arm920t/start.S +4 -0
+#ifdef CONFIG_GEMINI
+	orr	r0, r0, #CONFIG_SYS_FLASH_BASE
+	orr	r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif
why?
and NACK the start.S MUST be generic
I'll rework the RM9200 code for this too

Quoted 1 line

start.S is not generic already.

but it must not become more board specific with ifdef

Quoted 4 lines

and answer is: Gemini does NOT execute code from flash after start up. Some hardware copies 2048 bytes of code from flash to internal SRAM memory. After that it starts execute code from SRAM. We must use position independent code before reallocation. But start.S calls some functions,

Quoted 8 lines

linked below (TEXT_BASE + 0x800) address.
This copy loop copies code from 0x0 base address, which in case of Gemini is not Flash, but SRAM. I must add additional offset to copy code from Flash. Flash physical base is 0x30000000.
Because of this specific Gemini feature, I must change start.S and create custom linker script.
NOTE: this is not Faraday FA526 core specific, this is Gemini SoC specific. Other SoCs with FA526 core may use different boot approach.

so it will be better to use a PRELOADER such as we do for nand or onenand which will boot u-boot

Quoted 15 lines

Quoted 6 lines

cpu/arm920t/start.S +6 -0

+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		GEMINI_UART_CLK

Quoted 8 lines

cpu/arm920t/start.S

Quoted 7 lines

cpu/arm920t/start.S +7 -0

+#define CONFIG_SYS_NS16550_COM1		GEMINI_UART_BASE
+#define CONFIG_CONS_INDEX		1
+
+/* Select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+

please include config_cmd_default

Quoted 1 line

I don't have networking implemented yet and some of these commands need it.

so just include the config_cmd_default and undef what you do not support

Best Regards,
J.

Darius Augulis

author

2009-08-04 20:22 UTC #6 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

Quoted 8 lines · Jean-Christophe PLAGNIOL-VILLARD

Quoted 7 lines · Darius Augulis
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines · Darius Augulis
This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name.

Quoted 4 lines

Quoted 2 lines
Quoted 1 line
do you boot linux?
yes.
so why don't you define a machine id?
on arm you need to pass it to linux

oh yes, I know that. it's only RFC patch, I will finish all similar stuff later.

Quoted 57 lines

Quoted 27 lines
Quoted 27 lines
Quoted 27 lines
Signed-off-by Darius Augulis<[email protected]>
---
   MAINTAINERS                          |    4 +
   MAKEALL                              |    1
   Makefile                             |    3
   board/nas4220/Makefile               |   43 +++++
   board/nas4220/config.mk              |   14 ++
   board/nas4220/lowlevel_init.S        |   96 ++++++++++++
   board/nas4220/nas4220.c              |   75 +++++++++
   board/nas4220/u-boot.lds             |   48 ++++++
   cpu/arm920t/gemini/Makefile          |   38 +++++
   cpu/arm920t/gemini/timer.c           |   93 ++++++++++++
   cpu/arm920t/start.S                  |   11 +
   include/asm-arm/arch-gemini/gemini.h |  271 ++++++++++++++++++++++++++++++++++
   include/configs/nas4220.h            |  116 +++++++++++++++
   13 files changed, 811 insertions(+), 2 deletions(-)
create mode 100644 board/nas4220/Makefile create mode 100644 board/nas4220/config.mk create mode 100644 board/nas4220/lowlevel_init.S create mode 100644 board/nas4220/nas4220.c create mode 100644 board/nas4220/u-boot.lds create mode 100644 cpu/arm920t/gemini/Makefile create mode 100644 cpu/arm920t/gemini/timer.c create mode 100644 include/asm-arm/arch-gemini/gemini.h create mode 100644 include/configs/nas4220.h
Quoted 8 lines
Quoted 7 lines
ditto etc...
board/nas4220/lowlevel_init.S line 48
Quoted 5 lines
board/nas4220/lowlevel_init.S new file +5 -0
+
+	ldr	r3, =GEMINI_GLOBAL_ID		/* Global ID reg */
+	ldr	r4, [r3]
+	ldr	r5, =0xFF			/* Chip revision mask */
+	and	r4, r4, r5
please create a function for this and call it
it is used only single time. why do you recommend to create function?
because it will interesting to have it in the board info and a lot's of time you will need it in drivers
Quoted 20 lines
Quoted 20 lines
Quoted 8 lines
board/nas4220/lowlevel_init.S new file +8 -0
+	cmp	r4, #0xc0			/* Test if chip rev. is 'c0' */
+	bne	end_prefetch
+
+	/* Fix for rev. 'c0' chip */
+	ldr	r0, =GEMINI_DRAM_AHB_CTRL	/* AHB control */
+	ldr	r5, =GEMINI_WRITE_FLUSH_READ
+	str	r5, [r0]
+
<snip>
board/nas4220/lowlevel_init.S line 93
Quoted 10 lines
board/nas4220/lowlevel_init.S new file +10 -0
+
+	ldr	r2, =GEMINI_DRAM_BASE
+	mov	r4, #0xa0
+
+read_loop:
+	ldr	r3, [r2]			/* Read data */
+	subs	r4, r4, #1			/* Decrement loop count */
+	bge	read_loop
+
+	bic	r1, r1, #GEMINI_TRAINING_MODE	/* Disable train mode */
what is train mode?

Quoted 3 lines

Quoted 2 lines
this is not documented. This piece of code is revers-engineered proprietary Storlink boot loader.
so please put a comment in the code

ok.

Quoted 8 lines

Quoted 6 lines
Quoted 5 lines
board/nas4220/lowlevel_init.S line 96
Quoted 3 lines
board/nas4220/lowlevel_init.S new file +3 -0
+	str	r1, [r0]
+
+	mov	pc, lr
please create an api such as at91, davinci and other to manage this kind of config
what api are you talking about? please give some reference.
take a look an at91 in cpu/arm926ejs/at91/
for each soc you have hw init

ok, I've already implemented this.

Quoted 18 lines

Quoted 9 lines
Quoted 7 lines
board/nas4220/u-boot.lds
Quoted 6 lines
board/nas4220/u-boot.lds new file +0 -0
new file mode 100644
index 0000000..7d249c3
I do not understand why you need a specific lds?
because of specific and not software controlled boot procedure of Gemini. Please read my comments below.
this is steal not clear why you need
this
Quoted 6 lines
Quoted 6 lines
board/nas4220/u-boot.lds line 28
Quoted 6 lines
board/nas4220/u-boot.lds new file +6 -0
+	{
+		cpu/arm920t/start.o		(.text)
+		board/nas4220/libnas4220.a	(.text)
+		lib_arm/libarm.a		(.text)
+		*(.text)
+	}
and not

Quoted 4 lines

	{
		cpu/arm926ejs/start.o	(.text)
		*(.text)
	}

Gemini has arm920t (FA526) core.
I need libarm linked above 0x800.

Quoted 39 lines

Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
board/nas4220/u-boot.lds new file +4 -0
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
<snip>
Quoted 34 lines
Quoted 10 lines
Quoted 10 lines
board/nas4220/u-boot.lds new file +2 -0
+
+#endif /* defined (CONFIG_GEMINI) */
cpu/arm920t/start.S +0 -0
index 475cdaf..761753e 100644
@@ -115,8 +115,10 @@ start_code:
   	orr	r0,r0,#0xd3
   	msr	cpsr,r0
 
Quoted 7 lines
cpu/arm920t/start.S start_code: · line 121
Quoted 6 lines
cpu/arm920t/start.S +4 -2
-	bl coloured_LED_init
-	bl red_LED_on
+#ifndef CONFIG_GEMINI
+	bl	coloured_LED_init
+	bl	red_LED_on
+#endif
no need please remove
these are linked below (TEXT_BASE + 0x800) address. if called before reallocation, they are not accessible because of Gemini specific boot features.
Quoted 13 lines
cpu/arm920t/start.S relocate: /* relocate U-Boot to RAM */ · line 197
Quoted 10 lines
cpu/arm920t/start.S +4 -0
   #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
   	/*
@@ -189,6 +191,11 @@ relocate:				/* relocate U-Boot to RAM	    */
   	sub	r2, r3, r2		/* r2<- size of armboot            */
   	add	r2, r0, r2		/* r2<- source end address         */
 
+#ifdef CONFIG_GEMINI
+	orr	r0, r0, #CONFIG_SYS_FLASH_BASE
+	orr	r2, r2, #CONFIG_SYS_FLASH_BASE
+#endif
why?
and NACK the start.S MUST be generic
I'll rework the RM9200 code for this too

Quoted 2 lines

Quoted 1 line
start.S is not generic already.
but it must not become more board specific with ifdef

what could you suggest instead this?

Quoted 13 lines

Quoted 13 lines
and answer is: Gemini does NOT execute code from flash after start up. Some hardware copies 2048 bytes of code from flash to internal SRAM memory. After that it starts execute code from SRAM. We must use position independent code before reallocation. But start.S calls some functions, linked below (TEXT_BASE + 0x800) address.
This copy loop copies code from 0x0 base address, which in case of Gemini is not Flash, but SRAM. I must add additional offset to copy code from Flash. Flash physical base is 0x30000000.
Because of this specific Gemini feature, I must change start.S and create custom linker script.
NOTE: this is not Faraday FA526 core specific, this is Gemini SoC specific. Other SoCs with FA526 core may use different boot approach.

Quoted 2 lines

so it will be better to use a PRELOADER such as we do for nand or onenand which will boot u-boot

you suggest to use two separate boot loaders? this is bad idea. it's not better for users. they will have problems with firmware upgrade and similar.
Problem is solved with several code lines in u-boot, and it is working. Additional package (preloader) increases system complexity and decreases reliability.
btw, It is not attractive to use u-boot if I need additional loader.

Quoted 20 lines

Quoted 15 lines
Quoted 15 lines
Quoted 4 lines
cpu/arm920t/start.S +3 -0
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550		1
cpu/arm920t/start.S relocate: /* relocate U-Boot to RAM */
Quoted 10 lines
cpu/arm920t/start.S +10 -0
+#define CONFIG_SYS_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		GEMINI_UART_CLK
+#define CONFIG_SYS_NS16550_COM1		GEMINI_UART_BASE
+#define CONFIG_CONS_INDEX		1
+
+/* Select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
please include config_cmd_default
Quoted 1 line
I don't have networking implemented yet and some of these commands need it.
so just include the config_cmd_default and undef what you do not support
Best Regards,
J.

Jean-Christophe PLAGNIOL-VILLARD

2009-08-05 19:50 UTC #7 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

Quoted 7 lines

Quoted 5 lines
Quoted 4 lines
Quoted 3 lines
why?
and NACK the start.S MUST be generic
I'll rework the RM9200 code for this too
start.S is not generic already.
but it must not become more board specific with ifdef
what could you suggest instead this?

in your case the prelooder

Quoted 14 lines

Quoted 14 lines
Quoted 14 lines
and answer is: Gemini does NOT execute code from flash after start up. Some hardware copies 2048 bytes of code from flash to internal SRAM memory. After that it starts execute code from SRAM. We must use position independent code before reallocation. But start.S calls some functions, linked below (TEXT_BASE + 0x800) address.
This copy loop copies code from 0x0 base address, which in case of Gemini is not Flash, but SRAM. I must add additional offset to copy code from Flash. Flash physical base is 0x30000000.
Because of this specific Gemini feature, I must change start.S and create custom linker script.
NOTE: this is not Faraday FA526 core specific, this is Gemini SoC specific. Other SoCs with FA526 core may use different boot approach.

Quoted 4 lines

Quoted 2 lines
so it will be better to use a PRELOADER such as we do for nand or onenand which will boot u-boot
you suggest to use two separate boot loaders? this is bad idea.

it does not

Quoted 2 lines

it's not better for users. they will have problems with firmware upgrade and similar.

Quoted 4 lines

Problem is solved with several code lines in u-boot, and it is working. Additional package (preloader) increases system complexity and decreases reliability.
btw, It is not attractive to use u-boot if I need additional loader.

please take a look on the nand_spl and onenand_ipl
the preloader is part of u-boot source
when you build you u-boot it will result to only one binary with first the preloder and then concat u-boot itself
we do this for nand and onenand controler which are allow to download in internal SRAM or so a small piece of code as example on samsung soc for onenand only 2KiB of code

and with what you describe it's clearly the same for you here

Best Regards,
J.

Wolfgang Denk

2009-08-04 20:40 UTC #8 lore raw

RFC PATCH 1/1 Add support for Raidsonic ICYBOX NAS4220 board

In reply to Jean-Christophe PLAGNIOL-VILLARD

Dear Jean-Christophe PLAGNIOL-VILLARD,

Quoted 1 line · In message <[email protected]> you wrote:

...

Quoted 10 lines

Quoted 8 lines
Quoted 6 lines
board/nas4220/lowlevel_init.S line 48
Quoted 5 lines
board/nas4220/lowlevel_init.S new file +5 -0
+
+	ldr	r3, =GEMINI_GLOBAL_ID		/* Global ID reg */
+	ldr	r4, [r3]
+	ldr	r5, =0xFF			/* Chip revision mask */
+	and	r4, r4, r5
please create a function for this and call it
it is used only single time. why do you recommend to create function?
because it will interesting to have it in the board info and a lot's of time you will need it in drivers

Obviously this is not the case - he wrote: "used only single time".

Making it a function makes no sense to me then - especially since we're just talking about 4 LOC...

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"It is better to have tried and failed than to have  failed  to  try,
but the result's the same."                           - Mike Dennison