Skip to contentSkip to conversation

Port malta interrupt changes (GIC, GCMP) from linux-mti

PATCH New Raghu Gandham 1 participant 4 messages Jul 10, 2009 MIPS

lore
Share & tools
lore

Raghu Gandham

author
#0 lore raw

cover Port malta interrupt changes (GIC, GCMP) from linux-mti

The following series of patches port the changes in linux-mti.git repository to the head of tree.

---

Chris Dearman (2):
Port of GIC related changes from MTI branch. Fix accesses to device registers on MIPS boards

Jaidev Patwardhan (1):
Avoid accessing GCMP registers when they are not present

 arch/mips/Kconfig                 |    1 
 arch/mips/include/asm/gcmpregs.h  |   18 ++--
 arch/mips/include/asm/gic.h       |  188 ++++---------------------------------
 arch/mips/kernel/irq-gic.c        |  116 +++++++++--------------
 arch/mips/kernel/setup.c          |    3 -
 arch/mips/kernel/smp-mt.c         |   10 ++
 arch/mips/kernel/vpe.c            |    3 -
 arch/mips/mti-malta/malta-amon.c  |    7 +
 arch/mips/mti-malta/malta-int.c   |  119 ++++++++++++++---------
 arch/mips/mti-malta/malta-pci.c   |   14 ++-
 arch/mips/mti-malta/malta-setup.c |  111 ++++++++++++++++++++++
 11 files changed, 286 insertions(+), 304 deletions(-)
author
#1 lore raw

PATCH 1/3 Fix accesses to device registers on MIPS boards

From: Chris Dearman <[email protected]>

This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode)

Signed-off-by Chris Dearman ([email protected])

---

 arch/mips/mti-malta/malta-int.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/mips/mti-malta/malta-int.c +1 -1
index 3e0a9b3..e568d0d 100644
@@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void)
 		dummy = BONITO_PCIMAP_CFG;
 		iob();    /* sync */
 
-		irq = readl((u32 *)_pcictrl_bonito_pcicfg);
+		irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
 		iob();    /* sync */
 		irq &= 0xff;
 		BONITO_PCIMAP_CFG = 0;
author
#2 lore raw

PATCH 2/3 Port of GIC related changes from MTI branch.

In reply to Raghu Gandham

From: Chris Dearman <[email protected]>

Signed-off-by Chris Dearman <[email protected]>

---

 arch/mips/include/asm/gcmpregs.h |   18 ++--
 arch/mips/include/asm/gic.h      |  188 ++++----------------------------------
 arch/mips/kernel/irq-gic.c       |  116 +++++++++--------------
 arch/mips/mti-malta/malta-int.c  |  101 ++++++++++++--------
 arch/mips/mti-malta/malta-pci.c  |   14 ++-
 5 files changed, 143 insertions(+), 294 deletions(-)
arch/mips/include/asm/gcmpregs.h +12 -6
index 36fd969..c0cf76a 100644
@@ -19,15 +19,20 @@
 #define GCMP_GDB_OFS		0x8000 /* Global Debug Block */
 
 /* Offsets to individual GCMP registers from GCMP base */
-#define GCMPOFS(block, tag, reg)	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFS(block, tag, reg)	\
+	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFSn(block, tag, reg, n) \
+	(GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
 
 #define GCMPGCBOFS(reg)		GCMPOFS(GCB, GCB, reg)
+#define GCMPGCBOFSn(reg, n)	GCMPOFSn(GCB, GCB, reg, n)
 #define GCMPCLCBOFS(reg)	GCMPOFS(CLCB, CCB, reg)
 #define GCMPCOCBOFS(reg)	GCMPOFS(COCB, CCB, reg)
 #define GCMPGDBOFS(reg)		GCMPOFS(GDB, GDB, reg)
 
 /* GCMP register access */
 #define GCMPGCB(reg)			REGP(_gcmp_base, GCMPGCBOFS(reg))
+#define GCMPGCBn(reg, n)               REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
 #define GCMPCLCB(reg)			REGP(_gcmp_base, GCMPCLCBOFS(reg))
 #define GCMPCOCB(reg)			REGP(_gcmp_base, GCMPCOCBOFS(reg))
 #define GCMPGDB(reg)			REGP(_gcmp_base, GCMPGDBOFS(reg))

@@ -49,10 +54,10 @@
 #define  GCMP_GCB_GCMPB_GCMPBASE_MSK	GCMPGCBMSK(GCMPB_GCMPBASE, 17)
 #define  GCMP_GCB_GCMPB_CMDEFTGT_SHF	0
 #define  GCMP_GCB_GCMPB_CMDEFTGT_MSK	GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM	0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM1	1
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
+#define  GCMP_GCB_GCMPB_CMDEFTGT_DISABLED	0
+#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM		1
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1		2
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2		3
 #define GCMP_GCB_CCMC_OFS		0x0010	/* Global CM Control */
 #define GCMP_GCB_GCSRAP_OFS		0x0020	/* Global CSR Access Privilege */
 #define  GCMP_GCB_GCSRAP_CMACCESS_SHF	0

@@ -115,5 +120,6 @@
 #define GCMP_CCB_DBGGROUP_OFS		0x0100		/* DebugBreak Group */
 
 extern int __init gcmp_probe(unsigned long, unsigned long);
-
+extern int __init gcmp_niocu(void);
+extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
 #endif /* _ASM_GCMPREGS_H */
arch/mips/include/asm/gic.h +18 -170

246 lines not on this page · raw message

arch/mips/kernel/irq-gic.c +44 -72

213 lines not on this page · raw message

arch/mips/mti-malta/malta-int.c +58 -43

176 lines not on this page · raw message

arch/mips/mti-malta/malta-pci.c +11 -3
index b974319..25994e6 100644
@@ -27,7 +27,7 @@
 #include <linux/init.h>
 
 #include <asm/gt64120.h>
-
+#include <asm/gcmpregs.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/bonito64.h>
 #include <asm/mips-boards/msc01_pci.h>

@@ -201,7 +201,11 @@ void __init mips_pcibios_init(void)
 		msc_mem_resource.start = start & mask;
 		msc_mem_resource.end = (start & mask) | ~mask;
 		msc_controller.mem_offset = (start & mask) - (map & mask);
-
+#ifdef CONFIG_MIPS_CMP
+		if (gcmp_niocu())
+			gcmp_setregion(0, start, mask,
+				GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+#endif
 		MSC_READ(MSC01_PCI_SC2PIOBASL, start);
 		MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
 		MSC_READ(MSC01_PCI_SC2PIOMAPL, map);

@@ -209,7 +213,11 @@ void __init mips_pcibios_init(void)
 		msc_io_resource.end = (map & mask) | ~mask;
 		msc_controller.io_offset = 0;
 		ioport_resource.end = ~mask;
-
+#ifdef CONFIG_MIPS_CMP
+		if (gcmp_niocu())
+			gcmp_setregion(1, start, mask,
+				GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+#endif
 		/* If ranges overlap I/O takes precedence.  */
 		start = start & mask;
 		end = start | ~mask;
author
#3 lore raw

PATCH 3/3 Avoid accessing GCMP registers when they are not present

In reply to Raghu Gandham

From: Jaidev Patwardhan <[email protected]>

Signed-off-by Chris Dearman <[email protected]>

---

 arch/mips/mti-malta/malta-int.c |   16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)
arch/mips/mti-malta/malta-int.c +13 -3
index 377a925..4c3fca1 100644
@@ -411,6 +411,11 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
  */
 int __init gcmp_probe(unsigned long addr, unsigned long size)
 {
+	if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
+		gcmp_present = 0;
+		return gcmp_present;
+	}
+
 	if (gcmp_present >= 0)
 		return gcmp_present;
 

@@ -479,9 +484,14 @@ void __init arch_init_irq(void)
 		GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
 		gic_present = 1;
 	} else {
-		_msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
-		gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
-		MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF;
+		if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
+			_msc01_biu_base = (unsigned long)
+					ioremap_nocache(MSC01_BIU_REG_BASE,
+						MSC01_BIU_ADDRSPACE_SZ);
+			gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
+					MSC01_SC_CFG_GICPRES_MSK) >>
+					MSC01_SC_CFG_GICPRES_SHF;
+		}
 	}
 	if (gic_present)
 		pr_debug("GIC present\n");