sdhci-of: Some fixes for high-speed and 4-bit SD cards
Subsystems (5)
v2 cover sdhci-of: Some fixes for high-speed and 4-bit SD cards
In v2:
- Addressed David Vrabel's comments;
- New patches added:
powerpc: Introduce and document sdhci,wp-inverted property for eSDHC
sdhci-of: Don't hard-code inverted write-protect quirk powerpc/85xx: Add eSDHC support for MPC8536DS boards
PATCH v2 1/7 sdhci-of: Fix SD clock calculation
Linear divisor's values in a register start at 0 (zero means "divide by 1"). Before this patch the code didn't account that fact, so SD cards were running underclocked.
--- drivers/mmc/host/sdhci-of.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
drivers/mmc/host/sdhci-of.c +1 -0
@@ -136,6 +136,7 @@ static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) } pre_div >>=1 ; + div--; setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
Signature · 1 line
1.6.3.3
PATCH v2 2/7 sdhci-of: Avoid writing reserved bits into host control register
In reply to Anton VorontsovSDHCI core tries to write HISPD bit into the host control register, but the eSDHC controllers don't have that bit, and that causes all sorts of misbehaviour when using 4-bit mode capable SD cards.
--- drivers/mmc/host/sdhci-of.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
drivers/mmc/host/sdhci-of.c +6 -0
@@ -48,6 +48,8 @@ struct sdhci_of_host {#define ESDHC_CLOCK_HCKEN 0x00000002#define ESDHC_CLOCK_IPGEN 0x00000001 +#define ESDHC_HOST_CONTROL_RES 0x05 +static u32 esdhc_readl (struct sdhci_host *host,int reg) {return in_be32 (host->ioaddr + reg);
@@ -109,6 +111,10 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)int base = reg & ~0x3 ;int shift = (reg &0x3 ) *8 ; +/* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */ +if (reg ==SDHCI_HOST_CONTROL ) + val &= ~ESDHC_HOST_CONTROL_RES ; +clrsetbits_be32 (host->ioaddr + base ,0xff << shift, val << shift); }
Signature · 1 line
1.6.3.3
PATCH v2 3/7 sdhci-of: Fix high-speed cards recognition
In reply to Anton VorontsoveSDHC fails to recognize some SDHS cards, throwing timeout errors:
mmc0: error -110 whilst initialising SD card
That's because we calculate timeout value in a wrong way: on eSDHC hosts the timeout clock is derivied from the SD clock, which is set dynamically.
As David Vrabel suggested, deriving timeout clock from SD clock is a common scheme, so let's implement DATA_TIMEOUT_USES_SDCLK quirk and use it for eSDHC hosts.
Also, from now on we don't need esdhc_get_timeout_clock() callback, so remove it.
--- drivers/mmc/host/sdhci-of.c | 9 +-------- drivers/mmc/host/sdhci.c | 9 +++++++-- drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 10 insertions(+), 10 deletions(-)
drivers/mmc/host/sdhci-of.c +1 -8
@@ -172,19 +172,13 @@ static unsigned int esdhc_get_min_clock(struct sdhci_host *host)return of_host->clock /256 /16 ; } -static unsigned int esdhc_get_timeout_clock (struct sdhci_host *host) -{ -struct sdhci_of_host *of_host =sdhci_priv (host); - -return of_host->clock /1000 ; -} -static struct sdhci_of_data sdhci_esdhc = { .quirks =SDHCI_QUIRK_FORCE_BLK_SZ_2048 |SDHCI_QUIRK_BROKEN_CARD_DETECTION |SDHCI_QUIRK_INVERTED_WRITE_PROTECT |SDHCI_QUIRK_NO_BUSY_IRQ |SDHCI_QUIRK_NONSTANDARD_CLOCK | +SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |SDHCI_QUIRK_PIO_NEEDS_DELAY |SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |SDHCI_QUIRK_NO_CARD_NO_RESET ,
@@ -199,7 +193,6 @@ static struct sdhci_of_data sdhci_esdhc = { .enable_dma = esdhc_enable_dma, .get_max_clock = esdhc_get_max_clock, .get_min_clock = esdhc_get_min_clock, - .get_timeout_clock = esdhc_get_timeout_clock, }, };
drivers/mmc/host/sdhci.c +7 -2
@@ -591,6 +591,9 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data) target_timeout = data->timeout_ns /1000 + data->timeout_clks / host->clock; +if (host->quirks &SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK ) + host->timeout_clk = host->clock /1000 ; +/* * Figure out needed cycles. * We do this in steps in order to fit inside a 32 bit int.
@@ -1757,13 +1760,15 @@ int sdhci_add_host(struct sdhci_host *host) host->timeout_clk = (caps &SDHCI_TIMEOUT_CLK_MASK ) >>SDHCI_TIMEOUT_CLK_SHIFT ;if (host->timeout_clk ==0 ) { -if (!host->ops->get_timeout_clock) { +if (host->ops->get_timeout_clock) { + host->timeout_clk = host->ops->get_timeout_clock (host); + }else if (!(host->quirks & +SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK )) {printk (KERN_ERR "%s: Hardware doesn't specify timeout clock " "frequency.\n" ,mmc_hostname (mmc));return -ENODEV ; } - host->timeout_clk = host->ops->get_timeout_clock (host); }if (caps &SDHCI_TIMEOUT_CLK_UNIT ) host->timeout_clk *=1000 ;
drivers/mmc/host/sdhci.h +2 -0
@@ -232,6 +232,8 @@ struct sdhci_host {#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)/* Controller needs 10ms delay between applying power and clock */ #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) +/* Controller uses SDCLK instead of TMCLK for data timeouts */ +#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)int irq;/* Device IRQ */ void __iomem * ioaddr;/* Mapped address */
Signature · 1 line
1.6.3.3
PATCH v2 4/7 powerpc: Introduce and document sdhci,wp-inverted property for eSDHC
In reply to Anton VorontsoveSDHC block in MPC837x SOCs reports inverted write-protect state, soon sdhci-of driver will look for sdhci,wp-inverted properties to decide whether apply a specific quirk.
So, document the property and add it to device tree source files.
--- Documentation/powerpc/dts-bindings/fsl/esdhc.txt | 2 ++ arch/powerpc/boot/dts/mpc8377_mds.dts | 1 + arch/powerpc/boot/dts/mpc8377_rdb.dts | 1 + arch/powerpc/boot/dts/mpc8377_wlan.dts | 1 + arch/powerpc/boot/dts/mpc8378_mds.dts | 1 + arch/powerpc/boot/dts/mpc8378_rdb.dts | 1 + arch/powerpc/boot/dts/mpc8379_mds.dts | 1 + arch/powerpc/boot/dts/mpc8379_rdb.dts | 1 + 8 files changed, 9 insertions(+), 0 deletions(-)
Documentation/powerpc/dts-bindings/fsl/esdhc.txt +2 -0
@@ -10,6 +10,8 @@ Required properties: - interrupts : should contain eSDHC interrupt. - interrupt-parent : interrupt source phandle. - clock-frequency : specifies eSDHC base clock frequency. + - sdhci,wp-inverted : (optional) specifies that eSDHC controller + reports inverted write-protect state; - sdhci,1-bit-only : (optional) specifies that a controller can only handle 1-bit data transfers.
arch/powerpc/boot/dts/mpc8377_mds.dts +1 -0
@@ -159,6 +159,7 @@ reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; + sdhci,wp-inverted; /* Filled in by U-Boot */ clock-frequency = <0>; };
arch/powerpc/boot/dts/mpc8377_rdb.dts +1 -0
@@ -173,6 +173,7 @@ reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; + sdhci,wp-inverted; /* Filled in by U-Boot */ clock-frequency = <111111111>; };
arch/powerpc/boot/dts/mpc8377_wlan.dts +1 -0
@@ -150,6 +150,7 @@ reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; + sdhci,wp-inverted; clock-frequency = <133333333>; }; };
arch/powerpc/boot/dts/mpc8378_mds.dts +1 -0
@@ -159,6 +159,7 @@ reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; + sdhci,wp-inverted; /* Filled in by U-Boot */ clock-frequency = <0>; };
arch/powerpc/boot/dts/mpc8378_rdb.dts +1 -0
@@ -173,6 +173,7 @@ reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; + sdhci,wp-inverted; /* Filled in by U-Boot */ clock-frequency = <111111111>; };
arch/powerpc/boot/dts/mpc8379_mds.dts +1 -0
@@ -157,6 +157,7 @@ reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; + sdhci,wp-inverted; /* Filled in by U-Boot */ clock-frequency = <0>; };
arch/powerpc/boot/dts/mpc8379_rdb.dts +1 -0
@@ -171,6 +171,7 @@ reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; + sdhci,wp-inverted; /* Filled in by U-Boot */ clock-frequency = <111111111>; };
Signature · 1 line
1.6.3.3
PATCH v2 5/7 sdhci-of: Don't hard-code inverted write-protect quirk
In reply to Anton VorontsovMPC85xx SOCs have normal write-protect state reporting, so we shouldn't hard-code the quirk.
Instead, look for "sdhci,wp-inverted" property, plus check for mpc837x_{rdb,mds} machines since older device trees don't specify the new property.
--- drivers/mmc/host/sdhci-of.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-)
drivers/mmc/host/sdhci-of.c +13 -1
@@ -21,6 +21,7 @@#include <linux/of.h> #include <linux/of_platform.h> #include <linux/mmc/host.h> +#include <asm/machdep.h> #include "sdhci.h" struct sdhci_of_data {
@@ -175,7 +176,6 @@ static unsigned int esdhc_get_min_clock(struct sdhci_host *host)static struct sdhci_of_data sdhci_esdhc = { .quirks =SDHCI_QUIRK_FORCE_BLK_SZ_2048 |SDHCI_QUIRK_BROKEN_CARD_DETECTION | -SDHCI_QUIRK_INVERTED_WRITE_PROTECT |SDHCI_QUIRK_NO_BUSY_IRQ |SDHCI_QUIRK_NONSTANDARD_CLOCK | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
@@ -219,6 +219,15 @@ static int sdhci_of_resume(struct of_device *ofdev)#endif +static bool __devinit sdhci_of_wp_inverted (struct device_node *np) +{ +if (of_get_property (np,"sdhci,wp-inverted" ,NULL )) +return true; + +/* Old device trees don't have the wp-inverted property. */ +return machine_is (mpc837x_rdb) ||machine_is (mpc837x_mds); +} +static int __devinit sdhci_of_probe (struct of_device *ofdev,const struct of_device_id *match) {
@@ -261,6 +270,9 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,if (of_get_property (np,"sdhci,1-bit-only" ,NULL )) host->quirks |=SDHCI_QUIRK_FORCE_1_BIT_DATA ; +if (sdhci_of_wp_inverted (np)) + host->quirks |=SDHCI_QUIRK_INVERTED_WRITE_PROTECT ; + clk =of_get_property (np,"clock-frequency" , &size);if (clk && size ==sizeof (*clk) && *clk) of_host->clock = *clk;
Signature · 1 line
1.6.3.3
PATCH v2 6/7 sdhci-of: Cleanup eSDHC's set_clock() a little bit
In reply to Anton Vorontsov- Get rid of incomprehensible "if { for { if } }" construction for the exponential divisor calculation. The first if statement isn't correct at all, since it should check for "host->max_clk / pre_div / 16 > clock". The error doesn't cause any bugs because the check in the for loop does the right thing, and so the outer check becomes useless;
- For the linear divisor do the same: a single while statement is more readable than for + if construction;
- Add dev_dbg() that prints desired and actual clock frequency.
--- drivers/mmc/host/sdhci-of.c | 19 ++++++++----------- 1 files changed, 8 insertions(+), 11 deletions(-)
drivers/mmc/host/sdhci-of.c +8 -11
@@ -121,8 +121,8 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)static void esdhc_set_clock (struct sdhci_host *host,unsigned int clock) { -int div;int pre_div =2 ; +int div =1 ;clrbits32 (host->ioaddr +ESDHC_SYSTEM_CONTROL ,ESDHC_CLOCK_IPGEN |ESDHC_CLOCK_HCKEN |ESDHC_CLOCK_PEREN |ESDHC_CLOCK_MASK );
@@ -130,17 +130,14 @@ static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)if (clock ==0 ) goto out; -if (host->max_clk /16 > clock) { -for (; pre_div <256 ; pre_div *=2 ) { -if (host->max_clk / pre_div < clock *16 ) -break ; - } - } +while (host->max_clk / pre_div /16 > clock && pre_div <256 ) + pre_div *=2 ; -for (div =1 ; div <=16 ; div++) { -if (host->max_clk / (div * pre_div) <= clock) -break ; - } +while (host->max_clk / pre_div / div > clock && div <16 ) + div++; + +dev_dbg (mmc_dev (host->mmc),"desired SD clock: %d, actual: %d\n" , + clock, host->max_clk / pre_div / div); pre_div >>=1 ; div--;
Signature · 1 line
1.6.3.3
PATCH v2 7/7 powerpc/85xx: Add eSDHC support for MPC8536DS boards
In reply to Anton VorontsovThis patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
--- arch/powerpc/boot/dts/mpc8536ds.dts | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
arch/powerpc/boot/dts/mpc8536ds.dts +8 -0
@@ -250,6 +250,14 @@ phy_type = "ulpi"; }; + sdhci@2e000 { + compatible = "fsl,mpc8536-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2>; + interrupt-parent = <&mpic>; + clock-frequency = <250000000>; + }; + serial0: serial@4500 { cell-index = <0>; device_type = "serial";
Signature · 1 line
1.6.3.3
Re: [PATCH 7/7] powerpc/85xx: Add eSDHC support for MPC8536DS boards
Quoted 11 lines · Anton Vorontsov
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
Signed-off-by Anton Vorontsov <[email protected]>---
arch/powerpc/boot/dts/mpc8536ds.dts| 8 ++++++++1 files changed, 8 insertions(+), 0 deletions(-)
Can you update the mpc8536ds_36b.dts as well (its in my next branch)
- k
PATCH v2 1/1 powerpc/85xx: Add eSDHC support for MPC8536DS boards
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
---
Quoted 8 lines · Kumar Gala
Quoted 7 lines · Anton Vorontsov
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
Quoted 6 lines
Quoted 4 lines
Signed-off-by Anton Vorontsov <[email protected]>---
arch/powerpc/boot/dts/mpc8536ds.dts| 8 ++++++++1 files changed, 8 insertions(+), 0 deletions(-)Can you update the
mpc8536ds_36b.dtsas well (its in my next branch)
Sure thing.
arch/powerpc/boot/dts/mpc8536ds.dts | 8 ++++++++ arch/powerpc/boot/dts/mpc8536ds_36b.dts | 8 ++++++++ 2 files changed, 16 insertions(+), 0 deletions(-)
arch/powerpc/boot/dts/mpc8536ds.dts +8 -0
@@ -250,6 +250,14 @@ phy_type = "ulpi"; }; + sdhci@2e000 { + compatible = "fsl,mpc8536-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2>; + interrupt-parent = <&mpic>; + clock-frequency = <250000000>; + }; + serial0: serial@4500 { cell-index = <0>; device_type = "serial";
arch/powerpc/boot/dts/mpc8536ds_36b.dts +8 -0
@@ -250,6 +250,14 @@ phy_type = "ulpi"; }; + sdhci@2e000 { + compatible = "fsl,mpc8536-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2>; + interrupt-parent = <&mpic>; + clock-frequency = <250000000>; + }; + serial0: serial@4500 { cell-index = <0>; device_type = "serial";
Signature · 1 line
1.6.3.3
Re: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
Quoted 8 lines · Anton Vorontsov
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
Signed-off-by Anton Vorontsov <[email protected]>
out of interest the 85xx eSDHC don't need the sdhci,wp-inverted property?
- k
Re: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
Quoted 10 lines · Kumar Gala
Quoted 7 lines · Anton Vorontsov
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
Quoted 4 lines
Quoted 1 line
Signed-off-by Anton Vorontsov <[email protected]>out of interest the 85xx eSDHC don't need the sdhci,wp-inverted property?
Yes, eSDHC controllers in MPC85xx report normal state in its registers.
But the funny thing is that the switch itself is inverted, so to enable writing, on MPC8569E-MDS and MPC8536DS boards we have to place card's write protect tab into "lock" position.
Unfortunately we can't fix that in software since controller doesn't permit write operations if it detects write-protected state. On the bright side, IIRC MPC8536DS revision history says that WP line level is fixed via BCSR upgrade. Not sure if it is possible to fix it for MPC8569E-MDS.
Signature · 3 lines
Anton Vorontsov email: [email protected] irc://irc.freenode.net/bd2
RE: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
Quoted 29 lines
-----Original Message-----
From:
[email protected] [mailto:[email protected] .org] On Behalf Of Anton Vorontsov
Sent: Wednesday, August 19, 2009 9:51 AM
To: Kumar Gala
Cc: Ben Dooks; [email protected]; [email protected]; [email protected]; Andrew Morton; Pierre Ossman; David Vrabel
Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boardsQuoted 6 lines · Kumar Gala
Quoted 3 lines · Anton Vorontsov
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will
work without
Quoted 2 lines
Quoted 2 lines
upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's
recommended
Quoted 1 line
Quoted 1 line
to upgrade U-Boot, since it will fixup clock-frequency
automatically.
Quoted 1 line
Quoted 1 line
Quoted 8 lines
Quoted 4 lines
Quoted 1 line
Signed-off-by Anton Vorontsov <[email protected]>out of interest the 85xx eSDHC don't need the sdhci,wp-inverted property?
Yes, eSDHC controllers in MPC85xx report normal state in its registers.
Hi Anton,
The eSDHC controller in different silicon version on MPC8536 reports different WP state in the register PRSSTAT:
Silicon 1.0:
Card WP pos PRSSTAT[WPSPL] RMMCR[SDHC_WP] GENCFG[SDHC_WP_INV]
------------------------------------------------------------------------
---------------------------------------------
unLock 1 1
/
Lock 0 1
/
Silicon 1.1:
Card WP pos PRSSTAT[WPSPL] RMMCR[SDHC_WP] GENCFG[SDHC_WP_INV]
------------------------------------------------------------------------
---------------------------------------------
unLock 0 1
0
Lock 1 1
0
Note: the register GENCFG is added on silicon 1.1 to invert the WP state.
For silicon 1.0, the macro SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also defined,
so the dirver will report the error WP state in function sdhci_get_ro.
Best regards,
Mingkai
Re: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
Quoted 19 lines · On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote:
Quoted 19 lines · Kumar Gala
Quoted 6 lines · Anton Vorontsov
Quoted 4 lines
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will
work without
Quoted 2 lines
Quoted 2 lines
upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's
recommended
Quoted 1 line
Quoted 1 line
to upgrade U-Boot, since it will fixup clock-frequency
automatically.
Quoted 5 lines
Quoted 2 lines
Signed-off-by Anton Vorontsov <[email protected]>out of interest the 85xx eSDHC don't need the sdhci,wp-inverted property?
Quoted 8 lines
Quoted 3 lines
Yes, eSDHC controllers in MPC85xx report normal state in its registers.
Hi Anton,
The eSDHC controller in different silicon version on MPC8536 reports different WP state in the register PRSSTAT:
Thanks a million for the heads up!
Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't mention that, but the newer manual that I just downloaded ("MPC8536ERM Rev. 1 05/2009") does.
[...]
Quoted 3 lines
For silicon 1.0, the macro
SDHCI_QUIRK_INVERTED_WRITE_PROTECTis also defined,
so the dirver will report the error WP state in functionsdhci_get_ro.
Not any longer. We don't actually define it for any 85xx CPUs.
I need to think how should we handle all these WP inversions. :-)
So, we have inversion in BCSR (depending on the BCSR revision), configurable inversion in CPU via GENCFGR for 1.1 silicon, and non-configurable non-inverted reporting for 1.0 silicon...
Do you know if there are any plans to fix the WP inversion for MPC8569E-MDS boards, or make something like GENCFGR for MPC8569 CPUs?
Thanks,
Signature · 3 lines
Anton Vorontsov email: [email protected] irc://irc.freenode.net/bd2
RE: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
Quoted 65 lines
-----Original Message-----
From: Anton Vorontsov [mailto:[email protected]]
Sent: Friday, August 28, 2009 11:20 PM
To: Hu Mingkai-B21284
Cc: Kumar Gala; Ben Dooks; [email protected]; [email protected]; [email protected]; Andrew Morton; Pierre Ossman; David Vrabel
Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boardsQuoted 20 lines · On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote:
Quoted 20 lines · Kumar Gala
Quoted 6 lines · Anton Vorontsov
Quoted 4 lines
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will
work without
Quoted 3 lines
Quoted 3 lines
upgrading U-Boot. Though, that'll only work for default setup (1500
MHz) on new board revisions. For non-default setups, it'srecommended
Quoted 1 line
Quoted 1 line
to upgrade U-Boot, since it will fixup clock-frequency
automatically.
Quoted 5 lines
Quoted 2 lines
Signed-off-by Anton Vorontsov <[email protected]>out of interest the 85xx eSDHC don't need the sdhci,wp-inverted property?
Quoted 7 lines
Quoted 3 lines
Yes, eSDHC controllers in MPC85xx report normal state in its registers.
Hi Anton,
The eSDHC controller in different silicon version on
MPC8536 reports
Quoted 1 line
different WP state in the register PRSSTAT:
Thanks a million for the heads up!
Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't mention that, but the newer manual that I just downloaded ("MPC8536ERM Rev. 1
05/2009") does.[...]
Quoted 1 line
For silicon 1.0, the macro
SDHCI_QUIRK_INVERTED_WRITE_PROTECTis alsoQuoted 2 lines
defined, so the dirver will report the error WP state in function
sdhci_get_ro.Not any longer. We don't actually define it for any 85xx CPUs.
I need to think how should we handle all these WP inversions. :-)
So, we have inversion in BCSR (depending on the BCSR revision), configurable inversion in CPU via GENCFGR for 1.1 silicon, and non-configurable non-inverted reporting for 1.0 silicon...
Quoted 6 lines
Do you know if there are any plans to fix the WP inversion for MPC8569E-MDS boards, or make something like GENCFGR for MPC8569 CPUs?
Thanks,
Sorry, I also don't know the plan to MPC8569 CPU, but if I get any info, I'll inform you ASAP. :-)
Best regards,
Mingkai
Quoted 6 lines
--
Anton Vorontsov
email: [email protected]
irc://irc.freenode.net/bd2
Kumar Gala
AppliedRe: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
In reply to Anton VorontsovQuoted 24 lines · Anton Vorontsov
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
Signed-off-by Anton Vorontsov <[email protected]>---
Quoted 13 lines · Kumar Gala
Quoted 11 lines · Anton Vorontsov
This patch simply adds sdhci node to the device tree.
We specify clock-frequency manually, so that eSDHC will work without upgrading U-Boot. Though, that'll only work for default setup (1500 MHz) on new board revisions. For non-default setups, it's recommended to upgrade U-Boot, since it will fixup clock-frequency automatically.
Signed-off-by Anton Vorontsov <[email protected]>---
arch/powerpc/boot/dts/mpc8536ds.dts| 8 ++++++++1 files changed, 8 insertions(+), 0 deletions(-)
Quoted 7 lines
Quoted 1 line
Can you update the
mpc8536ds_36b.dtsas well (its in my next branch)Sure thing.
arch/powerpc/boot/dts/mpc8536ds.dts | 8 ++++++++ arch/powerpc/boot/dts/mpc8536ds_36b.dts | 8 ++++++++ 2 files changed, 16 insertions(+), 0 deletions(-)
applied to next.
- k