ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driver

Fix ECC Correction bug where the byte offset location were double flipped causing correction routine to toggle the wrong byte location in the ECC segment. The ndfc_calculate_ecc routine change the order of getting the ECC code.

        /* The NDFC uses Smart Media (SMC) bytes order */
        ecc_code[0] = p[2];
        ecc_code[1] = p[1];
        ecc_code[2] = p[3];

But in the Correction algorithm when calculating the byte offset location, the s1 is used as the upper part of the address. Which again reverse the order making the final byte offset address location incorrect.

	byteoffs = (s1 << 0) & 0x80;
	.
	.
	byteoffs |= (s0 >> 4) & 0x08;

The order is change to read it in straight and let the correction function to revert it to SMC order.

---
 drivers/mtd/nand/ndfc.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

index 528b22b..0891936 100644
@@ -89,8 +89,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
 
 	/* The NDFC uses Smart Media (SMC) bytes order
 	 */
-	ecc_code[0] = p[2];
-	ecc_code[1] = p[1];
+	ecc_code[0] = p[1];
+	ecc_code[1] = p[2];
 	ecc_code[2] = p[3];
 
 	return 0;

1.5.5

Applied to u-boot-ppc4xx/master. Thanks.

Cheers,
Stefan

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