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bcm63xx: only set the proper GPIO overlay settings

PATCH In review Florian Fainelli 3 participants 5 messages Aug 31, 2009 – Oct 12, 2009 MIPS

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#0 lore raw

PATCH 2/2 bcm63xx: only set the proper GPIO overlay settings

This patch makes the GPIO pin multiplexing configuration read the initial GPIO mode register value instead of setting it initially to 0, then setting the correct bits, this is safer.

---

arch/mips/bcm63xx/boards/board_bcm963xx.c +1 -1
index cfe32af..6ae4242 100644
@@ -634,7 +634,7 @@ void __init board_prom_init(void)
 	/* setup pin multiplexing depending on board enabled device,
 	 * this has to be done this early since PCI init is done
 	 * inside arch_initcall */
-	val = 0;
+	val = bcm_gpio_readl(GPIO_MODE_REG);
 
 #ifdef CONFIG_PCI
 	if (board.has_pci) {
#1 lore raw
Quoted 4 lines · Florian Fainelli

This patch makes the GPIO pin multiplexing configuration read the initial GPIO mode register value instead of setting it initially to 0, then setting the correct bits, this is safer.

I disagree, now we get working or not working devices depending on the CFE version used, for which we don't have any public source code nor changelog.

I cleared the register for that purpose.

If a particular pin muxing config is needed for some board, we should add this to the board specific struct instead.

Signature · 1 line
Maxime
#2 lore raw
Quoted 9 lines · Maxime Bizon
Quoted 4 lines · Florian Fainelli

This patch makes the GPIO pin multiplexing configuration read the initial GPIO mode register value instead of setting it initially to 0, then setting the correct bits, this is safer.

I disagree, now we get working or not working devices depending on the CFE version used, for which we don't have any public source code nor changelog.

I did not think this could break other boards, it is required on BCM6345 though.

Quoted 5 lines

I cleared the register for that purpose.

If a particular pin muxing config is needed for some board, we should add this to the board specific struct instead.

Then I will make it BCM6345 specific.

Thanks.

Signature · 5 lines
Best regards, Florian Fainelli
Email: [email protected]
Web: http://openwrt.org
IRC: [florian] on irc.freenode.net
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#3 lore raw
Quoted 15 lines · Florian Fainelli
Quoted 9 lines · Maxime Bizon
Quoted 4 lines · Florian Fainelli

This patch makes the GPIO pin multiplexing configuration read the initial GPIO mode register value instead of setting it initially to 0, then setting the correct bits, this is safer.

I disagree, now we get working or not working devices depending on the CFE version used, for which we don't have any public source code nor changelog.

I did not think this could break other boards, it is required on BCM6345 though.

Quoted 1 line
Quoted 6 lines
Quoted 4 lines

I cleared the register for that purpose.

If a particular pin muxing config is needed for some board, we should add this to the board specific struct instead.

Then I will make it BCM6345 specific.

I thought you were going to send an update to this?

Ralf

#4 lore raw
Quoted 15 lines · On Monday 12 October 2009 00:53:20 Ralf Baechle wrote:
Quoted 14 lines · Florian Fainelli
Quoted 9 lines · Maxime Bizon
Quoted 4 lines · Florian Fainelli

This patch makes the GPIO pin multiplexing configuration read the initial GPIO mode register value instead of setting it initially to 0, then setting the correct bits, this is safer.

I disagree, now we get working or not working devices depending on the CFE version used, for which we don't have any public source code nor changelog.

I did not think this could break other boards, it is required on BCM6345 though.

Quoted 8 lines
Quoted 6 lines
Quoted 4 lines

I cleared the register for that purpose.

If a particular pin muxing config is needed for some board, we should add this to the board specific struct instead.

Then I will make it BCM6345 specific.

I thought you were going to send an update to this?

Not at the moment, the user who reported that issue though it was related to that and I also saw a potential for breaking BCM6345 GPIO config, but since that one has a totally different GPIO registers layout it needs a bigger fix which deals with different registers.