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MIPS: Avoid destructive invalidation on partial L2 cachelines

PATCH In review Kevin Cernekee 2 participants 2 messages Sep 19, 2009 – Sep 23, 2009 MIPS

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Kevin Cernekee

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PATCH 1/1 MIPS: Avoid destructive invalidation on partial L2 cachelines

This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover the board cache code.

Signed-off-by Kevin Cernekee <[email protected]>
---
 arch/mips/mm/sc-mips.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)
arch/mips/mm/sc-mips.c +5 -0
index b55c2d1..5ab5fa8 100644
@@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
  */
 static void mips_sc_inv(unsigned long addr, unsigned long size)
 {
+	unsigned long lsize = cpu_scache_line_size();
+	unsigned long almask = ~(lsize - 1);
+
+	cache_op(Hit_Writeback_Inv_SD, addr & almask);
+	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
 	blast_inv_scache_range(addr, addr + size);
 }
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1.6.3.1