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qemu: update pcbios to enable i/o for cirrus

PATCH New Michael S. Tsirkin 1 participant 5 messages Oct 8, 2009 1 message not in the archive KVM

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A message that is not in the archive (sent off-list or not yet received): [email protected]

Michael S. Tsirkin

author
#1 lore raw

PATCH v2 1/4 qemu: update pcbios to enable i/o for cirrus

before making cirrus pci spec compliant,
need to fix pcibios to enable i/o for it.
The relevant patch is:
pcbios: enable io/memory unconditionally

Signed-off-by Michael S. Tsirkin <[email protected]>
---
 roms/pcbios |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
roms/pcbios +1 -1
index da5ff65..6ad727d 160000
@@ -1 +1 @@
-Subproject commit da5ff65dc9473e3f069736d38b9a189ea14a67eb
+Subproject commit 6ad727d68f1e1502a5c718dd39bdabc4db76d159
Signature · 1 line
1.6.5.rc2
author
#2 lore raw

PATCH v2 2/4 qemu: update seabios to enable i/o for cirrus

In reply to a message not in the archive

Need to update seabios submodule
before making cirrus PCI spec compliant.
the relevant patch is:
seabios: enable io/memory unconditionally

Signed-off-by Michael S. Tsirkin <[email protected]>
---
 roms/seabios |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
roms/seabios +1 -1
index 5c3f5dd..274e351 160000
@@ -1 +1 @@
-Subproject commit 5c3f5dde217f382b02350973a38f50941904473d
+Subproject commit 274e351aa119af1656a3e007f68c2c9c13555446
Signature · 1 line
1.6.5.rc2
author
#3 lore raw

PATCH v2 3/4 qemu: make cirrus init value pci spec compliant

In reply to a message not in the archive

PCI memory should be disabled at reset, otherwise we might claim transactions at address 0.
I/O should also be disabled, although for cirrus it is harmless to enable it as we do not
have I/O bar.

Note: need bios fix for this patch to work:
currently pc-bios incorrently assumes that it does not need to enable i/o unless device has i/o bar.

Signed-off-by Michael S. Tsirkin <[email protected]>
---
 hw/cirrus_vga.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)
hw/cirrus_vga.c +0 -1
index 9dfe76a..2b895db 100644
@@ -3230,7 +3230,6 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
      /* setup PCI */
      pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
      pci_config_set_device_id(pci_conf, device_id);
-     pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
      pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
      pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
Signature · 1 line
1.6.5.rc2
author
#4 lore raw

PATCH v2 4/4 qemu: cleanup unused macros in cirrus

In reply to a message not in the archive

Cirrus vga has a copy of many PCI macros,
and it doesn't even use them. Clean up.

Signed-off-by Michael S. Tsirkin <[email protected]>
---
 hw/cirrus_vga.c |   37 +------------------------------------
 1 files changed, 1 insertions(+), 36 deletions(-)
hw/cirrus_vga.c +1 -36
index 2b895db..f901d53 100644
@@ -171,41 +171,6 @@
 #define CIRRUS_MMIO_LINEDRAW_MODE     0x39	// byte
 #define CIRRUS_MMIO_BLTSTATUS         0x40	// byte
 
-// PCI 0x04: command(word), 0x06(word): status
-#define PCI_COMMAND_IOACCESS                0x0001
-#define PCI_COMMAND_MEMACCESS               0x0002
-#define PCI_COMMAND_BUSMASTER               0x0004
-#define PCI_COMMAND_SPECIALCYCLE            0x0008
-#define PCI_COMMAND_MEMWRITEINVALID         0x0010
-#define PCI_COMMAND_PALETTESNOOPING         0x0020
-#define PCI_COMMAND_PARITYDETECTION         0x0040
-#define PCI_COMMAND_ADDRESSDATASTEPPING     0x0080
-#define PCI_COMMAND_SERR                    0x0100
-#define PCI_COMMAND_BACKTOBACKTRANS         0x0200
-// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
-#define PCI_CLASS_BASE_DISPLAY        0x03
-// PCI 0x08, 0x00ff0000
-#define PCI_CLASS_SUB_VGA             0x00
-// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
-// 0x10-0x3f (headertype 00h)
-// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
-//   0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
-#define PCI_MAP_MEM                 0x0
-#define PCI_MAP_IO                  0x1
-#define PCI_MAP_MEM_ADDR_MASK       (~0xf)
-#define PCI_MAP_IO_ADDR_MASK        (~0x3)
-#define PCI_MAP_MEMFLAGS_32BIT      0x0
-#define PCI_MAP_MEMFLAGS_32BIT_1M   0x1
-#define PCI_MAP_MEMFLAGS_64BIT      0x4
-#define PCI_MAP_MEMFLAGS_CACHEABLE  0x8
-// PCI 0x28: cardbus CIS pointer
-// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
-// PCI 0x30: expansion ROM base address
-#define PCI_ROMBIOS_ENABLED         0x1
-// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
-// PCI 0x38: reserved
-// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
-
 #define CIRRUS_PNPMMIO_SIZE         0x1000
 
 #define ABS(a) ((signed)(a) > 0 ? a : -a)

@@ -3230,8 +3195,8 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
      /* setup PCI */
      pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
      pci_config_set_device_id(pci_conf, device_id);
+     //pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
      pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
-     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
 
      /* setup memory space */
      /* memory #0 LFB */
Signature · 1 line
1.6.5.rc2
author
#5 lore raw

PATCH v3 4/4 qemu: cleanup unused macros in cirrus

Cirrus vga has a copy of many PCI macros, and it doesn't even use them. Clean up. Also do not init header type, it has the right value by default.

Signed-off-by Michael S. Tsirkin <[email protected]>

---

Respin only the last patch in the series:
improve comment, and remove a commented out line I added by mistake.

 hw/cirrus_vga.c |   37 ------------------------------------
 1 files changed, 0 insertions(+), 36 deletions(-)
hw/cirrus_vga.c +0 -36
index 2b895db..f901d53 100644
@@ -171,41 +171,6 @@
 #define CIRRUS_MMIO_LINEDRAW_MODE     0x39	// byte
 #define CIRRUS_MMIO_BLTSTATUS         0x40	// byte
 
-// PCI 0x04: command(word), 0x06(word): status
-#define PCI_COMMAND_IOACCESS                0x0001
-#define PCI_COMMAND_MEMACCESS               0x0002
-#define PCI_COMMAND_BUSMASTER               0x0004
-#define PCI_COMMAND_SPECIALCYCLE            0x0008
-#define PCI_COMMAND_MEMWRITEINVALID         0x0010
-#define PCI_COMMAND_PALETTESNOOPING         0x0020
-#define PCI_COMMAND_PARITYDETECTION         0x0040
-#define PCI_COMMAND_ADDRESSDATASTEPPING     0x0080
-#define PCI_COMMAND_SERR                    0x0100
-#define PCI_COMMAND_BACKTOBACKTRANS         0x0200
-// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
-#define PCI_CLASS_BASE_DISPLAY        0x03
-// PCI 0x08, 0x00ff0000
-#define PCI_CLASS_SUB_VGA             0x00
-// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
-// 0x10-0x3f (headertype 00h)
-// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
-//   0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
-#define PCI_MAP_MEM                 0x0
-#define PCI_MAP_IO                  0x1
-#define PCI_MAP_MEM_ADDR_MASK       (~0xf)
-#define PCI_MAP_IO_ADDR_MASK        (~0x3)
-#define PCI_MAP_MEMFLAGS_32BIT      0x0
-#define PCI_MAP_MEMFLAGS_32BIT_1M   0x1
-#define PCI_MAP_MEMFLAGS_64BIT      0x4
-#define PCI_MAP_MEMFLAGS_CACHEABLE  0x8
-// PCI 0x28: cardbus CIS pointer
-// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
-// PCI 0x30: expansion ROM base address
-#define PCI_ROMBIOS_ENABLED         0x1
-// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
-// PCI 0x38: reserved
-// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
-
 #define CIRRUS_PNPMMIO_SIZE         0x1000
 
 #define ABS(a) ((signed)(a) > 0 ? a : -a)

@@ -3230,8 +3195,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
      /* setup PCI */
      pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
      pci_config_set_device_id(pci_conf, device_id);
      pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
-     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
 
      /* setup memory space */
      /* memory #0 LFB */
Signature · 1 line
1.6.5.rc2