add loongson2f support
cover add loongson2f support
The coming two patches add loongson2f support, including the basic loongson2f features support and a fix for oprofile of loongson2f.
Wu Zhangjin (2):
[loongson] add basic loongson-2f support
[loongson] oprofile: avoid do_IRQ for perfcounter when the interrupt
is from bonito
arch/mips/Kconfig | 18 ++++ arch/mips/Makefile | 2 + .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + arch/mips/include/asm/mach-loongson/loongson.h | 84 +++++++++++++++++++- arch/mips/include/asm/mach-loongson/mem.h | 27 +++++-- arch/mips/include/asm/mach-loongson/pci.h | 28 ++++++- arch/mips/loongson/common/bonito-irq.c | 5 +- arch/mips/loongson/common/init.c | 8 ++ arch/mips/loongson/common/mem.c | 17 ++++ arch/mips/loongson/common/pci.c | 8 ++ arch/mips/oprofile/op_model_loongson2.c | 5 +- 11 files changed, 193 insertions(+), 13 deletions(-)
PATCH 1/2 add basic loongson-2f support
Loongson2F has built-in DDR2 and PCIX controller. The PCIX controller have a similar programming interface with FPGA northbridge used in Loongson2E.
The main differences between loongson-2e and loongson-2f include:
1. loongson-2f has an extra address windows configuration module, which can be used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space.
2. loongson-2f support 8 levels of software configurable cpu frequency, which can be configured via a register(LOONGSON_CHIPCFG0). the coming cpufreq and standby support are based on this feature.
herein, the module and the corresponding operations are abstracted to loongson.h.
besides, the other loongson2f-specific source code are added here, including gcc 4.4 support, pci memory space, pci io space, dma address.
--- arch/mips/Kconfig | 18 ++++ arch/mips/Makefile | 2 + .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + arch/mips/include/asm/mach-loongson/loongson.h | 84 +++++++++++++++++++- arch/mips/include/asm/mach-loongson/mem.h | 27 +++++-- arch/mips/include/asm/mach-loongson/pci.h | 28 ++++++- arch/mips/loongson/common/bonito-irq.c | 5 +- arch/mips/loongson/common/init.c | 8 ++ arch/mips/loongson/common/mem.c | 17 ++++ arch/mips/loongson/common/pci.c | 8 ++ 10 files changed, 189 insertions(+), 12 deletions(-)
arch/mips/Kconfig +18 -0
@@ -1059,6 +1059,21 @@ config CPU_LOONGSON2E The Loongson 2E processor implements the MIPS III instruction set with many extensions. + It has an internal FPGA northbridge, which is compatiable to + bonito64. + +config CPU_LOONGSON2F + bool "Loongson 2F" + depends on SYS_HAS_CPU_LOONGSON2F + select CPU_LOONGSON2 + help + The Loongson 2F processor implements the MIPS III instruction set + with many extensions. + + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller + have a similar programming interface with FPGA northbridge used in + Loongson2E. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1
@@ -1303,6 +1318,9 @@ config CPU_LOONGSON2 config SYS_HAS_CPU_LOONGSON2E bool +config SYS_HAS_CPU_LOONGSON2F + bool + config SYS_HAS_CPU_MIPS32_R1 bool
arch/mips/Makefile +2 -0
@@ -125,6 +125,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=r4600) cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap
arch/mips/include/asm/mach-loongson/dma-coherence.h +4 -0
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,static inline unsigned long plat_dma_addr_to_phys (struct device *dev,dma_addr_t dma_addr) { +#if defined(CONFIG_CPU_LOONGSON2F ) && defined(CONFIG_64BIT ) +return (dma_addr >0x8fffffff ) ? dma_addr : (dma_addr &0x0fffffff ); +#else return dma_addr &0x7fffffff ; +#endif } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
arch/mips/include/asm/mach-loongson/loongson.h +83 -1
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arch/mips/include/asm/mach-loongson/mem.h +19 -8
@@ -1,5 +1,5 @@/* -* Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology +* Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <[email protected]> * * This program is free software; you can redistribute it and/or modify it
@@ -12,19 +12,30 @@#define __ASM_MACH_LOONGSON_MEM_H/* -* On Lemote Loongson 2e +* high memory space * -* the high memory space starts from 512M. -* the peripheral registers reside between 0x1000:0000 and 0x2000:0000. +* in loongson2e, starts from 512M +* in loongson2f, starts from 2G 256M */ +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_HIGHMEM_START 0x20000000 +#else +#define LOONGSON_HIGHMEM_START 0x90000000 +#endif -#ifdef CONFIG_LEMOTE_FULOONG2E - -#define LOONGSON_HIGHMEM_START 0x20000000 +/* +* the peripheral registers(MMIO): +* +* On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. +* On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. +*/ #define LOONGSON_MMIO_MEM_START 0x10000000 -#define LOONGSON_MMIO_MEM_END 0x20000000 +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_MMIO_MEM_END 0x20000000 +#else +#define LOONGSON_MMIO_MEM_END 0x80000000#endif #endif /* __ASM_MACH_LOONGSON_MEM_H */
arch/mips/include/asm/mach-loongson/pci.h +26 -2
@@ -1,5 +1,6 @@/* * Copyright (c) 2008 Zhang Le <[email protected]> +* Copyright (c) 2009 Wu Zhangjin <[email protected]> * * This program is free software; you can redistribute it * and/or modify it under the terms of the GNU General
@@ -24,7 +25,30 @@extern struct pci_ops loongson_pci_ops; -#ifdef CONFIG_LEMOTE_FULOONG2E +/* this is an offset from mips_io_port_base */ +#define LOONGSON_PCI_IO_START 0x00004000UL + +#if defined(CONFIG_CPU_LOONGSON2F ) && defined(CONFIG_64BIT ) + +/* +* we use address window2 to map cpu address space to pci space +* window2: cpu [1G, 2G] -> pci [1G, 2G] +* why not use window 0 & 1? because they are used by cpu when booting. +* window0: cpu [0, 256M] -> ddr [0, 256M] +* window1: cpu [256M, 512M] -> pci [256M, 512M] +*/ + +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ +#define LOONGSON_CPU_MEM_SRC 0x40000000ul/* 1G */ +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC + +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST +#define LOONGSON_PCI_MEM_END (0x80000000ul-1)/* 2G */ + +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ + LOONGSON_PCI_MEM_START + 1) + +#else /* loongson2f/32bit & loongson2e */ /* this pci memory space is mapped by pcimap in pci.c */ #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
@@ -32,6 +56,6 @@ extern struct pci_ops loongson_pci_ops;/* this is an offset from mips_io_port_base */ #define LOONGSON_PCI_IO_START 0x00004000UL -#endif +#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/ #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
arch/mips/loongson/common/bonito-irq.c +4 -1
@@ -12,6 +12,7 @@* option) any later version. */ #include <linux/interrupt.h> +#include <linux/compiler.h> #include <loongson.h>
@@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = { .unmask = bonito_irq_enable, }; -static struct irqaction dma_timeout_irqaction = { +static struct irqaction __maybe_unused dma_timeout_irqaction = { .handler = no_action, .name ="dma_timeout" , };
@@ -47,5 +48,7 @@ void bonito_irq_init(void)for (i =LOONGSON_IRQ_BASE ; i <LOONGSON_IRQ_BASE +32 ; i++)set_irq_chip_and_handler (i, &bonito_irq_type, handle_level_irq); +#ifdef CONFIG_CPU_LOONGSON2E setup_irq (LOONGSON_IRQ_BASE +10 , &dma_timeout_irqaction); +#endif }
arch/mips/loongson/common/init.c +8 -0
@@ -12,12 +12,20 @@#include <loongson.h> +/* Loongson CPU address windows config space base address */ +unsigned long __maybe_unused _loongson_addrwincfg_base; +void __init prom_init (void ) {/* init base address of io space */ set_io_port_base ((unsigned long )ioremap (LOONGSON_PCIIO_BASE ,LOONGSON_PCIIO_SIZE )); +#if defined(CONFIG_CPU_LOONGSON2F ) && defined(CONFIG_64BIT ) + _loongson_addrwincfg_base = (unsigned long ) +ioremap (LOONGSON_ADDRWINCFG_BASE ,LOONGSON_ADDRWINCFG_SIZE ); +#endif +prom_init_cmdline ();prom_init_env ();prom_init_memory ();
arch/mips/loongson/common/mem.c +17 -0
@@ -21,6 +21,23 @@ void __init prom_init_memory(void)add_memory_region (memsize <<20 ,LOONGSON_PCI_MEM_START - (memsize <<20 ),BOOT_MEM_RESERVED );#ifdef CONFIG_64BIT +#ifdef CONFIG_CPU_LOONGSON2F + { +int bit; + + bit =fls (memsize + highmemsize); +if (bit !=ffs (memsize + highmemsize)) + bit +=20 ; +else + bit = bit +20 -1 ; + +/* set cpu window3 to map CPU to DDR: 2G -> 2G */ +LOONGSON_ADDRWIN_CPUTODDR (ADDRWIN_WIN3 ,0x80000000ul , +0x80000000ul , (1 << bit)); +mmiowb (); + } +#endif /* CONFIG_CPU_LOONGSON2F */ +if (highmemsize >0 )add_memory_region (LOONGSON_HIGHMEM_START , highmemsize <<20 ,BOOT_MEM_RAM );
arch/mips/loongson/common/pci.c +8 -0
@@ -67,6 +67,14 @@ static void __init setup_pcimap(void)/* can not change gnt to break pci transfer when device's gnt not deassert for some broken device */ LOONGSON_PXARB_CFG =0x00fe0105ul ; + +#if defined(CONFIG_CPU_LOONGSON2F ) && defined(CONFIG_64BIT ) +/* +* set cpu addr window2 to map CPU address space to PCI address space +*/ +LOONGSON_ADDRWIN_CPUTOPCI (ADDRWIN_WIN2 ,LOONGSON_CPU_MEM_SRC , +LOONGSON_PCI_MEM_DST ,MMAP_CPUTOPCI_SIZE ); +#endif }static int __init pcibios_init (void )
Signature · 1 line
1.6.2.1
PATCH 2/2 oprofile: avoid do_IRQ for perfcounter when the interrupt is from bonito
In loongson2f, the IP6 is shared by bonito and perfcounter, we need to avoid do_IRQ for perfcounter when the interrupt is from bonito. This patch does it.
--- arch/mips/oprofile/op_model_loongson2.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
arch/mips/oprofile/op_model_loongson2.c +4 -1
@@ -1,7 +1,7 @@/* * Loongson2 performance counter driver for oprofile * -* Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology +* Copyright (C) 2009 Lemote Inc. * Author: Yanhua <[email protected]> * Author: Wu Zhangjin <[email protected]> *
@@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)*/ /* Check whether the irq belongs to me */ + enabled =read_c0_perfcnt () &LOONGSON2_PERFCNT_INT_EN ; +if (!enabled) +return IRQ_NONE ; enabled = reg.cnt1_enabled | reg.cnt2_enabled;if (!enabled)return IRQ_NONE ;
Signature · 1 line
1.6.2.1
Ralf Baechle
AppliedRe: [PATCH -queue 2/2] [loongson] oprofile: avoid do_IRQ for perfcounter when the interrupt is from bonito
Quoted 5 lines · Wu Zhangjin
In loongson2f, the IP6 is shared by bonito and perfcounter, we need to avoid
do_IRQfor perfcounter when the interrupt is from bonito. This patch does it.Signed-off-by Wu Zhangjin <[email protected]>
Queued for 2.6.33. Thanks!
Ralf
Ralf Baechle
AppliedRe: [PATCH -queue 1/2] [loongson] add basic loongson-2f support
In reply to Wu ZhangjinQuoted 14 lines · Wu Zhangjin
Loongson2F has built-in DDR2 and PCIX controller. The PCIX controller have a similar programming interface with FPGA northbridge used in Loongson2E.
The main differences between loongson-2e and loongson-2f include:
1. loongson-2f has an extra address windows configuration module, which can be used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space.
2. loongson-2f support 8 levels of software configurable cpu frequency, which can be configured via a
register(LOONGSON_CHIPCFG0). the coming cpufreq and standby support are based on this feature.
Quoted 5 lines
herein, the module and the corresponding operations are abstracted to
loongson.h.besides, the other loongson2f-specific source code are added here, including gcc 4.4 support, pci memory space, pci io space, dma address.
Queued for 2.6.33. Thanks!
Ralf